/*
 * Generated by gen_defines.py
 *
 * DTS input file:
 *   D:/Zephyr/workspace/my_projects/my_nucleo_f429zi_tcpdata-50kcack/build/zephyr/zephyr.dts.pre
 *
 * Directories with bindings:
 *   $ZEPHYR_BASE\dts\bindings
 *
 * Node dependency ordering (ordinal and path):
 *   0   /
 *   1   /aliases
 *   2   /chosen
 *   3   /connector
 *   4   /soc
 *   5   /soc/interrupt-controller@e000e100
 *   6   /clocks
 *   7   /clocks/clk-hse
 *   8   /clocks/pll
 *   9   /soc/rcc@40023800
 *   10  /soc/pin-controller@40020000
 *   11  /soc/pin-controller@40020000/adc1_in0_pa0
 *   12  /soc/adc@40012000
 *   13  /soc/flash-controller@40023c00
 *   14  /soc/flash-controller@40023c00/flash@1fff7a00
 *   15  /soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout
 *   16  /soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout/ts-cal1@2c
 *   17  /soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout/ts-cal2@2e
 *   18  /dietemp
 *   19  /memory@10000000
 *   20  /memory@20000000
 *   21  /soc/pin-controller@40020000/gpio@40020400
 *   22  /soc/pin-controller@40020000/i2c1_scl_pb8
 *   23  /soc/pin-controller@40020000/i2c1_sda_pb9
 *   24  /soc/i2c@40005400
 *   25  /smbus1
 *   26  /soc/pin-controller@40020000/i2c2_scl_pb10
 *   27  /soc/pin-controller@40020000/i2c2_sda_pb11
 *   28  /soc/i2c@40005800
 *   29  /smbus2
 *   30  /soc/i2c@40005c00
 *   31  /smbus3
 *   32  /vbat
 *   33  /soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout/vrefint@2a
 *   34  /vref
 *   35  /clocks/clk-hsi
 *   36  /clocks/clk-lse
 *   37  /clocks/clk-lsi
 *   38  /clocks/plli2s
 *   39  /clocks/pllsai
 *   40  /cpus
 *   41  /cpus/power-states
 *   42  /cpus/power-states/stop
 *   43  /cpus/cpu@0
 *   44  /soc/pin-controller@40020000/gpio@40020800
 *   45  /gpio_keys
 *   46  /gpio_keys/button
 *   47  /leds
 *   48  /leds/led_1
 *   49  /leds/led_2
 *   50  /leds/led_3
 *   51  /mcos
 *   52  /mcos/mco1
 *   53  /mcos/mco2
 *   54  /soc/pin-controller@40020000/gpio@40020000
 *   55  /power@40007000
 *   56  /power@40007000/wkup-pin@1
 *   57  /soc/adc@40012100
 *   58  /soc/adc@40012200
 *   59  /soc/can@40006400
 *   60  /soc/can@40006800
 *   61  /soc/pin-controller@40020000/dac_out1_pa4
 *   62  /soc/dac@40007400
 *   63  /soc/rcc@40023800/reset-controller
 *   64  /soc/display-controller@40016800
 *   65  /soc/dma@40026000
 *   66  /soc/i2s@40003800
 *   67  /soc/i2s@40003c00
 *   68  /soc/interrupt-controller@40013c00
 *   69  /soc/memory@40024000
 *   70  /soc/rng@50060800
 *   71  /soc/sdmmc@40012c00
 *   72  /soc/serial@40004400
 *   73  /soc/pin-controller@40020000/usart3_rx_pd9
 *   74  /soc/pin-controller@40020000/usart3_tx_pd8
 *   75  /soc/serial@40004800
 *   76  /soc/serial@40004c00
 *   77  /soc/serial@40005000
 *   78  /soc/serial@40007800
 *   79  /soc/serial@40007c00
 *   80  /soc/serial@40011000
 *   81  /soc/pin-controller@40020000/usart6_rx_pg9
 *   82  /soc/pin-controller@40020000/usart6_tx_pg14
 *   83  /soc/serial@40011400
 *   84  /soc/spi@40003800
 *   85  /soc/spi@40003c00
 *   86  /soc/pin-controller@40020000/gpio@40020c00
 *   87  /soc/pin-controller@40020000/spi1_miso_pa6
 *   88  /soc/pin-controller@40020000/spi1_mosi_pa7
 *   89  /soc/pin-controller@40020000/spi1_sck_pa5
 *   90  /soc/spi@40013000
 *   91  /soc/spi@40013400
 *   92  /soc/spi@40015000
 *   93  /soc/spi@40015400
 *   94  /soc/timer@e000e010
 *   95  /otghs_fs_phy
 *   96  /soc/usb@40040000
 *   97  /otgfs_phy
 *   98  /soc/pin-controller@40020000/usb_otg_fs_dm_pa11
 *   99  /soc/pin-controller@40020000/usb_otg_fs_dp_pa12
 *   100 /soc/usb@50000000
 *   101 /soc/watchdog@40002c00
 *   102 /soc/watchdog@40003000
 *   103 /soc/pin-controller@40020000/eth_crs_dv_pa7
 *   104 /soc/pin-controller@40020000/eth_ref_clk_pa1
 *   105 /soc/pin-controller@40020000/eth_rxd0_pc4
 *   106 /soc/pin-controller@40020000/eth_rxd1_pc5
 *   107 /soc/pin-controller@40020000/eth_tx_en_pg11
 *   108 /soc/pin-controller@40020000/eth_txd0_pg13
 *   109 /soc/pin-controller@40020000/eth_txd1_pb13
 *   110 /soc/ethernet@40028000
 *   111 /soc/pin-controller@40020000/eth_mdc_pc1
 *   112 /soc/pin-controller@40020000/eth_mdio_pa2
 *   113 /soc/ethernet@40028000/mdio
 *   114 /soc/ethernet@40028000/mdio/ethernet-phy@0
 *   115 /soc/flash-controller@40023c00/flash@1fff7800
 *   116 /soc/flash-controller@40023c00/flash@8000000
 *   117 /soc/flash-controller@40023c00/flash@8000000/partitions
 *   118 /soc/flash-controller@40023c00/flash@8000000/partitions/partition@0
 *   119 /soc/flash-controller@40023c00/flash@8000000/partitions/partition@20000
 *   120 /soc/flash-controller@40023c00/flash@8000000/partitions/partition@60000
 *   121 /soc/flash-controller@40023c00/flash@8000000/partitions/partition@a0000
 *   122 /soc/memory-controller@a0000000
 *   123 /soc/memory-controller@a0000000/sdram
 *   124 /soc/pin-controller@40020000/gpio@40021000
 *   125 /soc/pin-controller@40020000/gpio@40021400
 *   126 /soc/pin-controller@40020000/gpio@40021800
 *   127 /soc/pin-controller@40020000/gpio@40021c00
 *   128 /soc/pin-controller@40020000/gpio@40022000
 *   129 /soc/pin-controller@40020000/gpio@40022400
 *   130 /soc/pin-controller@40020000/gpio@40022800
 *   131 /soc/rtc@40002800
 *   132 /soc/rtc@40002800/backup_regs
 *   133 /soc/dma@40026400
 *   134 /soc/sai1@40015800
 *   135 /soc/sai1@40015800/sai1a@4
 *   136 /soc/sai1@40015800/sai1b@24
 *   137 /soc/timers@40000000
 *   138 /soc/timers@40000000/counter
 *   139 /soc/timers@40000000/pwm
 *   140 /soc/timers@40000000/qdec
 *   141 /soc/timers@40000400
 *   142 /soc/timers@40000400/counter
 *   143 /soc/timers@40000400/pwm
 *   144 /soc/timers@40000400/qdec
 *   145 /soc/timers@40000800
 *   146 /soc/timers@40000800/counter
 *   147 /soc/timers@40000800/pwm
 *   148 /soc/timers@40000800/qdec
 *   149 /soc/timers@40000c00
 *   150 /soc/timers@40000c00/counter
 *   151 /soc/timers@40000c00/pwm
 *   152 /soc/timers@40000c00/qdec
 *   153 /soc/timers@40001000
 *   154 /soc/timers@40001000/counter
 *   155 /soc/timers@40001400
 *   156 /soc/timers@40001400/counter
 *   157 /soc/timers@40001800
 *   158 /soc/timers@40001800/counter
 *   159 /soc/timers@40001800/pwm
 *   160 /soc/timers@40001c00
 *   161 /soc/timers@40001c00/counter
 *   162 /soc/timers@40001c00/pwm
 *   163 /soc/timers@40002000
 *   164 /soc/timers@40002000/counter
 *   165 /soc/timers@40002000/pwm
 *   166 /soc/timers@40010000
 *   167 /soc/timers@40010000/counter
 *   168 /soc/pin-controller@40020000/tim1_ch3_pe13
 *   169 /soc/timers@40010000/pwm
 *   170 /soc/timers@40010000/qdec
 *   171 /soc/timers@40010400
 *   172 /soc/timers@40010400/counter
 *   173 /soc/timers@40010400/pwm
 *   174 /soc/timers@40010400/qdec
 *   175 /soc/timers@40014000
 *   176 /soc/timers@40014000/counter
 *   177 /soc/timers@40014000/pwm
 *   178 /soc/timers@40014400
 *   179 /soc/timers@40014400/counter
 *   180 /soc/timers@40014400/pwm
 *   181 /soc/timers@40014800
 *   182 /soc/timers@40014800/counter
 *   183 /soc/timers@40014800/pwm
 *
 * Definitions derived from these nodes in dependency order are next,
 * followed by /chosen nodes.
 */

/* Used to remove brackets from around a single argument */
#define DT_DEBRACKET_INTERNAL(...) __VA_ARGS__

/*
 * Devicetree node: /
 *
 * Node identifier: DT_N
 */

/* Node's full path: */
#define DT_N_PATH "/"

/* Node's name with unit-address: */
#define DT_N_FULL_NAME "/"
#define DT_N_FULL_NAME_UNQUOTED /
#define DT_N_FULL_NAME_TOKEN _
#define DT_N_FULL_NAME_UPPER_TOKEN _

/* Helpers for dealing with node labels: */
#define DT_N_NODELABEL_NUM 0
#define DT_N_FOREACH_NODELABEL(fn) 
#define DT_N_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_FOREACH_ANCESTOR(fn) 

/* Helper macros for child nodes of this node. */
#define DT_N_CHILD_NUM 20
#define DT_N_CHILD_NUM_STATUS_OKAY 16
#define DT_N_CHILD_UNIT_ADDR_INT_536870912 DT_N_S_memory_20000000
#define DT_N_CHILD_UNIT_ADDR_INT_1073770496 DT_N_S_power_40007000
#define DT_N_CHILD_UNIT_ADDR_INT_268435456 DT_N_S_memory_10000000
#define DT_N_FOREACH_CHILD(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_cpus) fn(DT_N_S_memory_20000000) fn(DT_N_S_clocks) fn(DT_N_S_mcos) fn(DT_N_S_power_40007000) fn(DT_N_S_dietemp) fn(DT_N_S_vref) fn(DT_N_S_vbat) fn(DT_N_S_otgfs_phy) fn(DT_N_S_smbus1) fn(DT_N_S_smbus2) fn(DT_N_S_smbus3) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_memory_10000000) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_gpio_keys)
#define DT_N_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_mcos) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_power_40007000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_dietemp) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vref) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vbat) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otgfs_phy) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_10000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys)
#define DT_N_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_mcos, __VA_ARGS__) fn(DT_N_S_power_40007000, __VA_ARGS__) fn(DT_N_S_dietemp, __VA_ARGS__) fn(DT_N_S_vref, __VA_ARGS__) fn(DT_N_S_vbat, __VA_ARGS__) fn(DT_N_S_otgfs_phy, __VA_ARGS__) fn(DT_N_S_smbus1, __VA_ARGS__) fn(DT_N_S_smbus2, __VA_ARGS__) fn(DT_N_S_smbus3, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_memory_10000000, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_mcos, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_power_40007000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_dietemp, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vref, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vbat, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otgfs_phy, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_10000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_cpus) fn(DT_N_S_memory_20000000) fn(DT_N_S_clocks) fn(DT_N_S_mcos) fn(DT_N_S_dietemp) fn(DT_N_S_vref) fn(DT_N_S_vbat) fn(DT_N_S_otgfs_phy) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_memory_10000000) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_gpio_keys)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_mcos) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_dietemp) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vref) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vbat) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otgfs_phy) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_10000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_mcos, __VA_ARGS__) fn(DT_N_S_dietemp, __VA_ARGS__) fn(DT_N_S_vref, __VA_ARGS__) fn(DT_N_S_vbat, __VA_ARGS__) fn(DT_N_S_otgfs_phy, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_memory_10000000, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_mcos, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_dietemp, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vref, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vbat, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otgfs_phy, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_10000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys, __VA_ARGS__)

/* Node's hash: */
#define DT_N_HASH il7asoJjJEMhngUeSt4tHVu8Zxx4EFG_FDeJfL3_oPE

/* Node's dependency ordinal: */
#define DT_N_ORD 0
#define DT_N_ORD_STR_SORTABLE 00000

/* Ordinals for what this node depends on directly: */
#define DT_N_REQUIRES_ORDS /* nothing */

/* Ordinals for what depends directly on this node: */
#define DT_N_SUPPORTS_ORDS \
	1, /* /aliases */ \
	2, /* /chosen */ \
	3, /* /connector */ \
	4, /* /soc */ \
	6, /* /clocks */ \
	18, /* /dietemp */ \
	19, /* /memory@10000000 */ \
	20, /* /memory@20000000 */ \
	25, /* /smbus1 */ \
	29, /* /smbus2 */ \
	31, /* /smbus3 */ \
	32, /* /vbat */ \
	34, /* /vref */ \
	40, /* /cpus */ \
	45, /* /gpio_keys */ \
	47, /* /leds */ \
	51, /* /mcos */ \
	55, /* /power@40007000 */ \
	95, /* /otghs_fs_phy */ \
	97, /* /otgfs_phy */

/* Existence and alternate IDs: */
#define DT_N_EXISTS 1
#define DT_N_INST_0_st_my_nucleo_f429zi DT_N

/* Macros for properties that are special in the specification: */
#define DT_N_REG_NUM 0
#define DT_N_FOREACH_REG(fn) 
#define DT_N_FOREACH_REG_SEP(fn, sep) 
#define DT_N_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_RANGES_NUM 0
#define DT_N_FOREACH_RANGE(fn) 
#define DT_N_IRQ_NUM 0
#define DT_N_IRQ_LEVEL 0
#define DT_N_COMPAT_MATCHES_st_my_nucleo_f429zi 1
#define DT_N_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_COMPAT_MODEL_IDX_0 "my-nucleo-f429zi"
#define DT_N_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_P_compatible {"st,my-nucleo-f429zi"}
#define DT_N_P_compatible_IDX_0_EXISTS 1
#define DT_N_P_compatible_IDX_0 "st,my-nucleo-f429zi"
#define DT_N_P_compatible_IDX_0_STRING_UNQUOTED st,my-nucleo-f429zi
#define DT_N_P_compatible_IDX_0_STRING_TOKEN st_my_nucleo_f429zi
#define DT_N_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_MY_NUCLEO_F429ZI
#define DT_N_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N, compatible, 0)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N, compatible, 0)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N, compatible, 0, __VA_ARGS__)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N, compatible, 0, __VA_ARGS__)
#define DT_N_P_compatible_LEN 1
#define DT_N_P_compatible_EXISTS 1

/*
 * Devicetree node: /aliases
 *
 * Node identifier: DT_N_S_aliases
 */

/* Node's full path: */
#define DT_N_S_aliases_PATH "/aliases"

/* Node's name with unit-address: */
#define DT_N_S_aliases_FULL_NAME "aliases"
#define DT_N_S_aliases_FULL_NAME_UNQUOTED aliases
#define DT_N_S_aliases_FULL_NAME_TOKEN aliases
#define DT_N_S_aliases_FULL_NAME_UPPER_TOKEN ALIASES

/* Node parent (/) identifier: */
#define DT_N_S_aliases_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_aliases_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_aliases_NODELABEL_NUM 0
#define DT_N_S_aliases_FOREACH_NODELABEL(fn) 
#define DT_N_S_aliases_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_aliases_CHILD_NUM 0
#define DT_N_S_aliases_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_aliases_FOREACH_CHILD(fn) 
#define DT_N_S_aliases_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_aliases_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_aliases_HASH QavYY6yplHKhLPRKsRzaLCGlR0CWZ0JUNJakcBCfDXA

/* Node's dependency ordinal: */
#define DT_N_S_aliases_ORD 1
#define DT_N_S_aliases_ORD_STR_SORTABLE 00001

/* Ordinals for what this node depends on directly: */
#define DT_N_S_aliases_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_aliases_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_aliases_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_aliases_REG_NUM 0
#define DT_N_S_aliases_FOREACH_REG(fn) 
#define DT_N_S_aliases_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_aliases_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_aliases_RANGES_NUM 0
#define DT_N_S_aliases_FOREACH_RANGE(fn) 
#define DT_N_S_aliases_IRQ_NUM 0
#define DT_N_S_aliases_IRQ_LEVEL 0
#define DT_N_S_aliases_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_aliases_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /chosen
 *
 * Node identifier: DT_N_S_chosen
 */

/* Node's full path: */
#define DT_N_S_chosen_PATH "/chosen"

/* Node's name with unit-address: */
#define DT_N_S_chosen_FULL_NAME "chosen"
#define DT_N_S_chosen_FULL_NAME_UNQUOTED chosen
#define DT_N_S_chosen_FULL_NAME_TOKEN chosen
#define DT_N_S_chosen_FULL_NAME_UPPER_TOKEN CHOSEN

/* Node parent (/) identifier: */
#define DT_N_S_chosen_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_chosen_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_chosen_NODELABEL_NUM 0
#define DT_N_S_chosen_FOREACH_NODELABEL(fn) 
#define DT_N_S_chosen_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_chosen_CHILD_NUM 0
#define DT_N_S_chosen_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_chosen_FOREACH_CHILD(fn) 
#define DT_N_S_chosen_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_chosen_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_chosen_HASH qNExeeLInzqaWpm1KroyYDk4lRIxVO2ig78mq_hOnA8

/* Node's dependency ordinal: */
#define DT_N_S_chosen_ORD 2
#define DT_N_S_chosen_ORD_STR_SORTABLE 00002

/* Ordinals for what this node depends on directly: */
#define DT_N_S_chosen_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_chosen_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_chosen_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_chosen_REG_NUM 0
#define DT_N_S_chosen_FOREACH_REG(fn) 
#define DT_N_S_chosen_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_chosen_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_chosen_RANGES_NUM 0
#define DT_N_S_chosen_FOREACH_RANGE(fn) 
#define DT_N_S_chosen_IRQ_NUM 0
#define DT_N_S_chosen_IRQ_LEVEL 0
#define DT_N_S_chosen_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_chosen_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /connector
 *
 * Node identifier: DT_N_S_connector
 *
 * Binding (compatible = arduino-header-r3):
 *   $ZEPHYR_BASE\dts\bindings\gpio\arduino-header-r3.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_connector_PATH "/connector"

/* Node's name with unit-address: */
#define DT_N_S_connector_FULL_NAME "connector"
#define DT_N_S_connector_FULL_NAME_UNQUOTED connector
#define DT_N_S_connector_FULL_NAME_TOKEN connector
#define DT_N_S_connector_FULL_NAME_UPPER_TOKEN CONNECTOR

/* Node parent (/) identifier: */
#define DT_N_S_connector_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_connector_CHILD_IDX 17

/* Helpers for dealing with node labels: */
#define DT_N_S_connector_NODELABEL_NUM 1
#define DT_N_S_connector_FOREACH_NODELABEL(fn) fn(arduino_header)
#define DT_N_S_connector_FOREACH_NODELABEL_VARGS(fn, ...) fn(arduino_header, __VA_ARGS__)
#define DT_N_S_connector_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_connector_CHILD_NUM 0
#define DT_N_S_connector_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_connector_FOREACH_CHILD(fn) 
#define DT_N_S_connector_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_connector_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_connector_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_connector_HASH 1hNYiTso4N65bku_L_0pzRcHL_5NCz8DqiXd1i5KK7Q

/* Node's dependency ordinal: */
#define DT_N_S_connector_ORD 3
#define DT_N_S_connector_ORD_STR_SORTABLE 00003

/* Ordinals for what this node depends on directly: */
#define DT_N_S_connector_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_connector_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_connector_IDX_0_C_TOKEN arduino_header

/* Existence and alternate IDs: */
#define DT_N_S_connector_EXISTS 1
#define DT_N_INST_0_arduino_header_r3 DT_N_S_connector
#define DT_N_NODELABEL_arduino_header DT_N_S_connector

/* Macros for properties that are special in the specification: */
#define DT_N_S_connector_REG_NUM 0
#define DT_N_S_connector_FOREACH_REG(fn) 
#define DT_N_S_connector_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_connector_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_connector_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_connector_RANGES_NUM 0
#define DT_N_S_connector_FOREACH_RANGE(fn) 
#define DT_N_S_connector_IRQ_NUM 0
#define DT_N_S_connector_IRQ_LEVEL 0
#define DT_N_S_connector_COMPAT_MATCHES_arduino_header_r3 1
#define DT_N_S_connector_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_connector_PINCTRL_NUM 0

/* Map properties: */
#define DT_N_S_connector_P_gpio_map_LEN 22
#define DT_N_S_connector_P_gpio_map_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_0 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_0 3
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_0 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_0 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_IDX_0 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_IDX_0 3
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_IDX_0 3
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_IDX_0 3
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_IDX_0 4
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_IDX_0 5
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_IDX_0 5
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_IDX_0 10
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_IDX_0 6
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_IDX_0 9
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_IDX_0 7
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_IDX_0 14
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_IDX_0 8
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_IDX_0 15
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_IDX_0 9
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_IDX_0 13
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_IDX_0 10
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_IDX_0 14
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_CHILD_SPECIFIER_IDX_0 11
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_PARENT_SPECIFIER_IDX_0 11
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_CHILD_SPECIFIER_IDX_0 12
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_PARENT_SPECIFIER_IDX_0 9
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_CHILD_SPECIFIER_IDX_0 13
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_PARENT_SPECIFIER_IDX_0 13
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_CHILD_SPECIFIER_IDX_0 14
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_PARENT_SPECIFIER_IDX_0 12
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_CHILD_SPECIFIER_IDX_0 15
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_PARENT_SPECIFIER_IDX_0 15
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_CHILD_SPECIFIER_IDX_0 16
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_PARENT_SPECIFIER_IDX_0 14
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_CHILD_SPECIFIER_IDX_0 17
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_PARENT_SPECIFIER_IDX_0 7
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_CHILD_SPECIFIER_IDX_0 18
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_PARENT_SPECIFIER_IDX_0 6
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_CHILD_SPECIFIER_IDX_0 19
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_PARENT_SPECIFIER_IDX_0 5
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_CHILD_SPECIFIER_IDX_0 20
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_PARENT_SPECIFIER_IDX_0 9
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_CHILD_SPECIFIER_IDX_0 21
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_PARENT DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_PARENT_SPECIFIER_IDX_0 8
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_FOREACH_MAP_ENTRY(fn) fn(DT_N_S_connector, gpio_map, 0) \
	fn(DT_N_S_connector, gpio_map, 1) \
	fn(DT_N_S_connector, gpio_map, 2) \
	fn(DT_N_S_connector, gpio_map, 3) \
	fn(DT_N_S_connector, gpio_map, 4) \
	fn(DT_N_S_connector, gpio_map, 5) \
	fn(DT_N_S_connector, gpio_map, 6) \
	fn(DT_N_S_connector, gpio_map, 7) \
	fn(DT_N_S_connector, gpio_map, 8) \
	fn(DT_N_S_connector, gpio_map, 9) \
	fn(DT_N_S_connector, gpio_map, 10) \
	fn(DT_N_S_connector, gpio_map, 11) \
	fn(DT_N_S_connector, gpio_map, 12) \
	fn(DT_N_S_connector, gpio_map, 13) \
	fn(DT_N_S_connector, gpio_map, 14) \
	fn(DT_N_S_connector, gpio_map, 15) \
	fn(DT_N_S_connector, gpio_map, 16) \
	fn(DT_N_S_connector, gpio_map, 17) \
	fn(DT_N_S_connector, gpio_map, 18) \
	fn(DT_N_S_connector, gpio_map, 19) \
	fn(DT_N_S_connector, gpio_map, 20) \
	fn(DT_N_S_connector, gpio_map, 21)
#define DT_N_S_connector_P_gpio_map_FOREACH_MAP_ENTRY_SEP(fn, sep) fn(DT_N_S_connector, gpio_map, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 11) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 12) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 13) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 14) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 15) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 16) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 17) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 18) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 19) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 20) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 21)
#define DT_N_S_connector_P_gpio_map_FOREACH_MAP_ENTRY_VARGS(fn, ...) fn(DT_N_S_connector, gpio_map, 0, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 1, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 2, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 3, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 4, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 5, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 6, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 7, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 8, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 9, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 10, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 11, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 12, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 13, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 14, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 15, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 16, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 17, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 18, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 19, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 20, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 21, __VA_ARGS__)
#define DT_N_S_connector_P_gpio_map_FOREACH_MAP_ENTRY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_connector, gpio_map, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 16, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 17, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 18, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 19, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 20, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 21, __VA_ARGS__)

/* Generic property macros: */
#define DT_N_S_connector_P_gpio_map_mask {4294967295 /* 0xffffffff */, 4294967232 /* 0xffffffc0 */}
#define DT_N_S_connector_P_gpio_map_mask_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_mask_IDX_0 4294967295
#define DT_N_S_connector_P_gpio_map_mask_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_mask_IDX_1 4294967232
#define DT_N_S_connector_P_gpio_map_mask_FOREACH_PROP_ELEM(fn) fn(DT_N_S_connector, gpio_map_mask, 0) \
	fn(DT_N_S_connector, gpio_map_mask, 1)
#define DT_N_S_connector_P_gpio_map_mask_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_connector, gpio_map_mask, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map_mask, 1)
#define DT_N_S_connector_P_gpio_map_mask_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_connector, gpio_map_mask, 0, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map_mask, 1, __VA_ARGS__)
#define DT_N_S_connector_P_gpio_map_mask_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_connector, gpio_map_mask, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map_mask, 1, __VA_ARGS__)
#define DT_N_S_connector_P_gpio_map_mask_LEN 2
#define DT_N_S_connector_P_gpio_map_mask_EXISTS 1
#define DT_N_S_connector_P_gpio_map_pass_thru {0 /* 0x0 */, 63 /* 0x3f */}
#define DT_N_S_connector_P_gpio_map_pass_thru_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_pass_thru_IDX_0 0
#define DT_N_S_connector_P_gpio_map_pass_thru_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_pass_thru_IDX_1 63
#define DT_N_S_connector_P_gpio_map_pass_thru_FOREACH_PROP_ELEM(fn) fn(DT_N_S_connector, gpio_map_pass_thru, 0) \
	fn(DT_N_S_connector, gpio_map_pass_thru, 1)
#define DT_N_S_connector_P_gpio_map_pass_thru_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_connector, gpio_map_pass_thru, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map_pass_thru, 1)
#define DT_N_S_connector_P_gpio_map_pass_thru_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_connector, gpio_map_pass_thru, 0, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map_pass_thru, 1, __VA_ARGS__)
#define DT_N_S_connector_P_gpio_map_pass_thru_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_connector, gpio_map_pass_thru, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map_pass_thru, 1, __VA_ARGS__)
#define DT_N_S_connector_P_gpio_map_pass_thru_LEN 2
#define DT_N_S_connector_P_gpio_map_pass_thru_EXISTS 1
#define DT_N_S_connector_P_compatible {"arduino-header-r3"}
#define DT_N_S_connector_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_connector_P_compatible_IDX_0 "arduino-header-r3"
#define DT_N_S_connector_P_compatible_IDX_0_STRING_UNQUOTED arduino-header-r3
#define DT_N_S_connector_P_compatible_IDX_0_STRING_TOKEN arduino_header_r3
#define DT_N_S_connector_P_compatible_IDX_0_STRING_UPPER_TOKEN ARDUINO_HEADER_R3
#define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_connector, compatible, 0)
#define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_connector, compatible, 0)
#define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_connector, compatible, 0, __VA_ARGS__)
#define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_connector, compatible, 0, __VA_ARGS__)
#define DT_N_S_connector_P_compatible_LEN 1
#define DT_N_S_connector_P_compatible_EXISTS 1
#define DT_N_S_connector_P_dma_coherent 0
#define DT_N_S_connector_P_dma_coherent_EXISTS 1
#define DT_N_S_connector_P_zephyr_deferred_init 0
#define DT_N_S_connector_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_connector_P_wakeup_source 0
#define DT_N_S_connector_P_wakeup_source_EXISTS 1
#define DT_N_S_connector_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_connector_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc
 *
 * Node identifier: DT_N_S_soc
 */

/* Node's full path: */
#define DT_N_S_soc_PATH "/soc"

/* Node's name with unit-address: */
#define DT_N_S_soc_FULL_NAME "soc"
#define DT_N_S_soc_FULL_NAME_UNQUOTED soc
#define DT_N_S_soc_FULL_NAME_TOKEN soc
#define DT_N_S_soc_FULL_NAME_UPPER_TOKEN SOC

/* Node parent (/) identifier: */
#define DT_N_S_soc_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_NODELABEL_NUM 0
#define DT_N_S_soc_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_CHILD_NUM 59
#define DT_N_S_soc_CHILD_NUM_STATUS_OKAY 20
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_3758153984 DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_3758153744 DT_N_S_soc_S_timer_e000e010
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073888256 DT_N_S_soc_S_flash_controller_40023c00
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073887232 DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073822720 DT_N_S_soc_S_interrupt_controller_40013c00
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073872896 DT_N_S_soc_S_pin_controller_40020000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073754112 DT_N_S_soc_S_watchdog_40003000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073753088 DT_N_S_soc_S_watchdog_40002c00
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073811456 DT_N_S_soc_S_serial_40011000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073759232 DT_N_S_soc_S_serial_40004400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073812480 DT_N_S_soc_S_serial_40011400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073763328 DT_N_S_soc_S_i2c_40005400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073764352 DT_N_S_soc_S_i2c_40005800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073765376 DT_N_S_soc_S_i2c_40005c00
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073819648 DT_N_S_soc_S_spi_40013000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1342177280 DT_N_S_soc_S_usb_50000000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073807360 DT_N_S_soc_S_timers_40010000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073741824 DT_N_S_soc_S_timers_40000000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073742848 DT_N_S_soc_S_timers_40000400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073743872 DT_N_S_soc_S_timers_40000800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073744896 DT_N_S_soc_S_timers_40000c00
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073823744 DT_N_S_soc_S_timers_40014000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073824768 DT_N_S_soc_S_timers_40014400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073825792 DT_N_S_soc_S_timers_40014800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073752064 DT_N_S_soc_S_rtc_40002800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073815552 DT_N_S_soc_S_adc_40012000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073897472 DT_N_S_soc_S_dma_40026000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073898496 DT_N_S_soc_S_dma_40026400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073818624 DT_N_S_soc_S_sdmmc_40012c00
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073820672 DT_N_S_soc_S_spi_40013400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073760256 DT_N_S_soc_S_serial_40004800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073761280 DT_N_S_soc_S_serial_40004c00
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073762304 DT_N_S_soc_S_serial_40005000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073745920 DT_N_S_soc_S_timers_40001000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073746944 DT_N_S_soc_S_timers_40001400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073808384 DT_N_S_soc_S_timers_40010400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073747968 DT_N_S_soc_S_timers_40001800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073748992 DT_N_S_soc_S_timers_40001c00
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073750016 DT_N_S_soc_S_timers_40002000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1074003968 DT_N_S_soc_S_usb_40040000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073767424 DT_N_S_soc_S_can_40006400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073768448 DT_N_S_soc_S_can_40006800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1342572544 DT_N_S_soc_S_rng_50060800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073889280 DT_N_S_soc_S_memory_40024000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073815808 DT_N_S_soc_S_adc_40012100
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073816064 DT_N_S_soc_S_adc_40012200
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073771520 DT_N_S_soc_S_dac_40007400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073905664 DT_N_S_soc_S_ethernet_40028000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073772544 DT_N_S_soc_S_serial_40007800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073773568 DT_N_S_soc_S_serial_40007c00
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073827840 DT_N_S_soc_S_spi_40015000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073828864 DT_N_S_soc_S_spi_40015400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_2684354560 DT_N_S_soc_S_memory_controller_a0000000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073829888 DT_N_S_soc_S_sai1_40015800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073833984 DT_N_S_soc_S_display_controller_40016800
#define DT_N_S_soc_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_flash_controller_40023c00) fn(DT_N_S_soc_S_rcc_40023800) fn(DT_N_S_soc_S_interrupt_controller_40013c00) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc_S_watchdog_40003000) fn(DT_N_S_soc_S_watchdog_40002c00) fn(DT_N_S_soc_S_serial_40011000) fn(DT_N_S_soc_S_serial_40004400) fn(DT_N_S_soc_S_serial_40011400) fn(DT_N_S_soc_S_i2c_40005400) fn(DT_N_S_soc_S_i2c_40005800) fn(DT_N_S_soc_S_i2c_40005c00) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_usb_50000000) fn(DT_N_S_soc_S_timers_40010000) fn(DT_N_S_soc_S_timers_40000000) fn(DT_N_S_soc_S_timers_40000400) fn(DT_N_S_soc_S_timers_40000800) fn(DT_N_S_soc_S_timers_40000c00) fn(DT_N_S_soc_S_timers_40014000) fn(DT_N_S_soc_S_timers_40014400) fn(DT_N_S_soc_S_timers_40014800) fn(DT_N_S_soc_S_rtc_40002800) fn(DT_N_S_soc_S_adc_40012000) fn(DT_N_S_soc_S_dma_40026000) fn(DT_N_S_soc_S_dma_40026400) fn(DT_N_S_soc_S_sdmmc_40012c00) fn(DT_N_S_soc_S_spi_40003800) fn(DT_N_S_soc_S_spi_40003c00) fn(DT_N_S_soc_S_spi_40013400) fn(DT_N_S_soc_S_i2s_40003800) fn(DT_N_S_soc_S_i2s_40003c00) fn(DT_N_S_soc_S_serial_40004800) fn(DT_N_S_soc_S_serial_40004c00) fn(DT_N_S_soc_S_serial_40005000) fn(DT_N_S_soc_S_timers_40001000) fn(DT_N_S_soc_S_timers_40001400) fn(DT_N_S_soc_S_timers_40010400) fn(DT_N_S_soc_S_timers_40001800) fn(DT_N_S_soc_S_timers_40001c00) fn(DT_N_S_soc_S_timers_40002000) fn(DT_N_S_soc_S_usb_40040000) fn(DT_N_S_soc_S_can_40006400) fn(DT_N_S_soc_S_can_40006800) fn(DT_N_S_soc_S_rng_50060800) fn(DT_N_S_soc_S_memory_40024000) fn(DT_N_S_soc_S_adc_40012100) fn(DT_N_S_soc_S_adc_40012200) fn(DT_N_S_soc_S_dac_40007400) fn(DT_N_S_soc_S_ethernet_40028000) fn(DT_N_S_soc_S_serial_40007800) fn(DT_N_S_soc_S_serial_40007c00) fn(DT_N_S_soc_S_spi_40015000) fn(DT_N_S_soc_S_spi_40015400) fn(DT_N_S_soc_S_memory_controller_a0000000) fn(DT_N_S_soc_S_sai1_40015800) fn(DT_N_S_soc_S_display_controller_40016800)
#define DT_N_S_soc_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rcc_40023800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_interrupt_controller_40013c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_40003000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_40002c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40011000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40011400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40013000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usb_50000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rtc_40002800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40012000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dma_40026000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dma_40026400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sdmmc_40012c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40003800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40003c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40013400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2s_40003800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2s_40003c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40005000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40002000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usb_40040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_can_40006400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_can_40006800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rng_50060800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_40024000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40012100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40012200) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dac_40007400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ethernet_40028000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40007800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40007c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40015000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40015400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_controller_a0000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sai1_40015800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_display_controller_40016800)
#define DT_N_S_soc_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_40023800, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_40013c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_40003000, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_40002c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005800, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005c00, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_40002800, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40012000, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40026000, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40026400, __VA_ARGS__) fn(DT_N_S_soc_S_sdmmc_40012c00, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003c00, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013400, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40003c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40005000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40040000, __VA_ARGS__) fn(DT_N_S_soc_S_can_40006400, __VA_ARGS__) fn(DT_N_S_soc_S_can_40006800, __VA_ARGS__) fn(DT_N_S_soc_S_rng_50060800, __VA_ARGS__) fn(DT_N_S_soc_S_memory_40024000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40012100, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40012200, __VA_ARGS__) fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) fn(DT_N_S_soc_S_ethernet_40028000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007c00, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40015400, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_a0000000, __VA_ARGS__) fn(DT_N_S_soc_S_sai1_40015800, __VA_ARGS__) fn(DT_N_S_soc_S_display_controller_40016800, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rcc_40023800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_interrupt_controller_40013c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_40003000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_40002c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40011000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usb_50000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rtc_40002800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40012000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dma_40026000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dma_40026400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sdmmc_40012c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40003800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40003c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40013400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2s_40003800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2s_40003c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40005000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40002000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usb_40040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_can_40006400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_can_40006800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rng_50060800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_40024000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40012100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40012200, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ethernet_40028000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40007800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40007c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40015000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40015400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_controller_a0000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sai1_40015800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_display_controller_40016800, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_flash_controller_40023c00) fn(DT_N_S_soc_S_rcc_40023800) fn(DT_N_S_soc_S_interrupt_controller_40013c00) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc_S_watchdog_40003000) fn(DT_N_S_soc_S_serial_40011400) fn(DT_N_S_soc_S_i2c_40005400) fn(DT_N_S_soc_S_i2c_40005800) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_usb_50000000) fn(DT_N_S_soc_S_timers_40010000) fn(DT_N_S_soc_S_rtc_40002800) fn(DT_N_S_soc_S_adc_40012000) fn(DT_N_S_soc_S_dma_40026400) fn(DT_N_S_soc_S_serial_40004800) fn(DT_N_S_soc_S_rng_50060800) fn(DT_N_S_soc_S_dac_40007400) fn(DT_N_S_soc_S_ethernet_40028000)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rcc_40023800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_interrupt_controller_40013c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_40003000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40011400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40013000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usb_50000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rtc_40002800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40012000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dma_40026400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rng_50060800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dac_40007400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ethernet_40028000)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_40023800, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_40013c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_40003000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005800, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_40002800, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40012000, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40026400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004800, __VA_ARGS__) fn(DT_N_S_soc_S_rng_50060800, __VA_ARGS__) fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) fn(DT_N_S_soc_S_ethernet_40028000, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rcc_40023800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_interrupt_controller_40013c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_40003000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usb_50000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rtc_40002800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40012000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dma_40026400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rng_50060800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ethernet_40028000, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_HASH DcVqqq9YzG86l3_Hk7pNncUh2rnHG8USjbVY6wBdFts

/* Node's dependency ordinal: */
#define DT_N_S_soc_ORD 4
#define DT_N_S_soc_ORD_STR_SORTABLE 00004

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_SUPPORTS_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	10, /* /soc/pin-controller@40020000 */ \
	12, /* /soc/adc@40012000 */ \
	13, /* /soc/flash-controller@40023c00 */ \
	24, /* /soc/i2c@40005400 */ \
	28, /* /soc/i2c@40005800 */ \
	30, /* /soc/i2c@40005c00 */ \
	57, /* /soc/adc@40012100 */ \
	58, /* /soc/adc@40012200 */ \
	59, /* /soc/can@40006400 */ \
	60, /* /soc/can@40006800 */ \
	62, /* /soc/dac@40007400 */ \
	64, /* /soc/display-controller@40016800 */ \
	65, /* /soc/dma@40026000 */ \
	66, /* /soc/i2s@40003800 */ \
	67, /* /soc/i2s@40003c00 */ \
	68, /* /soc/interrupt-controller@40013c00 */ \
	69, /* /soc/memory@40024000 */ \
	70, /* /soc/rng@50060800 */ \
	71, /* /soc/sdmmc@40012c00 */ \
	72, /* /soc/serial@40004400 */ \
	75, /* /soc/serial@40004800 */ \
	76, /* /soc/serial@40004c00 */ \
	77, /* /soc/serial@40005000 */ \
	78, /* /soc/serial@40007800 */ \
	79, /* /soc/serial@40007c00 */ \
	80, /* /soc/serial@40011000 */ \
	83, /* /soc/serial@40011400 */ \
	84, /* /soc/spi@40003800 */ \
	85, /* /soc/spi@40003c00 */ \
	90, /* /soc/spi@40013000 */ \
	91, /* /soc/spi@40013400 */ \
	92, /* /soc/spi@40015000 */ \
	93, /* /soc/spi@40015400 */ \
	94, /* /soc/timer@e000e010 */ \
	96, /* /soc/usb@40040000 */ \
	100, /* /soc/usb@50000000 */ \
	101, /* /soc/watchdog@40002c00 */ \
	102, /* /soc/watchdog@40003000 */ \
	110, /* /soc/ethernet@40028000 */ \
	122, /* /soc/memory-controller@a0000000 */ \
	131, /* /soc/rtc@40002800 */ \
	133, /* /soc/dma@40026400 */ \
	134, /* /soc/sai1@40015800 */ \
	137, /* /soc/timers@40000000 */ \
	141, /* /soc/timers@40000400 */ \
	145, /* /soc/timers@40000800 */ \
	149, /* /soc/timers@40000c00 */ \
	153, /* /soc/timers@40001000 */ \
	155, /* /soc/timers@40001400 */ \
	157, /* /soc/timers@40001800 */ \
	160, /* /soc/timers@40001c00 */ \
	163, /* /soc/timers@40002000 */ \
	166, /* /soc/timers@40010000 */ \
	171, /* /soc/timers@40010400 */ \
	175, /* /soc/timers@40014000 */ \
	178, /* /soc/timers@40014400 */ \
	181, /* /soc/timers@40014800 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_EXISTS 1
#define DT_N_INST_0_st_stm32f429 DT_N_S_soc
#define DT_N_INST_0_st_stm32f4   DT_N_S_soc
#define DT_N_INST_0_simple_bus   DT_N_S_soc

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_REG_NUM 0
#define DT_N_S_soc_FOREACH_REG(fn) 
#define DT_N_S_soc_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_RANGES_NUM 0
#define DT_N_S_soc_FOREACH_RANGE(fn) 
#define DT_N_S_soc_IRQ_NUM 0
#define DT_N_S_soc_IRQ_LEVEL 0
#define DT_N_S_soc_COMPAT_MATCHES_st_stm32f429 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_COMPAT_MODEL_IDX_0 "stm32f429"
#define DT_N_S_soc_COMPAT_MATCHES_st_stm32f4 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_COMPAT_MODEL_IDX_1 "stm32f4"
#define DT_N_S_soc_COMPAT_MATCHES_simple_bus 1
#define DT_N_S_soc_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_P_ranges_EXISTS 1
#define DT_N_S_soc_P_compatible {"st,stm32f429", "st,stm32f4", "simple-bus"}
#define DT_N_S_soc_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_0 "st,stm32f429"
#define DT_N_S_soc_P_compatible_IDX_0_STRING_UNQUOTED st,stm32f429
#define DT_N_S_soc_P_compatible_IDX_0_STRING_TOKEN st_stm32f429
#define DT_N_S_soc_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32F429
#define DT_N_S_soc_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_1 "st,stm32f4"
#define DT_N_S_soc_P_compatible_IDX_1_STRING_UNQUOTED st,stm32f4
#define DT_N_S_soc_P_compatible_IDX_1_STRING_TOKEN st_stm32f4
#define DT_N_S_soc_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32F4
#define DT_N_S_soc_P_compatible_IDX_2_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_2 "simple-bus"
#define DT_N_S_soc_P_compatible_IDX_2_STRING_UNQUOTED simple-bus
#define DT_N_S_soc_P_compatible_IDX_2_STRING_TOKEN simple_bus
#define DT_N_S_soc_P_compatible_IDX_2_STRING_UPPER_TOKEN SIMPLE_BUS
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc, compatible, 0) \
	fn(DT_N_S_soc, compatible, 1) \
	fn(DT_N_S_soc, compatible, 2)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 2)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc, compatible, 1, __VA_ARGS__) \
	fn(DT_N_S_soc, compatible, 2, __VA_ARGS__)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 2, __VA_ARGS__)
#define DT_N_S_soc_P_compatible_LEN 3
#define DT_N_S_soc_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/interrupt-controller@e000e100
 *
 * Node identifier: DT_N_S_soc_S_interrupt_controller_e000e100
 *
 * Binding (compatible = arm,v7m-nvic):
 *   $ZEPHYR_BASE\dts\bindings\interrupt-controller\arm,v7m-nvic.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PATH "/soc/interrupt-controller@e000e100"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME "interrupt-controller@e000e100"
#define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME_UNQUOTED interrupt-controller@e000e100
#define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME_TOKEN interrupt_controller_e000e100
#define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME_UPPER_TOKEN INTERRUPT_CONTROLLER_E000E100

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_NODELABEL_NUM 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_NODELABEL(fn) fn(nvic)
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_NODELABEL_VARGS(fn, ...) fn(nvic, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_NUM 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_HASH MNKByYDCdVxyLwiy4A_bv2jZfVhfDT01mZ2_1uEhUYQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_ORD 5
#define DT_N_S_soc_S_interrupt_controller_e000e100_ORD_STR_SORTABLE 00005

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_SUPPORTS_ORDS \
	12, /* /soc/adc@40012000 */ \
	13, /* /soc/flash-controller@40023c00 */ \
	24, /* /soc/i2c@40005400 */ \
	28, /* /soc/i2c@40005800 */ \
	30, /* /soc/i2c@40005c00 */ \
	57, /* /soc/adc@40012100 */ \
	58, /* /soc/adc@40012200 */ \
	59, /* /soc/can@40006400 */ \
	60, /* /soc/can@40006800 */ \
	64, /* /soc/display-controller@40016800 */ \
	65, /* /soc/dma@40026000 */ \
	66, /* /soc/i2s@40003800 */ \
	67, /* /soc/i2s@40003c00 */ \
	68, /* /soc/interrupt-controller@40013c00 */ \
	70, /* /soc/rng@50060800 */ \
	71, /* /soc/sdmmc@40012c00 */ \
	72, /* /soc/serial@40004400 */ \
	75, /* /soc/serial@40004800 */ \
	76, /* /soc/serial@40004c00 */ \
	77, /* /soc/serial@40005000 */ \
	78, /* /soc/serial@40007800 */ \
	79, /* /soc/serial@40007c00 */ \
	80, /* /soc/serial@40011000 */ \
	83, /* /soc/serial@40011400 */ \
	84, /* /soc/spi@40003800 */ \
	85, /* /soc/spi@40003c00 */ \
	90, /* /soc/spi@40013000 */ \
	91, /* /soc/spi@40013400 */ \
	92, /* /soc/spi@40015000 */ \
	93, /* /soc/spi@40015400 */ \
	96, /* /soc/usb@40040000 */ \
	100, /* /soc/usb@50000000 */ \
	101, /* /soc/watchdog@40002c00 */ \
	110, /* /soc/ethernet@40028000 */ \
	131, /* /soc/rtc@40002800 */ \
	133, /* /soc/dma@40026400 */ \
	137, /* /soc/timers@40000000 */ \
	141, /* /soc/timers@40000400 */ \
	145, /* /soc/timers@40000800 */ \
	149, /* /soc/timers@40000c00 */ \
	153, /* /soc/timers@40001000 */ \
	155, /* /soc/timers@40001400 */ \
	157, /* /soc/timers@40001800 */ \
	160, /* /soc/timers@40001c00 */ \
	163, /* /soc/timers@40002000 */ \
	166, /* /soc/timers@40010000 */ \
	171, /* /soc/timers@40010400 */ \
	175, /* /soc/timers@40014000 */ \
	178, /* /soc/timers@40014400 */ \
	181, /* /soc/timers@40014800 */
#define DT_N_NODELABEL_DT_N_S_soc_S_interrupt_controller_e000e100_IDX_0_C_TOKEN nvic

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_EXISTS 1
#define DT_N_INST_0_arm_v7m_nvic DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_NODELABEL_nvic      DT_N_S_soc_S_interrupt_controller_e000e100

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_NUM 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_ADDRESS 3758153984 /* 0xe000e100 */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_SIZE 3072 /* 0xc00 */
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_REG(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100, 0)
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100, 0)
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_e000e100_RANGES_NUM 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_NUM 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_LEVEL 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MATCHES_arm_v7m_nvic 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MODEL_IDX_0 "v7m-nvic"
#define DT_N_S_soc_S_interrupt_controller_e000e100_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg {3758153984 /* 0xe000e100 */, 3072 /* 0xc00 */}
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0 3758153984
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1 3072
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits 4
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible {"arm,v7m-nvic"}
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0 "arm,v7m-nvic"
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UNQUOTED arm,v7m-nvic
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_TOKEN arm_v7m_nvic
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_V7M_NVIC
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_LEN 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_dma_coherent 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /clocks
 *
 * Node identifier: DT_N_S_clocks
 */

/* Node's full path: */
#define DT_N_S_clocks_PATH "/clocks"

/* Node's name with unit-address: */
#define DT_N_S_clocks_FULL_NAME "clocks"
#define DT_N_S_clocks_FULL_NAME_UNQUOTED clocks
#define DT_N_S_clocks_FULL_NAME_TOKEN clocks
#define DT_N_S_clocks_FULL_NAME_UPPER_TOKEN CLOCKS

/* Node parent (/) identifier: */
#define DT_N_S_clocks_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_clocks_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_clocks_NODELABEL_NUM 0
#define DT_N_S_clocks_FOREACH_NODELABEL(fn) 
#define DT_N_S_clocks_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_clocks_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_clocks_CHILD_NUM 7
#define DT_N_S_clocks_CHILD_NUM_STATUS_OKAY 3
#define DT_N_S_clocks_FOREACH_CHILD(fn) fn(DT_N_S_clocks_S_clk_hse) fn(DT_N_S_clocks_S_clk_hsi) fn(DT_N_S_clocks_S_clk_lse) fn(DT_N_S_clocks_S_clk_lsi) fn(DT_N_S_clocks_S_pll) fn(DT_N_S_clocks_S_plli2s) fn(DT_N_S_clocks_S_pllsai)
#define DT_N_S_clocks_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hse) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_hsi) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_lse) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_lsi) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_pll) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_plli2s) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_pllsai)
#define DT_N_S_clocks_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lsi, __VA_ARGS__) fn(DT_N_S_clocks_S_pll, __VA_ARGS__) fn(DT_N_S_clocks_S_plli2s, __VA_ARGS__) fn(DT_N_S_clocks_S_pllsai, __VA_ARGS__)
#define DT_N_S_clocks_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_hsi, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_lse, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_lsi, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_pll, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_plli2s, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_pllsai, __VA_ARGS__)
#define DT_N_S_clocks_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_clocks_S_clk_hse) fn(DT_N_S_clocks_S_clk_lsi) fn(DT_N_S_clocks_S_pll)
#define DT_N_S_clocks_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hse) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_lsi) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_pll)
#define DT_N_S_clocks_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lsi, __VA_ARGS__) fn(DT_N_S_clocks_S_pll, __VA_ARGS__)
#define DT_N_S_clocks_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_lsi, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_pll, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_clocks_HASH 3P3fmk_q5wPvaymGA6NeomHHBb_cCfQX2PaKw_k1t_w

/* Node's dependency ordinal: */
#define DT_N_S_clocks_ORD 6
#define DT_N_S_clocks_ORD_STR_SORTABLE 00006

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clocks_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clocks_SUPPORTS_ORDS \
	7, /* /clocks/clk-hse */ \
	8, /* /clocks/pll */ \
	35, /* /clocks/clk-hsi */ \
	36, /* /clocks/clk-lse */ \
	37, /* /clocks/clk-lsi */ \
	38, /* /clocks/plli2s */ \
	39, /* /clocks/pllsai */

/* Existence and alternate IDs: */
#define DT_N_S_clocks_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_clocks_REG_NUM 0
#define DT_N_S_clocks_FOREACH_REG(fn) 
#define DT_N_S_clocks_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_clocks_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_clocks_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_RANGES_NUM 0
#define DT_N_S_clocks_FOREACH_RANGE(fn) 
#define DT_N_S_clocks_IRQ_NUM 0
#define DT_N_S_clocks_IRQ_LEVEL 0
#define DT_N_S_clocks_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clocks_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /clocks/clk-hse
 *
 * Node identifier: DT_N_S_clocks_S_clk_hse
 *
 * Binding (compatible = st,stm32-hse-clock):
 *   $ZEPHYR_BASE\dts\bindings\clock\st,stm32-hse-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_clocks_S_clk_hse_PATH "/clocks/clk-hse"

/* Node's name with unit-address: */
#define DT_N_S_clocks_S_clk_hse_FULL_NAME "clk-hse"
#define DT_N_S_clocks_S_clk_hse_FULL_NAME_UNQUOTED clk-hse
#define DT_N_S_clocks_S_clk_hse_FULL_NAME_TOKEN clk_hse
#define DT_N_S_clocks_S_clk_hse_FULL_NAME_UPPER_TOKEN CLK_HSE

/* Node parent (/clocks) identifier: */
#define DT_N_S_clocks_S_clk_hse_PARENT DT_N_S_clocks

/* Node's index in its parent's list of children: */
#define DT_N_S_clocks_S_clk_hse_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_clocks_S_clk_hse_NODELABEL_NUM 1
#define DT_N_S_clocks_S_clk_hse_FOREACH_NODELABEL(fn) fn(clk_hse)
#define DT_N_S_clocks_S_clk_hse_FOREACH_NODELABEL_VARGS(fn, ...) fn(clk_hse, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hse_FOREACH_ANCESTOR(fn) fn(DT_N_S_clocks) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_clocks_S_clk_hse_CHILD_NUM 0
#define DT_N_S_clocks_S_clk_hse_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_clocks_S_clk_hse_FOREACH_CHILD(fn) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_clocks_S_clk_hse_HASH CHg50lhzojbh1fYYqBOhbjZFQvgn2_C8kiV4EgV0j3Y

/* Node's dependency ordinal: */
#define DT_N_S_clocks_S_clk_hse_ORD 7
#define DT_N_S_clocks_S_clk_hse_ORD_STR_SORTABLE 00007

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clocks_S_clk_hse_REQUIRES_ORDS \
	6, /* /clocks */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clocks_S_clk_hse_SUPPORTS_ORDS \
	8, /* /clocks/pll */
#define DT_N_NODELABEL_DT_N_S_clocks_S_clk_hse_IDX_0_C_TOKEN clk_hse

/* Existence and alternate IDs: */
#define DT_N_S_clocks_S_clk_hse_EXISTS 1
#define DT_N_INST_0_st_stm32_hse_clock DT_N_S_clocks_S_clk_hse
#define DT_N_NODELABEL_clk_hse         DT_N_S_clocks_S_clk_hse

/* Macros for properties that are special in the specification: */
#define DT_N_S_clocks_S_clk_hse_REG_NUM 0
#define DT_N_S_clocks_S_clk_hse_FOREACH_REG(fn) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_clk_hse_RANGES_NUM 0
#define DT_N_S_clocks_S_clk_hse_FOREACH_RANGE(fn) 
#define DT_N_S_clocks_S_clk_hse_IRQ_NUM 0
#define DT_N_S_clocks_S_clk_hse_IRQ_LEVEL 0
#define DT_N_S_clocks_S_clk_hse_COMPAT_MATCHES_st_stm32_hse_clock 1
#define DT_N_S_clocks_S_clk_hse_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_clocks_S_clk_hse_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_COMPAT_MODEL_IDX_0 "stm32-hse-clock"
#define DT_N_S_clocks_S_clk_hse_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clocks_S_clk_hse_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_clocks_S_clk_hse_P_hse_bypass 1
#define DT_N_S_clocks_S_clk_hse_P_hse_bypass_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_css_enabled 0
#define DT_N_S_clocks_S_clk_hse_P_css_enabled_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_clock_frequency 8000000
#define DT_N_S_clocks_S_clk_hse_P_clock_frequency_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_status "okay"
#define DT_N_S_clocks_S_clk_hse_P_status_STRING_UNQUOTED okay
#define DT_N_S_clocks_S_clk_hse_P_status_STRING_TOKEN okay
#define DT_N_S_clocks_S_clk_hse_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_clocks_S_clk_hse_P_status_IDX_0 "okay"
#define DT_N_S_clocks_S_clk_hse_P_status_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_clocks_S_clk_hse_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_hse, status, 0)
#define DT_N_S_clocks_S_clk_hse_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hse, status, 0)
#define DT_N_S_clocks_S_clk_hse_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hse, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hse_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hse, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hse_P_status_LEN 1
#define DT_N_S_clocks_S_clk_hse_P_status_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_compatible {"st,stm32-hse-clock"}
#define DT_N_S_clocks_S_clk_hse_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_compatible_IDX_0 "st,stm32-hse-clock"
#define DT_N_S_clocks_S_clk_hse_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-hse-clock
#define DT_N_S_clocks_S_clk_hse_P_compatible_IDX_0_STRING_TOKEN st_stm32_hse_clock
#define DT_N_S_clocks_S_clk_hse_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_HSE_CLOCK
#define DT_N_S_clocks_S_clk_hse_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_hse, compatible, 0)
#define DT_N_S_clocks_S_clk_hse_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hse, compatible, 0)
#define DT_N_S_clocks_S_clk_hse_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hse, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hse_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hse, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hse_P_compatible_LEN 1
#define DT_N_S_clocks_S_clk_hse_P_compatible_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_dma_coherent 0
#define DT_N_S_clocks_S_clk_hse_P_dma_coherent_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_zephyr_deferred_init 0
#define DT_N_S_clocks_S_clk_hse_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_wakeup_source 0
#define DT_N_S_clocks_S_clk_hse_P_wakeup_source_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_clocks_S_clk_hse_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /clocks/pll
 *
 * Node identifier: DT_N_S_clocks_S_pll
 *
 * Binding (compatible = st,stm32fx-pll-clock):
 *   $ZEPHYR_BASE\dts\bindings\clock\st,stm32fx-pll-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_clocks_S_pll_PATH "/clocks/pll"

/* Node's name with unit-address: */
#define DT_N_S_clocks_S_pll_FULL_NAME "pll"
#define DT_N_S_clocks_S_pll_FULL_NAME_UNQUOTED pll
#define DT_N_S_clocks_S_pll_FULL_NAME_TOKEN pll
#define DT_N_S_clocks_S_pll_FULL_NAME_UPPER_TOKEN PLL

/* Node parent (/clocks) identifier: */
#define DT_N_S_clocks_S_pll_PARENT DT_N_S_clocks

/* Node's index in its parent's list of children: */
#define DT_N_S_clocks_S_pll_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_clocks_S_pll_NODELABEL_NUM 1
#define DT_N_S_clocks_S_pll_FOREACH_NODELABEL(fn) fn(pll)
#define DT_N_S_clocks_S_pll_FOREACH_NODELABEL_VARGS(fn, ...) fn(pll, __VA_ARGS__)
#define DT_N_S_clocks_S_pll_FOREACH_ANCESTOR(fn) fn(DT_N_S_clocks) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_clocks_S_pll_CHILD_NUM 0
#define DT_N_S_clocks_S_pll_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_clocks_S_pll_FOREACH_CHILD(fn) 
#define DT_N_S_clocks_S_pll_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_clocks_S_pll_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_clocks_S_pll_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_pll_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_clocks_S_pll_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_clocks_S_pll_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_clocks_S_pll_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_clocks_S_pll_HASH MENiPNxcjOF6dwaYSdS9Iq0tqHDbWKghVscDDRncn0o

/* Node's dependency ordinal: */
#define DT_N_S_clocks_S_pll_ORD 8
#define DT_N_S_clocks_S_pll_ORD_STR_SORTABLE 00008

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clocks_S_pll_REQUIRES_ORDS \
	6, /* /clocks */ \
	7, /* /clocks/clk-hse */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clocks_S_pll_SUPPORTS_ORDS \
	9, /* /soc/rcc@40023800 */
#define DT_N_NODELABEL_DT_N_S_clocks_S_pll_IDX_0_C_TOKEN pll

/* Existence and alternate IDs: */
#define DT_N_S_clocks_S_pll_EXISTS 1
#define DT_N_INST_0_st_stm32fx_pll_clock DT_N_S_clocks_S_pll
#define DT_N_NODELABEL_pll               DT_N_S_clocks_S_pll

/* Macros for properties that are special in the specification: */
#define DT_N_S_clocks_S_pll_REG_NUM 0
#define DT_N_S_clocks_S_pll_FOREACH_REG(fn) 
#define DT_N_S_clocks_S_pll_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_clocks_S_pll_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_clocks_S_pll_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_pll_RANGES_NUM 0
#define DT_N_S_clocks_S_pll_FOREACH_RANGE(fn) 
#define DT_N_S_clocks_S_pll_IRQ_NUM 0
#define DT_N_S_clocks_S_pll_IRQ_LEVEL 0
#define DT_N_S_clocks_S_pll_COMPAT_MATCHES_st_stm32fx_pll_clock 1
#define DT_N_S_clocks_S_pll_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_pll_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_clocks_S_pll_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_pll_COMPAT_MODEL_IDX_0 "stm32fx-pll-clock"
#define DT_N_S_clocks_S_pll_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clocks_S_pll_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_clocks_S_pll_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_pll_P_clocks_IDX_0_PH DT_N_S_clocks_S_clk_hse
#define DT_N_S_clocks_S_pll_P_clocks_IDX_0_FOREACH_CELL(fn) 
#define DT_N_S_clocks_S_pll_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) 
#define DT_N_S_clocks_S_pll_P_clocks_IDX_0_NUM_CELLS 0
#define DT_N_S_clocks_S_pll_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_pll, clocks, 0)
#define DT_N_S_clocks_S_pll_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_pll, clocks, 0)
#define DT_N_S_clocks_S_pll_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_pll, clocks, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_pll_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_pll, clocks, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_pll_P_clocks_LEN 1
#define DT_N_S_clocks_S_pll_P_clocks_EXISTS 1
#define DT_N_S_clocks_S_pll_P_div_m 8
#define DT_N_S_clocks_S_pll_P_div_m_EXISTS 1
#define DT_N_S_clocks_S_pll_P_mul_n 336
#define DT_N_S_clocks_S_pll_P_mul_n_EXISTS 1
#define DT_N_S_clocks_S_pll_P_div_p 2
#define DT_N_S_clocks_S_pll_P_div_p_IDX_0_ENUM_IDX 0
#define DT_N_S_clocks_S_pll_P_div_p_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_pll_P_div_p_IDX_0_ENUM_VAL_2_EXISTS 1
#define DT_N_S_clocks_S_pll_P_div_p_ENUM_VAL_2_EXISTS 1
#define DT_N_S_clocks_S_pll_P_div_p_EXISTS 1
#define DT_N_S_clocks_S_pll_P_div_q 7
#define DT_N_S_clocks_S_pll_P_div_q_EXISTS 1
#define DT_N_S_clocks_S_pll_P_status "okay"
#define DT_N_S_clocks_S_pll_P_status_STRING_UNQUOTED okay
#define DT_N_S_clocks_S_pll_P_status_STRING_TOKEN okay
#define DT_N_S_clocks_S_pll_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_clocks_S_pll_P_status_IDX_0 "okay"
#define DT_N_S_clocks_S_pll_P_status_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_pll_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_clocks_S_pll_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_clocks_S_pll_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_clocks_S_pll_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_pll, status, 0)
#define DT_N_S_clocks_S_pll_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_pll, status, 0)
#define DT_N_S_clocks_S_pll_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_pll, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_pll_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_pll, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_pll_P_status_LEN 1
#define DT_N_S_clocks_S_pll_P_status_EXISTS 1
#define DT_N_S_clocks_S_pll_P_compatible {"st,stm32fx-pll-clock"}
#define DT_N_S_clocks_S_pll_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_pll_P_compatible_IDX_0 "st,stm32fx-pll-clock"
#define DT_N_S_clocks_S_pll_P_compatible_IDX_0_STRING_UNQUOTED st,stm32fx-pll-clock
#define DT_N_S_clocks_S_pll_P_compatible_IDX_0_STRING_TOKEN st_stm32fx_pll_clock
#define DT_N_S_clocks_S_pll_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32FX_PLL_CLOCK
#define DT_N_S_clocks_S_pll_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_pll, compatible, 0)
#define DT_N_S_clocks_S_pll_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_pll, compatible, 0)
#define DT_N_S_clocks_S_pll_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_pll, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_pll_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_pll, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_pll_P_compatible_LEN 1
#define DT_N_S_clocks_S_pll_P_compatible_EXISTS 1
#define DT_N_S_clocks_S_pll_P_dma_coherent 0
#define DT_N_S_clocks_S_pll_P_dma_coherent_EXISTS 1
#define DT_N_S_clocks_S_pll_P_zephyr_deferred_init 0
#define DT_N_S_clocks_S_pll_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_clocks_S_pll_P_wakeup_source 0
#define DT_N_S_clocks_S_pll_P_wakeup_source_EXISTS 1
#define DT_N_S_clocks_S_pll_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_clocks_S_pll_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/rcc@40023800
 *
 * Node identifier: DT_N_S_soc_S_rcc_40023800
 *
 * Binding (compatible = st,stm32f4-rcc):
 *   $ZEPHYR_BASE\dts\bindings\clock\st,stm32f4-rcc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rcc_40023800_PATH "/soc/rcc@40023800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rcc_40023800_FULL_NAME "rcc@40023800"
#define DT_N_S_soc_S_rcc_40023800_FULL_NAME_UNQUOTED rcc@40023800
#define DT_N_S_soc_S_rcc_40023800_FULL_NAME_TOKEN rcc_40023800
#define DT_N_S_soc_S_rcc_40023800_FULL_NAME_UPPER_TOKEN RCC_40023800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_rcc_40023800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rcc_40023800_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_rcc_40023800_NODELABEL_NUM 1
#define DT_N_S_soc_S_rcc_40023800_FOREACH_NODELABEL(fn) fn(rcc)
#define DT_N_S_soc_S_rcc_40023800_FOREACH_NODELABEL_VARGS(fn, ...) fn(rcc, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40023800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rcc_40023800_CHILD_NUM 1
#define DT_N_S_soc_S_rcc_40023800_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_rcc_40023800_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_rcc_40023800_S_reset_controller)
#define DT_N_S_soc_S_rcc_40023800_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_rcc_40023800_S_reset_controller)
#define DT_N_S_soc_S_rcc_40023800_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_rcc_40023800_S_reset_controller, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40023800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rcc_40023800_S_reset_controller, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40023800_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_rcc_40023800_S_reset_controller)
#define DT_N_S_soc_S_rcc_40023800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_rcc_40023800_S_reset_controller)
#define DT_N_S_soc_S_rcc_40023800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_rcc_40023800_S_reset_controller, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40023800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rcc_40023800_S_reset_controller, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_rcc_40023800_HASH S7aeZ5AZP2h8Z_Xqoo7bufqbhrOEAWgcHcl2SI2slSE

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rcc_40023800_ORD 9
#define DT_N_S_soc_S_rcc_40023800_ORD_STR_SORTABLE 00009

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rcc_40023800_REQUIRES_ORDS \
	4, /* /soc */ \
	8, /* /clocks/pll */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rcc_40023800_SUPPORTS_ORDS \
	12, /* /soc/adc@40012000 */ \
	21, /* /soc/pin-controller@40020000/gpio@40020400 */ \
	24, /* /soc/i2c@40005400 */ \
	28, /* /soc/i2c@40005800 */ \
	30, /* /soc/i2c@40005c00 */ \
	44, /* /soc/pin-controller@40020000/gpio@40020800 */ \
	54, /* /soc/pin-controller@40020000/gpio@40020000 */ \
	57, /* /soc/adc@40012100 */ \
	58, /* /soc/adc@40012200 */ \
	59, /* /soc/can@40006400 */ \
	60, /* /soc/can@40006800 */ \
	62, /* /soc/dac@40007400 */ \
	63, /* /soc/rcc@40023800/reset-controller */ \
	64, /* /soc/display-controller@40016800 */ \
	65, /* /soc/dma@40026000 */ \
	66, /* /soc/i2s@40003800 */ \
	67, /* /soc/i2s@40003c00 */ \
	68, /* /soc/interrupt-controller@40013c00 */ \
	69, /* /soc/memory@40024000 */ \
	70, /* /soc/rng@50060800 */ \
	71, /* /soc/sdmmc@40012c00 */ \
	72, /* /soc/serial@40004400 */ \
	75, /* /soc/serial@40004800 */ \
	76, /* /soc/serial@40004c00 */ \
	77, /* /soc/serial@40005000 */ \
	78, /* /soc/serial@40007800 */ \
	79, /* /soc/serial@40007c00 */ \
	80, /* /soc/serial@40011000 */ \
	83, /* /soc/serial@40011400 */ \
	84, /* /soc/spi@40003800 */ \
	85, /* /soc/spi@40003c00 */ \
	86, /* /soc/pin-controller@40020000/gpio@40020c00 */ \
	90, /* /soc/spi@40013000 */ \
	91, /* /soc/spi@40013400 */ \
	92, /* /soc/spi@40015000 */ \
	93, /* /soc/spi@40015400 */ \
	96, /* /soc/usb@40040000 */ \
	100, /* /soc/usb@50000000 */ \
	101, /* /soc/watchdog@40002c00 */ \
	110, /* /soc/ethernet@40028000 */ \
	122, /* /soc/memory-controller@a0000000 */ \
	124, /* /soc/pin-controller@40020000/gpio@40021000 */ \
	125, /* /soc/pin-controller@40020000/gpio@40021400 */ \
	126, /* /soc/pin-controller@40020000/gpio@40021800 */ \
	127, /* /soc/pin-controller@40020000/gpio@40021c00 */ \
	128, /* /soc/pin-controller@40020000/gpio@40022000 */ \
	129, /* /soc/pin-controller@40020000/gpio@40022400 */ \
	130, /* /soc/pin-controller@40020000/gpio@40022800 */ \
	131, /* /soc/rtc@40002800 */ \
	133, /* /soc/dma@40026400 */ \
	134, /* /soc/sai1@40015800 */ \
	137, /* /soc/timers@40000000 */ \
	141, /* /soc/timers@40000400 */ \
	145, /* /soc/timers@40000800 */ \
	149, /* /soc/timers@40000c00 */ \
	153, /* /soc/timers@40001000 */ \
	155, /* /soc/timers@40001400 */ \
	157, /* /soc/timers@40001800 */ \
	160, /* /soc/timers@40001c00 */ \
	163, /* /soc/timers@40002000 */ \
	166, /* /soc/timers@40010000 */ \
	171, /* /soc/timers@40010400 */ \
	175, /* /soc/timers@40014000 */ \
	178, /* /soc/timers@40014400 */ \
	181, /* /soc/timers@40014800 */
#define DT_N_NODELABEL_DT_N_S_soc_S_rcc_40023800_IDX_0_C_TOKEN rcc

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rcc_40023800_EXISTS 1
#define DT_N_INST_0_st_stm32f4_rcc DT_N_S_soc_S_rcc_40023800
#define DT_N_NODELABEL_rcc         DT_N_S_soc_S_rcc_40023800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rcc_40023800_REG_NUM 1
#define DT_N_S_soc_S_rcc_40023800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_REG_IDX_0_VAL_ADDRESS 1073887232 /* 0x40023800 */
#define DT_N_S_soc_S_rcc_40023800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_rcc_40023800_FOREACH_REG(fn) fn(DT_N_S_soc_S_rcc_40023800, 0)
#define DT_N_S_soc_S_rcc_40023800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_rcc_40023800, 0)
#define DT_N_S_soc_S_rcc_40023800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_rcc_40023800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40023800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rcc_40023800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40023800_RANGES_NUM 0
#define DT_N_S_soc_S_rcc_40023800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rcc_40023800_IRQ_NUM 0
#define DT_N_S_soc_S_rcc_40023800_IRQ_LEVEL 0
#define DT_N_S_soc_S_rcc_40023800_COMPAT_MATCHES_st_stm32f4_rcc 1
#define DT_N_S_soc_S_rcc_40023800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_rcc_40023800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_COMPAT_MODEL_IDX_0 "stm32f4-rcc"
#define DT_N_S_soc_S_rcc_40023800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rcc_40023800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_rcc_40023800_P_timpre 0
#define DT_N_S_soc_S_rcc_40023800_P_timpre_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_reg {1073887232 /* 0x40023800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_rcc_40023800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_reg_IDX_0 1073887232
#define DT_N_S_soc_S_rcc_40023800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_rcc_40023800_P_reg_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_clock_frequency 168000000
#define DT_N_S_soc_S_rcc_40023800_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_ahb_prescaler 1
#define DT_N_S_soc_S_rcc_40023800_P_ahb_prescaler_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_rcc_40023800_P_ahb_prescaler_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_ahb_prescaler_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_ahb_prescaler_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_ahb_prescaler_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_apb1_prescaler 4
#define DT_N_S_soc_S_rcc_40023800_P_apb1_prescaler_IDX_0_ENUM_IDX 2
#define DT_N_S_soc_S_rcc_40023800_P_apb1_prescaler_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_apb1_prescaler_IDX_0_ENUM_VAL_4_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_apb1_prescaler_ENUM_VAL_4_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_apb1_prescaler_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_apb2_prescaler 2
#define DT_N_S_soc_S_rcc_40023800_P_apb2_prescaler_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_rcc_40023800_P_apb2_prescaler_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_apb2_prescaler_IDX_0_ENUM_VAL_2_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_apb2_prescaler_ENUM_VAL_2_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_apb2_prescaler_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_undershoot_prevention 0
#define DT_N_S_soc_S_rcc_40023800_P_undershoot_prevention_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_compatible {"st,stm32f4-rcc"}
#define DT_N_S_soc_S_rcc_40023800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_compatible_IDX_0 "st,stm32f4-rcc"
#define DT_N_S_soc_S_rcc_40023800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32f4-rcc
#define DT_N_S_soc_S_rcc_40023800_P_compatible_IDX_0_STRING_TOKEN st_stm32f4_rcc
#define DT_N_S_soc_S_rcc_40023800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32F4_RCC
#define DT_N_S_soc_S_rcc_40023800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rcc_40023800, compatible, 0)
#define DT_N_S_soc_S_rcc_40023800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rcc_40023800, compatible, 0)
#define DT_N_S_soc_S_rcc_40023800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rcc_40023800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40023800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rcc_40023800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40023800_P_compatible_LEN 1
#define DT_N_S_soc_S_rcc_40023800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_clocks_IDX_0_PH DT_N_S_clocks_S_pll
#define DT_N_S_soc_S_rcc_40023800_P_clocks_IDX_0_FOREACH_CELL(fn) 
#define DT_N_S_soc_S_rcc_40023800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) 
#define DT_N_S_soc_S_rcc_40023800_P_clocks_IDX_0_NUM_CELLS 0
#define DT_N_S_soc_S_rcc_40023800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rcc_40023800, clocks, 0)
#define DT_N_S_soc_S_rcc_40023800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rcc_40023800, clocks, 0)
#define DT_N_S_soc_S_rcc_40023800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rcc_40023800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40023800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rcc_40023800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40023800_P_clocks_LEN 1
#define DT_N_S_soc_S_rcc_40023800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_dma_coherent 0
#define DT_N_S_soc_S_rcc_40023800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_rcc_40023800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_wakeup_source 0
#define DT_N_S_soc_S_rcc_40023800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_rcc_40023800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000
 *
 * Binding (compatible = st,stm32-pinctrl):
 *   $ZEPHYR_BASE\dts\bindings\pinctrl\st,stm32-pinctrl.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_PATH "/soc/pin-controller@40020000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_FULL_NAME "pin-controller@40020000"
#define DT_N_S_soc_S_pin_controller_40020000_FULL_NAME_UNQUOTED pin-controller@40020000
#define DT_N_S_soc_S_pin_controller_40020000_FULL_NAME_TOKEN pin_controller_40020000
#define DT_N_S_soc_S_pin_controller_40020000_FULL_NAME_UPPER_TOKEN PIN_CONTROLLER_40020000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_FOREACH_NODELABEL(fn) fn(pinctrl)
#define DT_N_S_soc_S_pin_controller_40020000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pinctrl, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_CHILD_NUM 36
#define DT_N_S_soc_S_pin_controller_40020000_CHILD_NUM_STATUS_OKAY 36
#define DT_N_S_soc_S_pin_controller_40020000_CHILD_UNIT_ADDR_INT_1073872896 DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000
#define DT_N_S_soc_S_pin_controller_40020000_CHILD_UNIT_ADDR_INT_1073873920 DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400
#define DT_N_S_soc_S_pin_controller_40020000_CHILD_UNIT_ADDR_INT_1073874944 DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800
#define DT_N_S_soc_S_pin_controller_40020000_CHILD_UNIT_ADDR_INT_1073875968 DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00
#define DT_N_S_soc_S_pin_controller_40020000_CHILD_UNIT_ADDR_INT_1073876992 DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000
#define DT_N_S_soc_S_pin_controller_40020000_CHILD_UNIT_ADDR_INT_1073878016 DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400
#define DT_N_S_soc_S_pin_controller_40020000_CHILD_UNIT_ADDR_INT_1073879040 DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800
#define DT_N_S_soc_S_pin_controller_40020000_CHILD_UNIT_ADDR_INT_1073880064 DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00
#define DT_N_S_soc_S_pin_controller_40020000_CHILD_UNIT_ADDR_INT_1073881088 DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000
#define DT_N_S_soc_S_pin_controller_40020000_CHILD_UNIT_ADDR_INT_1073882112 DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400
#define DT_N_S_soc_S_pin_controller_40020000_CHILD_UNIT_ADDR_INT_1073883136 DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800
#define DT_N_S_soc_S_pin_controller_40020000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800) fn(DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0) fn(DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5) fn(DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12)
#define DT_N_S_soc_S_pin_controller_40020000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12)
#define DT_N_S_soc_S_pin_controller_40020000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800) fn(DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0) fn(DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5) fn(DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12)
#define DT_N_S_soc_S_pin_controller_40020000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12)
#define DT_N_S_soc_S_pin_controller_40020000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_HASH 7lBD4y_pHx2ZNZ3rFhsnaqw4SXtwoDeiRf9WLX2Mohs

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_ORD 10
#define DT_N_S_soc_S_pin_controller_40020000_ORD_STR_SORTABLE 00010

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_SUPPORTS_ORDS \
	11, /* /soc/pin-controller@40020000/adc1_in0_pa0 */ \
	21, /* /soc/pin-controller@40020000/gpio@40020400 */ \
	22, /* /soc/pin-controller@40020000/i2c1_scl_pb8 */ \
	23, /* /soc/pin-controller@40020000/i2c1_sda_pb9 */ \
	26, /* /soc/pin-controller@40020000/i2c2_scl_pb10 */ \
	27, /* /soc/pin-controller@40020000/i2c2_sda_pb11 */ \
	44, /* /soc/pin-controller@40020000/gpio@40020800 */ \
	54, /* /soc/pin-controller@40020000/gpio@40020000 */ \
	61, /* /soc/pin-controller@40020000/dac_out1_pa4 */ \
	73, /* /soc/pin-controller@40020000/usart3_rx_pd9 */ \
	74, /* /soc/pin-controller@40020000/usart3_tx_pd8 */ \
	81, /* /soc/pin-controller@40020000/usart6_rx_pg9 */ \
	82, /* /soc/pin-controller@40020000/usart6_tx_pg14 */ \
	86, /* /soc/pin-controller@40020000/gpio@40020c00 */ \
	87, /* /soc/pin-controller@40020000/spi1_miso_pa6 */ \
	88, /* /soc/pin-controller@40020000/spi1_mosi_pa7 */ \
	89, /* /soc/pin-controller@40020000/spi1_sck_pa5 */ \
	98, /* /soc/pin-controller@40020000/usb_otg_fs_dm_pa11 */ \
	99, /* /soc/pin-controller@40020000/usb_otg_fs_dp_pa12 */ \
	103, /* /soc/pin-controller@40020000/eth_crs_dv_pa7 */ \
	104, /* /soc/pin-controller@40020000/eth_ref_clk_pa1 */ \
	105, /* /soc/pin-controller@40020000/eth_rxd0_pc4 */ \
	106, /* /soc/pin-controller@40020000/eth_rxd1_pc5 */ \
	107, /* /soc/pin-controller@40020000/eth_tx_en_pg11 */ \
	108, /* /soc/pin-controller@40020000/eth_txd0_pg13 */ \
	109, /* /soc/pin-controller@40020000/eth_txd1_pb13 */ \
	111, /* /soc/pin-controller@40020000/eth_mdc_pc1 */ \
	112, /* /soc/pin-controller@40020000/eth_mdio_pa2 */ \
	124, /* /soc/pin-controller@40020000/gpio@40021000 */ \
	125, /* /soc/pin-controller@40020000/gpio@40021400 */ \
	126, /* /soc/pin-controller@40020000/gpio@40021800 */ \
	127, /* /soc/pin-controller@40020000/gpio@40021c00 */ \
	128, /* /soc/pin-controller@40020000/gpio@40022000 */ \
	129, /* /soc/pin-controller@40020000/gpio@40022400 */ \
	130, /* /soc/pin-controller@40020000/gpio@40022800 */ \
	168, /* /soc/pin-controller@40020000/tim1_ch3_pe13 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_IDX_0_C_TOKEN pinctrl

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_EXISTS 1
#define DT_N_INST_0_st_stm32_pinctrl DT_N_S_soc_S_pin_controller_40020000
#define DT_N_NODELABEL_pinctrl       DT_N_S_soc_S_pin_controller_40020000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_REG_IDX_0_VAL_ADDRESS 1073872896 /* 0x40020000 */
#define DT_N_S_soc_S_pin_controller_40020000_REG_IDX_0_VAL_SIZE 11264 /* 0x2c00 */
#define DT_N_S_soc_S_pin_controller_40020000_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_40020000, 0)
#define DT_N_S_soc_S_pin_controller_40020000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000, 0)
#define DT_N_S_soc_S_pin_controller_40020000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_COMPAT_MATCHES_st_stm32_pinctrl 1
#define DT_N_S_soc_S_pin_controller_40020000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_40020000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_COMPAT_MODEL_IDX_0 "stm32-pinctrl"
#define DT_N_S_soc_S_pin_controller_40020000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_P_reg {1073872896 /* 0x40020000 */, 11264 /* 0x2c00 */}
#define DT_N_S_soc_S_pin_controller_40020000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_P_reg_IDX_0 1073872896
#define DT_N_S_soc_S_pin_controller_40020000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_P_reg_IDX_1 11264
#define DT_N_S_soc_S_pin_controller_40020000_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_P_remap_pa11 0
#define DT_N_S_soc_S_pin_controller_40020000_P_remap_pa11_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_P_remap_pa12 0
#define DT_N_S_soc_S_pin_controller_40020000_P_remap_pa12_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_P_remap_pa11_pa12 0
#define DT_N_S_soc_S_pin_controller_40020000_P_remap_pa11_pa12_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_P_compatible {"st,stm32-pinctrl"}
#define DT_N_S_soc_S_pin_controller_40020000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_P_compatible_IDX_0 "st,stm32-pinctrl"
#define DT_N_S_soc_S_pin_controller_40020000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pinctrl
#define DT_N_S_soc_S_pin_controller_40020000_P_compatible_IDX_0_STRING_TOKEN st_stm32_pinctrl
#define DT_N_S_soc_S_pin_controller_40020000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PINCTRL
#define DT_N_S_soc_S_pin_controller_40020000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_40020000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_40020000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_40020000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_40020000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/adc1_in0_pa0
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_PATH "/soc/pin-controller@40020000/adc1_in0_pa0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FULL_NAME "adc1_in0_pa0"
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FULL_NAME_UNQUOTED adc1_in0_pa0
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FULL_NAME_TOKEN adc1_in0_pa0
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FULL_NAME_UPPER_TOKEN ADC1_IN0_PA0

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_CHILD_IDX 11

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FOREACH_NODELABEL(fn) fn(adc1_in0_pa0)
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc1_in0_pa0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_HASH bs_lYQu2uhUX7DQ0OJ38QcGsXp9u0qDcfTBhCyRO7hI

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_ORD 11
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_ORD_STR_SORTABLE 00011

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_SUPPORTS_ORDS \
	12, /* /soc/adc@40012000 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_IDX_0_C_TOKEN adc1_in0_pa0

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_EXISTS 1
#define DT_N_NODELABEL_adc1_in0_pa0 DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_pinmux 16
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/adc@40012000
 *
 * Node identifier: DT_N_S_soc_S_adc_40012000
 *
 * Binding (compatible = st,stm32f4-adc):
 *   $ZEPHYR_BASE\dts\bindings\adc\st,stm32f4-adc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_adc_40012000_PATH "/soc/adc@40012000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_adc_40012000_FULL_NAME "adc@40012000"
#define DT_N_S_soc_S_adc_40012000_FULL_NAME_UNQUOTED adc@40012000
#define DT_N_S_soc_S_adc_40012000_FULL_NAME_TOKEN adc_40012000
#define DT_N_S_soc_S_adc_40012000_FULL_NAME_UPPER_TOKEN ADC_40012000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_adc_40012000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_adc_40012000_CHILD_IDX 25

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_adc_40012000_NODELABEL_NUM 1
#define DT_N_S_soc_S_adc_40012000_FOREACH_NODELABEL(fn) fn(adc1)
#define DT_N_S_soc_S_adc_40012000_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc1, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_adc_40012000_CHILD_NUM 0
#define DT_N_S_soc_S_adc_40012000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_adc_40012000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_adc_40012000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_adc_40012000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_adc_40012000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_adc_40012000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_adc_40012000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_adc_40012000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_adc_40012000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_adc_40012000_HASH Te5HmBbeCyjRhNRBg_7Nuz9I98ZrK89deTVOAC2lhR8

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_adc_40012000_ORD 12
#define DT_N_S_soc_S_adc_40012000_ORD_STR_SORTABLE 00012

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_adc_40012000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	11, /* /soc/pin-controller@40020000/adc1_in0_pa0 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_adc_40012000_SUPPORTS_ORDS \
	18, /* /dietemp */ \
	32, /* /vbat */ \
	34, /* /vref */
#define DT_N_NODELABEL_DT_N_S_soc_S_adc_40012000_IDX_0_C_TOKEN adc1

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_adc_40012000_EXISTS 1
#define DT_N_INST_0_st_stm32f4_adc DT_N_S_soc_S_adc_40012000
#define DT_N_INST_0_st_stm32_adc   DT_N_S_soc_S_adc_40012000
#define DT_N_NODELABEL_adc1        DT_N_S_soc_S_adc_40012000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_adc_40012000_REG_NUM 1
#define DT_N_S_soc_S_adc_40012000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_REG_IDX_0_VAL_ADDRESS 1073815552 /* 0x40012000 */
#define DT_N_S_soc_S_adc_40012000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_adc_40012000_FOREACH_REG(fn) fn(DT_N_S_soc_S_adc_40012000, 0)
#define DT_N_S_soc_S_adc_40012000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012000, 0)
#define DT_N_S_soc_S_adc_40012000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_RANGES_NUM 0
#define DT_N_S_soc_S_adc_40012000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_adc_40012000_IRQ_NUM 1
#define DT_N_S_soc_S_adc_40012000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_IRQ_IDX_0_VAL_irq 18
#define DT_N_S_soc_S_adc_40012000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_adc_40012000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_adc_40012000_IRQ_LEVEL 1
#define DT_N_S_soc_S_adc_40012000_COMPAT_MATCHES_st_stm32f4_adc 1
#define DT_N_S_soc_S_adc_40012000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_adc_40012000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_COMPAT_MODEL_IDX_0 "stm32f4-adc"
#define DT_N_S_soc_S_adc_40012000_COMPAT_MATCHES_st_stm32_adc 1
#define DT_N_S_soc_S_adc_40012000_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_adc_40012000_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_COMPAT_MODEL_IDX_1 "stm32-adc"
#define DT_N_S_soc_S_adc_40012000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_adc_40012000_PINCTRL_NUM 1
#define DT_N_S_soc_S_adc_40012000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_adc_40012000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_adc_40012000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_adc_40012000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0

/* Generic property macros: */
#define DT_N_S_soc_S_adc_40012000_P_reg {1073815552 /* 0x40012000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_adc_40012000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_reg_IDX_0 1073815552
#define DT_N_S_soc_S_adc_40012000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_adc_40012000_P_reg_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_adc_40012000_P_clocks_IDX_0_VAL_bus 68
#define DT_N_S_soc_S_adc_40012000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_clocks_IDX_0_VAL_bits 256
#define DT_N_S_soc_S_adc_40012000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_adc_40012000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_adc_40012000, clocks, 0, bits)
#define DT_N_S_soc_S_adc_40012000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, clocks, 0, bits)
#define DT_N_S_soc_S_adc_40012000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_adc_40012000_P_clocks_IDX_0_NAME "adcx"
#define DT_N_S_soc_S_adc_40012000_P_clocks_NAME_adcx_IDX 0
#define DT_N_S_soc_S_adc_40012000_P_clocks_NAME_adcx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_adc_40012000, clocks, adcx, bus) \
	fn(DT_N_S_soc_S_adc_40012000, clocks, adcx, bits)
#define DT_N_S_soc_S_adc_40012000_P_clocks_NAME_adcx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012000, clocks, adcx, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, clocks, adcx, bits)
#define DT_N_S_soc_S_adc_40012000_P_clocks_NAME_adcx_NUM_CELLS 2
#define DT_N_S_soc_S_adc_40012000_P_clocks_NAME_adcx_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_adc_40012000_P_clocks_NAME_adcx_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_clocks_NAME_adcx_VAL_bus DT_N_S_soc_S_adc_40012000_P_clocks_IDX_0_VAL_bus
#define DT_N_S_soc_S_adc_40012000_P_clocks_NAME_adcx_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_clocks_NAME_adcx_VAL_bits DT_N_S_soc_S_adc_40012000_P_clocks_IDX_0_VAL_bits
#define DT_N_S_soc_S_adc_40012000_P_clocks_NAME_adcx_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012000, clocks, 0)
#define DT_N_S_soc_S_adc_40012000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012000, clocks, 0)
#define DT_N_S_soc_S_adc_40012000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_clocks_LEN 1
#define DT_N_S_soc_S_adc_40012000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_clock_names {"adcx"}
#define DT_N_S_soc_S_adc_40012000_P_clock_names_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_adc_40012000_P_clock_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_clock_names_IDX_0_ENUM_VAL_adcx_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_clock_names_ENUM_VAL_adcx_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_clock_names_IDX_0 "adcx"
#define DT_N_S_soc_S_adc_40012000_P_clock_names_IDX_0_STRING_UNQUOTED adcx
#define DT_N_S_soc_S_adc_40012000_P_clock_names_IDX_0_STRING_TOKEN adcx
#define DT_N_S_soc_S_adc_40012000_P_clock_names_IDX_0_STRING_UPPER_TOKEN ADCX
#define DT_N_S_soc_S_adc_40012000_P_clock_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012000, clock_names, 0)
#define DT_N_S_soc_S_adc_40012000_P_clock_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012000, clock_names, 0)
#define DT_N_S_soc_S_adc_40012000_P_clock_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012000, clock_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_clock_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012000, clock_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_clock_names_LEN 1
#define DT_N_S_soc_S_adc_40012000_P_clock_names_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_interrupts {18 /* 0x12 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_adc_40012000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_interrupts_IDX_0 18
#define DT_N_S_soc_S_adc_40012000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_adc_40012000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_clock_source "SYNC"
#define DT_N_S_soc_S_adc_40012000_P_st_adc_clock_source_STRING_UNQUOTED SYNC
#define DT_N_S_soc_S_adc_40012000_P_st_adc_clock_source_STRING_TOKEN SYNC
#define DT_N_S_soc_S_adc_40012000_P_st_adc_clock_source_STRING_UPPER_TOKEN SYNC
#define DT_N_S_soc_S_adc_40012000_P_st_adc_clock_source_IDX_0 "SYNC"
#define DT_N_S_soc_S_adc_40012000_P_st_adc_clock_source_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_clock_source_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_adc_40012000_P_st_adc_clock_source_IDX_0_ENUM_VAL_sync_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_clock_source_ENUM_VAL_sync_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_clock_source_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012000, st_adc_clock_source, 0)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_clock_source_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012000, st_adc_clock_source, 0)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012000, st_adc_clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_clock_source_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012000, st_adc_clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_clock_source_LEN 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_clock_source_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_prescaler 2
#define DT_N_S_soc_S_adc_40012000_P_st_adc_prescaler_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_prescaler_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_prescaler_IDX_0_ENUM_VAL_2_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_prescaler_ENUM_VAL_2_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_prescaler_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_vref_mv 3300
#define DT_N_S_soc_S_adc_40012000_P_vref_mv_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_resolutions {12 /* 0xc */, 10 /* 0xa */, 8 /* 0x8 */, 6 /* 0x6 */}
#define DT_N_S_soc_S_adc_40012000_P_st_adc_resolutions_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_resolutions_IDX_0 12
#define DT_N_S_soc_S_adc_40012000_P_st_adc_resolutions_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_resolutions_IDX_1 10
#define DT_N_S_soc_S_adc_40012000_P_st_adc_resolutions_IDX_2_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_resolutions_IDX_2 8
#define DT_N_S_soc_S_adc_40012000_P_st_adc_resolutions_IDX_3_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_resolutions_IDX_3 6
#define DT_N_S_soc_S_adc_40012000_P_st_adc_resolutions_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012000, st_adc_resolutions, 0) \
	fn(DT_N_S_soc_S_adc_40012000, st_adc_resolutions, 1) \
	fn(DT_N_S_soc_S_adc_40012000, st_adc_resolutions, 2) \
	fn(DT_N_S_soc_S_adc_40012000, st_adc_resolutions, 3)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_resolutions_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012000, st_adc_resolutions, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, st_adc_resolutions, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, st_adc_resolutions, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, st_adc_resolutions, 3)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_resolutions_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012000, st_adc_resolutions, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012000, st_adc_resolutions, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012000, st_adc_resolutions, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012000, st_adc_resolutions, 3, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_resolutions_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012000, st_adc_resolutions, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, st_adc_resolutions, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, st_adc_resolutions, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, st_adc_resolutions, 3, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_resolutions_LEN 4
#define DT_N_S_soc_S_adc_40012000_P_st_adc_resolutions_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_sampling_times {3 /* 0x3 */, 15 /* 0xf */, 28 /* 0x1c */, 56 /* 0x38 */, 84 /* 0x54 */, 112 /* 0x70 */, 144 /* 0x90 */, 480 /* 0x1e0 */}
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_IDX_0 3
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_IDX_1 15
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_IDX_2_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_IDX_2 28
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_IDX_3_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_IDX_3 56
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_IDX_4_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_IDX_4 84
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_IDX_5_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_IDX_5 112
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_IDX_6_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_IDX_6 144
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_IDX_7_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_IDX_7 480
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012000, sampling_times, 0) \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 1) \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 2) \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 3) \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 4) \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 5) \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 6) \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 7)
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012000, sampling_times, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 7)
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012000, sampling_times, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 7, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012000, sampling_times, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, sampling_times, 7, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_LEN 8
#define DT_N_S_soc_S_adc_40012000_P_sampling_times_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_sequencer "programmable"
#define DT_N_S_soc_S_adc_40012000_P_st_adc_sequencer_STRING_UNQUOTED programmable
#define DT_N_S_soc_S_adc_40012000_P_st_adc_sequencer_STRING_TOKEN programmable
#define DT_N_S_soc_S_adc_40012000_P_st_adc_sequencer_STRING_UPPER_TOKEN PROGRAMMABLE
#define DT_N_S_soc_S_adc_40012000_P_st_adc_sequencer_IDX_0 "programmable"
#define DT_N_S_soc_S_adc_40012000_P_st_adc_sequencer_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_sequencer_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_sequencer_IDX_0_ENUM_VAL_programmable_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_sequencer_ENUM_VAL_programmable_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_sequencer_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012000, st_adc_sequencer, 0)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_sequencer_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012000, st_adc_sequencer, 0)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_sequencer_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012000, st_adc_sequencer, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_sequencer_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012000, st_adc_sequencer, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_sequencer_LEN 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_sequencer_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_oversampler "none"
#define DT_N_S_soc_S_adc_40012000_P_st_adc_oversampler_STRING_UNQUOTED none
#define DT_N_S_soc_S_adc_40012000_P_st_adc_oversampler_STRING_TOKEN none
#define DT_N_S_soc_S_adc_40012000_P_st_adc_oversampler_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_adc_40012000_P_st_adc_oversampler_IDX_0 "none"
#define DT_N_S_soc_S_adc_40012000_P_st_adc_oversampler_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_oversampler_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_adc_40012000_P_st_adc_oversampler_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_oversampler_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_oversampler_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012000, st_adc_oversampler, 0)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_oversampler_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012000, st_adc_oversampler, 0)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_oversampler_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012000, st_adc_oversampler, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_oversampler_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012000, st_adc_oversampler, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_oversampler_LEN 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_oversampler_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_internal_regulator "none"
#define DT_N_S_soc_S_adc_40012000_P_st_adc_internal_regulator_STRING_UNQUOTED none
#define DT_N_S_soc_S_adc_40012000_P_st_adc_internal_regulator_STRING_TOKEN none
#define DT_N_S_soc_S_adc_40012000_P_st_adc_internal_regulator_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_adc_40012000_P_st_adc_internal_regulator_IDX_0 "none"
#define DT_N_S_soc_S_adc_40012000_P_st_adc_internal_regulator_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_internal_regulator_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_adc_40012000_P_st_adc_internal_regulator_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_internal_regulator_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_internal_regulator_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012000, st_adc_internal_regulator, 0)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_internal_regulator_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012000, st_adc_internal_regulator, 0)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_internal_regulator_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012000, st_adc_internal_regulator, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_internal_regulator_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012000, st_adc_internal_regulator, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_st_adc_internal_regulator_LEN 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_internal_regulator_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_has_deep_powerdown 0
#define DT_N_S_soc_S_adc_40012000_P_st_adc_has_deep_powerdown_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_has_channel_preselection 0
#define DT_N_S_soc_S_adc_40012000_P_st_adc_has_channel_preselection_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_has_differential_support 0
#define DT_N_S_soc_S_adc_40012000_P_st_adc_has_differential_support_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_has_injected_support 1
#define DT_N_S_soc_S_adc_40012000_P_st_adc_has_injected_support_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_status "okay"
#define DT_N_S_soc_S_adc_40012000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_adc_40012000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_adc_40012000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_adc_40012000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_adc_40012000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_adc_40012000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012000, status, 0)
#define DT_N_S_soc_S_adc_40012000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012000, status, 0)
#define DT_N_S_soc_S_adc_40012000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_status_LEN 1
#define DT_N_S_soc_S_adc_40012000_P_status_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_compatible {"st,stm32f4-adc", "st,stm32-adc"}
#define DT_N_S_soc_S_adc_40012000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_compatible_IDX_0 "st,stm32f4-adc"
#define DT_N_S_soc_S_adc_40012000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32f4-adc
#define DT_N_S_soc_S_adc_40012000_P_compatible_IDX_0_STRING_TOKEN st_stm32f4_adc
#define DT_N_S_soc_S_adc_40012000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32F4_ADC
#define DT_N_S_soc_S_adc_40012000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_compatible_IDX_1 "st,stm32-adc"
#define DT_N_S_soc_S_adc_40012000_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-adc
#define DT_N_S_soc_S_adc_40012000_P_compatible_IDX_1_STRING_TOKEN st_stm32_adc
#define DT_N_S_soc_S_adc_40012000_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_ADC
#define DT_N_S_soc_S_adc_40012000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012000, compatible, 0) \
	fn(DT_N_S_soc_S_adc_40012000, compatible, 1)
#define DT_N_S_soc_S_adc_40012000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, compatible, 1)
#define DT_N_S_soc_S_adc_40012000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_compatible_LEN 2
#define DT_N_S_soc_S_adc_40012000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_dma_coherent 0
#define DT_N_S_soc_S_adc_40012000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_adc_40012000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_wakeup_source 0
#define DT_N_S_soc_S_adc_40012000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_adc_40012000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012000, pinctrl_0, 0)
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012000, pinctrl_0, 0)
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012000, pinctrl_names, 0)
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012000, pinctrl_names, 0)
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_adc_40012000_P_pinctrl_names_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40023c00
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40023c00
 *
 * Binding (compatible = st,stm32-flash-controller):
 *   $ZEPHYR_BASE\dts\bindings\flash_controller\st,stm32-flash-controller.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40023c00_PATH "/soc/flash-controller@40023c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40023c00_FULL_NAME "flash-controller@40023c00"
#define DT_N_S_soc_S_flash_controller_40023c00_FULL_NAME_UNQUOTED flash-controller@40023c00
#define DT_N_S_soc_S_flash_controller_40023c00_FULL_NAME_TOKEN flash_controller_40023c00
#define DT_N_S_soc_S_flash_controller_40023c00_FULL_NAME_UPPER_TOKEN FLASH_CONTROLLER_40023C00

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40023c00_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40023c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_FOREACH_NODELABEL(fn) fn(flash)
#define DT_N_S_soc_S_flash_controller_40023c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(flash, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40023c00_CHILD_NUM 3
#define DT_N_S_soc_S_flash_controller_40023c00_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_soc_S_flash_controller_40023c00_CHILD_UNIT_ADDR_INT_134217728 DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000
#define DT_N_S_soc_S_flash_controller_40023c00_CHILD_UNIT_ADDR_INT_536836096 DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800
#define DT_N_S_soc_S_flash_controller_40023c00_CHILD_UNIT_ADDR_INT_536836608 DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00
#define DT_N_S_soc_S_flash_controller_40023c00_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00)
#define DT_N_S_soc_S_flash_controller_40023c00_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00)
#define DT_N_S_soc_S_flash_controller_40023c00_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00)
#define DT_N_S_soc_S_flash_controller_40023c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00)
#define DT_N_S_soc_S_flash_controller_40023c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40023c00_HASH o6IgGUoikpDMUcHrnMq7wi0BEFmMtiE5rUwzi0VNUNk

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40023c00_ORD 13
#define DT_N_S_soc_S_flash_controller_40023c00_ORD_STR_SORTABLE 00013

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40023c00_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40023c00_SUPPORTS_ORDS \
	14, /* /soc/flash-controller@40023c00/flash@1fff7a00 */ \
	115, /* /soc/flash-controller@40023c00/flash@1fff7800 */ \
	116, /* /soc/flash-controller@40023c00/flash@8000000 */
#define DT_N_NODELABEL_DT_N_S_soc_S_flash_controller_40023c00_IDX_0_C_TOKEN flash

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40023c00_EXISTS 1
#define DT_N_INST_0_st_stm32_flash_controller   DT_N_S_soc_S_flash_controller_40023c00
#define DT_N_INST_0_st_stm32f4_flash_controller DT_N_S_soc_S_flash_controller_40023c00
#define DT_N_NODELABEL_flash                    DT_N_S_soc_S_flash_controller_40023c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40023c00_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_REG_IDX_0_VAL_ADDRESS 1073888256 /* 0x40023c00 */
#define DT_N_S_soc_S_flash_controller_40023c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_flash_controller_40023c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40023c00, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_IRQ_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_IRQ_IDX_0_VAL_irq 4
#define DT_N_S_soc_S_flash_controller_40023c00_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_flash_controller_40023c00_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_flash_controller_40023c00_IRQ_LEVEL 1
#define DT_N_S_soc_S_flash_controller_40023c00_COMPAT_MATCHES_st_stm32_flash_controller 1
#define DT_N_S_soc_S_flash_controller_40023c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_flash_controller_40023c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_COMPAT_MODEL_IDX_0 "stm32-flash-controller"
#define DT_N_S_soc_S_flash_controller_40023c00_COMPAT_MATCHES_st_stm32f4_flash_controller 1
#define DT_N_S_soc_S_flash_controller_40023c00_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_flash_controller_40023c00_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_COMPAT_MODEL_IDX_1 "stm32f4-flash-controller"
#define DT_N_S_soc_S_flash_controller_40023c00_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40023c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40023c00_P_st_rdp1_enable_byte 85
#define DT_N_S_soc_S_flash_controller_40023c00_P_st_rdp1_enable_byte_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_P_reg {1073888256 /* 0x40023c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_flash_controller_40023c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_P_reg_IDX_0 1073888256
#define DT_N_S_soc_S_flash_controller_40023c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_flash_controller_40023c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_P_compatible {"st,stm32-flash-controller", "st,stm32f4-flash-controller"}
#define DT_N_S_soc_S_flash_controller_40023c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_P_compatible_IDX_0 "st,stm32-flash-controller"
#define DT_N_S_soc_S_flash_controller_40023c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-flash-controller
#define DT_N_S_soc_S_flash_controller_40023c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_flash_controller
#define DT_N_S_soc_S_flash_controller_40023c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_FLASH_CONTROLLER
#define DT_N_S_soc_S_flash_controller_40023c00_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_P_compatible_IDX_1 "st,stm32f4-flash-controller"
#define DT_N_S_soc_S_flash_controller_40023c00_P_compatible_IDX_1_STRING_UNQUOTED st,stm32f4-flash-controller
#define DT_N_S_soc_S_flash_controller_40023c00_P_compatible_IDX_1_STRING_TOKEN st_stm32f4_flash_controller
#define DT_N_S_soc_S_flash_controller_40023c00_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32F4_FLASH_CONTROLLER
#define DT_N_S_soc_S_flash_controller_40023c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40023c00, compatible, 0) \
	fn(DT_N_S_soc_S_flash_controller_40023c00, compatible, 1)
#define DT_N_S_soc_S_flash_controller_40023c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_flash_controller_40023c00, compatible, 1)
#define DT_N_S_soc_S_flash_controller_40023c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_flash_controller_40023c00, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_flash_controller_40023c00, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_P_compatible_LEN 2
#define DT_N_S_soc_S_flash_controller_40023c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_P_interrupts {4 /* 0x4 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_flash_controller_40023c00_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_P_interrupts_IDX_0 4
#define DT_N_S_soc_S_flash_controller_40023c00_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_flash_controller_40023c00_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_P_dma_coherent 0
#define DT_N_S_soc_S_flash_controller_40023c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_40023c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_40023c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_40023c00_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40023c00/flash@1fff7a00
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00
 *
 * Binding (compatible = st,stm32-nvm-otp):
 *   $ZEPHYR_BASE\dts\bindings\otp\st,stm32-nvm-otp.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_PATH "/soc/flash-controller@40023c00/flash@1fff7a00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FULL_NAME "flash@1fff7a00"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FULL_NAME_UNQUOTED flash@1fff7a00
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FULL_NAME_TOKEN flash_1fff7a00
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FULL_NAME_UPPER_TOKEN FLASH_1FFF7A00

/* Node parent (/soc/flash-controller@40023c00) identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_PARENT DT_N_S_soc_S_flash_controller_40023c00

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_NODELABEL_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40023c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_CHILD_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_HASH YVfXyPR0Dh20jtTqBeoMUzv4E2p5psSk0f6r7lMR4Ug

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_ORD 14
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_ORD_STR_SORTABLE 00014

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_REQUIRES_ORDS \
	13, /* /soc/flash-controller@40023c00 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_SUPPORTS_ORDS \
	15, /* /soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_EXISTS 1
#define DT_N_INST_0_st_stm32_nvm_otp DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_REG_IDX_0_VAL_ADDRESS 536836608 /* 0x1fff7a00 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_REG_IDX_0_VAL_SIZE 256 /* 0x100 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_COMPAT_MATCHES_st_stm32_nvm_otp 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_COMPAT_MODEL_IDX_0 "stm32-nvm-otp"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_reg {536836608 /* 0x1fff7a00 */, 256 /* 0x100 */}
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_reg_IDX_0 536836608
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_reg_IDX_1 256
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_compatible {"st,stm32-nvm-otp"}
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_compatible_IDX_0 "st,stm32-nvm-otp"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-nvm-otp
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_compatible_IDX_0_STRING_TOKEN st_stm32_nvm_otp
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_NVM_OTP
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_compatible_LEN 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_dma_coherent 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout
 *
 * Binding (compatible = fixed-layout):
 *   $ZEPHYR_BASE\dts\bindings\nvmem\fixed-layout.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_PATH "/soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FULL_NAME "nvmem-layout"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FULL_NAME_UNQUOTED nvmem-layout
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FULL_NAME_TOKEN nvmem_layout
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FULL_NAME_UPPER_TOKEN NVMEM_LAYOUT

/* Node parent (/soc/flash-controller@40023c00/flash@1fff7a00) identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_PARENT DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_NODELABEL_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00) fn(DT_N_S_soc_S_flash_controller_40023c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_CHILD_NUM 3
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_CHILD_NUM_STATUS_OKAY 3
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_CHILD_UNIT_ADDR_INT_42 DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_CHILD_UNIT_ADDR_INT_44 DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_CHILD_UNIT_ADDR_INT_46 DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_HASH GzI2dAcVXsv_sM__DIqYwoCsI5DSUjwRgZ4JLgUfSH0

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_ORD 15
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_ORD_STR_SORTABLE 00015

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_REQUIRES_ORDS \
	14, /* /soc/flash-controller@40023c00/flash@1fff7a00 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_SUPPORTS_ORDS \
	16, /* /soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout/ts-cal1@2c */ \
	17, /* /soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout/ts-cal2@2e */ \
	33, /* /soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout/vrefint@2a */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_EXISTS 1
#define DT_N_INST_0_fixed_layout DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_REG_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FOREACH_REG(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_COMPAT_MATCHES_fixed_layout 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout/ts-cal1@2c
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_PATH "/soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout/ts-cal1@2c"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FULL_NAME "ts-cal1@2c"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FULL_NAME_UNQUOTED ts-cal1@2c
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FULL_NAME_TOKEN ts_cal1_2c
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FULL_NAME_UPPER_TOKEN TS_CAL1_2C

/* Node parent (/soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout) identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_PARENT DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FOREACH_NODELABEL(fn) fn(ts_cal1_otp)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FOREACH_NODELABEL_VARGS(fn, ...) fn(ts_cal1_otp, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00) fn(DT_N_S_soc_S_flash_controller_40023c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_HASH l7z1KWCsRUwOMQu4ISAFDa9VrBVdevgOf7UJM0dQ10U

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_ORD 16
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_ORD_STR_SORTABLE 00016

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_REQUIRES_ORDS \
	15, /* /soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_SUPPORTS_ORDS \
	18, /* /dietemp */
#define DT_N_NODELABEL_DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_IDX_0_C_TOKEN ts_cal1_otp

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_EXISTS 1
#define DT_N_NODELABEL_ts_cal1_otp DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_REG_IDX_0_VAL_ADDRESS 44 /* 0x2c */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_REG_IDX_0_VAL_SIZE 2 /* 0x2 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_P_reg {44 /* 0x2c */, 2 /* 0x2 */}
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_P_reg_IDX_0 44
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_P_reg_IDX_1 2
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_P_read_only 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c_P_read_only_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout/ts-cal2@2e
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_PATH "/soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout/ts-cal2@2e"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FULL_NAME "ts-cal2@2e"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FULL_NAME_UNQUOTED ts-cal2@2e
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FULL_NAME_TOKEN ts_cal2_2e
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FULL_NAME_UPPER_TOKEN TS_CAL2_2E

/* Node parent (/soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout) identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_PARENT DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FOREACH_NODELABEL(fn) fn(ts_cal2_otp)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FOREACH_NODELABEL_VARGS(fn, ...) fn(ts_cal2_otp, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00) fn(DT_N_S_soc_S_flash_controller_40023c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_HASH t4zEaoePqbVDgg1UnHhPcvKzRlOxzxFbc1NJVuvuGfM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_ORD 17
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_ORD_STR_SORTABLE 00017

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_REQUIRES_ORDS \
	15, /* /soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_SUPPORTS_ORDS \
	18, /* /dietemp */
#define DT_N_NODELABEL_DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_IDX_0_C_TOKEN ts_cal2_otp

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_EXISTS 1
#define DT_N_NODELABEL_ts_cal2_otp DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_REG_IDX_0_VAL_ADDRESS 46 /* 0x2e */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_REG_IDX_0_VAL_SIZE 2 /* 0x2 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_P_reg {46 /* 0x2e */, 2 /* 0x2 */}
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_P_reg_IDX_0 46
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_P_reg_IDX_1 2
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_P_read_only 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e_P_read_only_EXISTS 1

/*
 * Devicetree node: /dietemp
 *
 * Node identifier: DT_N_S_dietemp
 *
 * Binding (compatible = st,stm32-temp-cal):
 *   $ZEPHYR_BASE\dts\bindings\sensor\st,stm32-temp-cal.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_dietemp_PATH "/dietemp"

/* Node's name with unit-address: */
#define DT_N_S_dietemp_FULL_NAME "dietemp"
#define DT_N_S_dietemp_FULL_NAME_UNQUOTED dietemp
#define DT_N_S_dietemp_FULL_NAME_TOKEN dietemp
#define DT_N_S_dietemp_FULL_NAME_UPPER_TOKEN DIETEMP

/* Node parent (/) identifier: */
#define DT_N_S_dietemp_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_dietemp_CHILD_IDX 8

/* Helpers for dealing with node labels: */
#define DT_N_S_dietemp_NODELABEL_NUM 1
#define DT_N_S_dietemp_FOREACH_NODELABEL(fn) fn(die_temp)
#define DT_N_S_dietemp_FOREACH_NODELABEL_VARGS(fn, ...) fn(die_temp, __VA_ARGS__)
#define DT_N_S_dietemp_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_dietemp_CHILD_NUM 0
#define DT_N_S_dietemp_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_dietemp_FOREACH_CHILD(fn) 
#define DT_N_S_dietemp_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_dietemp_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_dietemp_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_dietemp_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_dietemp_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_dietemp_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_dietemp_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_dietemp_HASH 1P3ft3QMjkFq1eBnbB6dz9pZsoSMwhVrPGe82Fpxz6c

/* Node's dependency ordinal: */
#define DT_N_S_dietemp_ORD 18
#define DT_N_S_dietemp_ORD_STR_SORTABLE 00018

/* Ordinals for what this node depends on directly: */
#define DT_N_S_dietemp_REQUIRES_ORDS \
	0, /* / */ \
	12, /* /soc/adc@40012000 */ \
	16, /* /soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout/ts-cal1@2c */ \
	17, /* /soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout/ts-cal2@2e */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_dietemp_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_dietemp_IDX_0_C_TOKEN die_temp

/* Existence and alternate IDs: */
#define DT_N_S_dietemp_EXISTS 1
#define DT_N_ALIAS_die_temp0          DT_N_S_dietemp
#define DT_N_INST_0_st_stm32_temp_cal DT_N_S_dietemp
#define DT_N_NODELABEL_die_temp       DT_N_S_dietemp

/* Macros for properties that are special in the specification: */
#define DT_N_S_dietemp_REG_NUM 0
#define DT_N_S_dietemp_FOREACH_REG(fn) 
#define DT_N_S_dietemp_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_dietemp_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_dietemp_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_dietemp_RANGES_NUM 0
#define DT_N_S_dietemp_FOREACH_RANGE(fn) 
#define DT_N_S_dietemp_IRQ_NUM 0
#define DT_N_S_dietemp_IRQ_LEVEL 0
#define DT_N_S_dietemp_COMPAT_MATCHES_st_stm32_temp_cal 1
#define DT_N_S_dietemp_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_dietemp_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_dietemp_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_dietemp_COMPAT_MODEL_IDX_0 "stm32-temp-cal"
#define DT_N_S_dietemp_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_dietemp_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_dietemp_P_nvmem_cell_names {"TS_CAL1", "TS_CAL2"}
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_0_ENUM_IDX 0
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_1_ENUM_IDX 1
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_0_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_0_ENUM_VAL_ts_cal1_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cell_names_ENUM_VAL_ts_cal1_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_1_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_1_ENUM_VAL_ts_cal2_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cell_names_ENUM_VAL_ts_cal2_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_0 "TS_CAL1"
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_0_STRING_UNQUOTED TS_CAL1
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_0_STRING_TOKEN TS_CAL1
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_0_STRING_UPPER_TOKEN TS_CAL1
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_1 "TS_CAL2"
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_1_STRING_UNQUOTED TS_CAL2
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_1_STRING_TOKEN TS_CAL2
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_1_STRING_UPPER_TOKEN TS_CAL2
#define DT_N_S_dietemp_P_nvmem_cell_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_dietemp, nvmem_cell_names, 0) \
	fn(DT_N_S_dietemp, nvmem_cell_names, 1)
#define DT_N_S_dietemp_P_nvmem_cell_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_dietemp, nvmem_cell_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_dietemp, nvmem_cell_names, 1)
#define DT_N_S_dietemp_P_nvmem_cell_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_dietemp, nvmem_cell_names, 0, __VA_ARGS__) \
	fn(DT_N_S_dietemp, nvmem_cell_names, 1, __VA_ARGS__)
#define DT_N_S_dietemp_P_nvmem_cell_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_dietemp, nvmem_cell_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_dietemp, nvmem_cell_names, 1, __VA_ARGS__)
#define DT_N_S_dietemp_P_nvmem_cell_names_LEN 2
#define DT_N_S_dietemp_P_nvmem_cell_names_EXISTS 1
#define DT_N_S_dietemp_P_ts_cal2_temp 110
#define DT_N_S_dietemp_P_ts_cal2_temp_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cells_IDX_0_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cells_IDX_0_PH DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c
#define DT_N_S_dietemp_P_nvmem_cells_IDX_0_FOREACH_CELL(fn) 
#define DT_N_S_dietemp_P_nvmem_cells_IDX_0_FOREACH_CELL_SEP(fn, sep) 
#define DT_N_S_dietemp_P_nvmem_cells_IDX_0_NUM_CELLS 0
#define DT_N_S_dietemp_P_nvmem_cells_IDX_0_NAME "TS_CAL1"
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal1_IDX 0
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal1_FOREACH_CELL(fn) 
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal1_FOREACH_CELL_SEP(fn, sep) 
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal1_NUM_CELLS 0
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal1_PH DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal1_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cells_IDX_1_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cells_IDX_1_PH DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e
#define DT_N_S_dietemp_P_nvmem_cells_IDX_1_FOREACH_CELL(fn) 
#define DT_N_S_dietemp_P_nvmem_cells_IDX_1_FOREACH_CELL_SEP(fn, sep) 
#define DT_N_S_dietemp_P_nvmem_cells_IDX_1_NUM_CELLS 0
#define DT_N_S_dietemp_P_nvmem_cells_IDX_1_NAME "TS_CAL2"
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal2_IDX 1
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal2_FOREACH_CELL(fn) 
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal2_FOREACH_CELL_SEP(fn, sep) 
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal2_NUM_CELLS 0
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal2_PH DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal2_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cells_FOREACH_PROP_ELEM(fn) fn(DT_N_S_dietemp, nvmem_cells, 0) \
	fn(DT_N_S_dietemp, nvmem_cells, 1)
#define DT_N_S_dietemp_P_nvmem_cells_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_dietemp, nvmem_cells, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_dietemp, nvmem_cells, 1)
#define DT_N_S_dietemp_P_nvmem_cells_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_dietemp, nvmem_cells, 0, __VA_ARGS__) \
	fn(DT_N_S_dietemp, nvmem_cells, 1, __VA_ARGS__)
#define DT_N_S_dietemp_P_nvmem_cells_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_dietemp, nvmem_cells, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_dietemp, nvmem_cells, 1, __VA_ARGS__)
#define DT_N_S_dietemp_P_nvmem_cells_LEN 2
#define DT_N_S_dietemp_P_nvmem_cells_EXISTS 1
#define DT_N_S_dietemp_P_ts_cal1_temp 30
#define DT_N_S_dietemp_P_ts_cal1_temp_EXISTS 1
#define DT_N_S_dietemp_P_ts_cal_vrefanalog 3300
#define DT_N_S_dietemp_P_ts_cal_vrefanalog_EXISTS 1
#define DT_N_S_dietemp_P_ts_cal_resolution 12
#define DT_N_S_dietemp_P_ts_cal_resolution_IDX_0_ENUM_IDX 0
#define DT_N_S_dietemp_P_ts_cal_resolution_IDX_0_EXISTS 1
#define DT_N_S_dietemp_P_ts_cal_resolution_IDX_0_ENUM_VAL_12_EXISTS 1
#define DT_N_S_dietemp_P_ts_cal_resolution_ENUM_VAL_12_EXISTS 1
#define DT_N_S_dietemp_P_ts_cal_resolution_EXISTS 1
#define DT_N_S_dietemp_P_status "okay"
#define DT_N_S_dietemp_P_status_STRING_UNQUOTED okay
#define DT_N_S_dietemp_P_status_STRING_TOKEN okay
#define DT_N_S_dietemp_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_dietemp_P_status_IDX_0 "okay"
#define DT_N_S_dietemp_P_status_IDX_0_EXISTS 1
#define DT_N_S_dietemp_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_dietemp_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_dietemp_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_dietemp_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_dietemp, status, 0)
#define DT_N_S_dietemp_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_dietemp, status, 0)
#define DT_N_S_dietemp_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_dietemp, status, 0, __VA_ARGS__)
#define DT_N_S_dietemp_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_dietemp, status, 0, __VA_ARGS__)
#define DT_N_S_dietemp_P_status_LEN 1
#define DT_N_S_dietemp_P_status_EXISTS 1
#define DT_N_S_dietemp_P_compatible {"st,stm32-temp-cal"}
#define DT_N_S_dietemp_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_dietemp_P_compatible_IDX_0 "st,stm32-temp-cal"
#define DT_N_S_dietemp_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-temp-cal
#define DT_N_S_dietemp_P_compatible_IDX_0_STRING_TOKEN st_stm32_temp_cal
#define DT_N_S_dietemp_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TEMP_CAL
#define DT_N_S_dietemp_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_dietemp, compatible, 0)
#define DT_N_S_dietemp_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_dietemp, compatible, 0)
#define DT_N_S_dietemp_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_dietemp, compatible, 0, __VA_ARGS__)
#define DT_N_S_dietemp_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_dietemp, compatible, 0, __VA_ARGS__)
#define DT_N_S_dietemp_P_compatible_LEN 1
#define DT_N_S_dietemp_P_compatible_EXISTS 1
#define DT_N_S_dietemp_P_dma_coherent 0
#define DT_N_S_dietemp_P_dma_coherent_EXISTS 1
#define DT_N_S_dietemp_P_io_channels_IDX_0_EXISTS 1
#define DT_N_S_dietemp_P_io_channels_IDX_0_PH DT_N_S_soc_S_adc_40012000
#define DT_N_S_dietemp_P_io_channels_IDX_0_VAL_input 18
#define DT_N_S_dietemp_P_io_channels_IDX_0_VAL_input_EXISTS 1
#define DT_N_S_dietemp_P_io_channels_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_dietemp, io_channels, 0, input)
#define DT_N_S_dietemp_P_io_channels_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_dietemp, io_channels, 0, input)
#define DT_N_S_dietemp_P_io_channels_IDX_0_NUM_CELLS 1
#define DT_N_S_dietemp_P_io_channels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_dietemp, io_channels, 0)
#define DT_N_S_dietemp_P_io_channels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_dietemp, io_channels, 0)
#define DT_N_S_dietemp_P_io_channels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_dietemp, io_channels, 0, __VA_ARGS__)
#define DT_N_S_dietemp_P_io_channels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_dietemp, io_channels, 0, __VA_ARGS__)
#define DT_N_S_dietemp_P_io_channels_LEN 1
#define DT_N_S_dietemp_P_io_channels_EXISTS 1
#define DT_N_S_dietemp_P_zephyr_deferred_init 0
#define DT_N_S_dietemp_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_dietemp_P_wakeup_source 0
#define DT_N_S_dietemp_P_wakeup_source_EXISTS 1
#define DT_N_S_dietemp_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_dietemp_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /memory@10000000
 *
 * Node identifier: DT_N_S_memory_10000000
 *
 * Binding (compatible = zephyr,memory-region):
 *   $ZEPHYR_BASE\dts\bindings\base\zephyr,memory-region.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_memory_10000000_PATH "/memory@10000000"

/* Node's name with unit-address: */
#define DT_N_S_memory_10000000_FULL_NAME "memory@10000000"
#define DT_N_S_memory_10000000_FULL_NAME_UNQUOTED memory@10000000
#define DT_N_S_memory_10000000_FULL_NAME_TOKEN memory_10000000
#define DT_N_S_memory_10000000_FULL_NAME_UPPER_TOKEN MEMORY_10000000

/* Node parent (/) identifier: */
#define DT_N_S_memory_10000000_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_memory_10000000_CHILD_IDX 16

/* Helpers for dealing with node labels: */
#define DT_N_S_memory_10000000_NODELABEL_NUM 1
#define DT_N_S_memory_10000000_FOREACH_NODELABEL(fn) fn(ccm0)
#define DT_N_S_memory_10000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(ccm0, __VA_ARGS__)
#define DT_N_S_memory_10000000_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_memory_10000000_CHILD_NUM 0
#define DT_N_S_memory_10000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_memory_10000000_FOREACH_CHILD(fn) 
#define DT_N_S_memory_10000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_memory_10000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_memory_10000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_memory_10000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_memory_10000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_memory_10000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_memory_10000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_memory_10000000_HASH 6bf8mI9ltrZ_8RxtsC_CoudtIJvcGnTP6xk2meUpGW4

/* Node's dependency ordinal: */
#define DT_N_S_memory_10000000_ORD 19
#define DT_N_S_memory_10000000_ORD_STR_SORTABLE 00019

/* Ordinals for what this node depends on directly: */
#define DT_N_S_memory_10000000_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_memory_10000000_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_memory_10000000_IDX_0_C_TOKEN ccm0

/* Existence and alternate IDs: */
#define DT_N_S_memory_10000000_EXISTS 1
#define DT_N_INST_1_zephyr_memory_region DT_N_S_memory_10000000
#define DT_N_INST_0_st_stm32_ccm         DT_N_S_memory_10000000
#define DT_N_NODELABEL_ccm0              DT_N_S_memory_10000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_memory_10000000_REG_NUM 1
#define DT_N_S_memory_10000000_REG_IDX_0_EXISTS 1
#define DT_N_S_memory_10000000_REG_IDX_0_VAL_ADDRESS 268435456 /* 0x10000000 */
#define DT_N_S_memory_10000000_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */
#define DT_N_S_memory_10000000_FOREACH_REG(fn) fn(DT_N_S_memory_10000000, 0)
#define DT_N_S_memory_10000000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_memory_10000000, 0)
#define DT_N_S_memory_10000000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_memory_10000000, 0, __VA_ARGS__)
#define DT_N_S_memory_10000000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_10000000, 0, __VA_ARGS__)
#define DT_N_S_memory_10000000_RANGES_NUM 0
#define DT_N_S_memory_10000000_FOREACH_RANGE(fn) 
#define DT_N_S_memory_10000000_IRQ_NUM 0
#define DT_N_S_memory_10000000_IRQ_LEVEL 0
#define DT_N_S_memory_10000000_COMPAT_MATCHES_zephyr_memory_region 1
#define DT_N_S_memory_10000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_memory_10000000_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_memory_10000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_memory_10000000_COMPAT_MODEL_IDX_0 "memory-region"
#define DT_N_S_memory_10000000_COMPAT_MATCHES_st_stm32_ccm 1
#define DT_N_S_memory_10000000_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_memory_10000000_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_memory_10000000_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_memory_10000000_COMPAT_MODEL_IDX_1 "stm32-ccm"
#define DT_N_S_memory_10000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_memory_10000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_memory_10000000_P_zephyr_memory_region "DTCM"
#define DT_N_S_memory_10000000_P_zephyr_memory_region_STRING_UNQUOTED DTCM
#define DT_N_S_memory_10000000_P_zephyr_memory_region_STRING_TOKEN DTCM
#define DT_N_S_memory_10000000_P_zephyr_memory_region_STRING_UPPER_TOKEN DTCM
#define DT_N_S_memory_10000000_P_zephyr_memory_region_IDX_0 "DTCM"
#define DT_N_S_memory_10000000_P_zephyr_memory_region_IDX_0_EXISTS 1
#define DT_N_S_memory_10000000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_10000000, zephyr_memory_region, 0)
#define DT_N_S_memory_10000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_10000000, zephyr_memory_region, 0)
#define DT_N_S_memory_10000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_memory_10000000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_memory_10000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_10000000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_memory_10000000_P_zephyr_memory_region_LEN 1
#define DT_N_S_memory_10000000_P_zephyr_memory_region_EXISTS 1
#define DT_N_S_memory_10000000_P_compatible {"zephyr,memory-region", "st,stm32-ccm"}
#define DT_N_S_memory_10000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_memory_10000000_P_compatible_IDX_0 "zephyr,memory-region"
#define DT_N_S_memory_10000000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,memory-region
#define DT_N_S_memory_10000000_P_compatible_IDX_0_STRING_TOKEN zephyr_memory_region
#define DT_N_S_memory_10000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MEMORY_REGION
#define DT_N_S_memory_10000000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_memory_10000000_P_compatible_IDX_1 "st,stm32-ccm"
#define DT_N_S_memory_10000000_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-ccm
#define DT_N_S_memory_10000000_P_compatible_IDX_1_STRING_TOKEN st_stm32_ccm
#define DT_N_S_memory_10000000_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_CCM
#define DT_N_S_memory_10000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_10000000, compatible, 0) \
	fn(DT_N_S_memory_10000000, compatible, 1)
#define DT_N_S_memory_10000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_10000000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_memory_10000000, compatible, 1)
#define DT_N_S_memory_10000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_memory_10000000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_memory_10000000, compatible, 1, __VA_ARGS__)
#define DT_N_S_memory_10000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_10000000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_memory_10000000, compatible, 1, __VA_ARGS__)
#define DT_N_S_memory_10000000_P_compatible_LEN 2
#define DT_N_S_memory_10000000_P_compatible_EXISTS 1
#define DT_N_S_memory_10000000_P_reg {268435456 /* 0x10000000 */, 65536 /* 0x10000 */}
#define DT_N_S_memory_10000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_memory_10000000_P_reg_IDX_0 268435456
#define DT_N_S_memory_10000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_memory_10000000_P_reg_IDX_1 65536
#define DT_N_S_memory_10000000_P_reg_EXISTS 1
#define DT_N_S_memory_10000000_P_dma_coherent 0
#define DT_N_S_memory_10000000_P_dma_coherent_EXISTS 1
#define DT_N_S_memory_10000000_P_zephyr_deferred_init 0
#define DT_N_S_memory_10000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_memory_10000000_P_wakeup_source 0
#define DT_N_S_memory_10000000_P_wakeup_source_EXISTS 1
#define DT_N_S_memory_10000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_memory_10000000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /memory@20000000
 *
 * Node identifier: DT_N_S_memory_20000000
 *
 * Binding (compatible = zephyr,memory-region):
 *   $ZEPHYR_BASE\dts\bindings\base\zephyr,memory-region.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_memory_20000000_PATH "/memory@20000000"

/* Node's name with unit-address: */
#define DT_N_S_memory_20000000_FULL_NAME "memory@20000000"
#define DT_N_S_memory_20000000_FULL_NAME_UNQUOTED memory@20000000
#define DT_N_S_memory_20000000_FULL_NAME_TOKEN memory_20000000
#define DT_N_S_memory_20000000_FULL_NAME_UPPER_TOKEN MEMORY_20000000

/* Node parent (/) identifier: */
#define DT_N_S_memory_20000000_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_memory_20000000_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_memory_20000000_NODELABEL_NUM 1
#define DT_N_S_memory_20000000_FOREACH_NODELABEL(fn) fn(sram0)
#define DT_N_S_memory_20000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sram0, __VA_ARGS__)
#define DT_N_S_memory_20000000_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_memory_20000000_CHILD_NUM 0
#define DT_N_S_memory_20000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_memory_20000000_FOREACH_CHILD(fn) 
#define DT_N_S_memory_20000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_memory_20000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_memory_20000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_memory_20000000_HASH Ppv28MrjF0V_ocFctWWy62TJJRdbnlSCTerwKpAvZ6U

/* Node's dependency ordinal: */
#define DT_N_S_memory_20000000_ORD 20
#define DT_N_S_memory_20000000_ORD_STR_SORTABLE 00020

/* Ordinals for what this node depends on directly: */
#define DT_N_S_memory_20000000_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_memory_20000000_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_memory_20000000_IDX_0_C_TOKEN sram0

/* Existence and alternate IDs: */
#define DT_N_S_memory_20000000_EXISTS 1
#define DT_N_INST_0_zephyr_memory_region DT_N_S_memory_20000000
#define DT_N_INST_0_mmio_sram            DT_N_S_memory_20000000
#define DT_N_NODELABEL_sram0             DT_N_S_memory_20000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_memory_20000000_REG_NUM 1
#define DT_N_S_memory_20000000_REG_IDX_0_EXISTS 1
#define DT_N_S_memory_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */
#define DT_N_S_memory_20000000_REG_IDX_0_VAL_SIZE 196608 /* 0x30000 */
#define DT_N_S_memory_20000000_FOREACH_REG(fn) fn(DT_N_S_memory_20000000, 0)
#define DT_N_S_memory_20000000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_memory_20000000, 0)
#define DT_N_S_memory_20000000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_memory_20000000, 0, __VA_ARGS__)
#define DT_N_S_memory_20000000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_20000000, 0, __VA_ARGS__)
#define DT_N_S_memory_20000000_RANGES_NUM 0
#define DT_N_S_memory_20000000_FOREACH_RANGE(fn) 
#define DT_N_S_memory_20000000_IRQ_NUM 0
#define DT_N_S_memory_20000000_IRQ_LEVEL 0
#define DT_N_S_memory_20000000_COMPAT_MATCHES_zephyr_memory_region 1
#define DT_N_S_memory_20000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_memory_20000000_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_memory_20000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_memory_20000000_COMPAT_MODEL_IDX_0 "memory-region"
#define DT_N_S_memory_20000000_COMPAT_MATCHES_mmio_sram 1
#define DT_N_S_memory_20000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_memory_20000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_memory_20000000_P_zephyr_memory_region "SRAM0"
#define DT_N_S_memory_20000000_P_zephyr_memory_region_STRING_UNQUOTED SRAM0
#define DT_N_S_memory_20000000_P_zephyr_memory_region_STRING_TOKEN SRAM0
#define DT_N_S_memory_20000000_P_zephyr_memory_region_STRING_UPPER_TOKEN SRAM0
#define DT_N_S_memory_20000000_P_zephyr_memory_region_IDX_0 "SRAM0"
#define DT_N_S_memory_20000000_P_zephyr_memory_region_IDX_0_EXISTS 1
#define DT_N_S_memory_20000000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_20000000, zephyr_memory_region, 0)
#define DT_N_S_memory_20000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_20000000, zephyr_memory_region, 0)
#define DT_N_S_memory_20000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_memory_20000000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_memory_20000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_20000000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_memory_20000000_P_zephyr_memory_region_LEN 1
#define DT_N_S_memory_20000000_P_zephyr_memory_region_EXISTS 1
#define DT_N_S_memory_20000000_P_compatible {"zephyr,memory-region", "mmio-sram"}
#define DT_N_S_memory_20000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_memory_20000000_P_compatible_IDX_0 "zephyr,memory-region"
#define DT_N_S_memory_20000000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,memory-region
#define DT_N_S_memory_20000000_P_compatible_IDX_0_STRING_TOKEN zephyr_memory_region
#define DT_N_S_memory_20000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MEMORY_REGION
#define DT_N_S_memory_20000000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_memory_20000000_P_compatible_IDX_1 "mmio-sram"
#define DT_N_S_memory_20000000_P_compatible_IDX_1_STRING_UNQUOTED mmio-sram
#define DT_N_S_memory_20000000_P_compatible_IDX_1_STRING_TOKEN mmio_sram
#define DT_N_S_memory_20000000_P_compatible_IDX_1_STRING_UPPER_TOKEN MMIO_SRAM
#define DT_N_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_20000000, compatible, 0) \
	fn(DT_N_S_memory_20000000, compatible, 1)
#define DT_N_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_20000000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_memory_20000000, compatible, 1)
#define DT_N_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_memory_20000000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_memory_20000000, compatible, 1, __VA_ARGS__)
#define DT_N_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_20000000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_memory_20000000, compatible, 1, __VA_ARGS__)
#define DT_N_S_memory_20000000_P_compatible_LEN 2
#define DT_N_S_memory_20000000_P_compatible_EXISTS 1
#define DT_N_S_memory_20000000_P_reg {536870912 /* 0x20000000 */, 196608 /* 0x30000 */}
#define DT_N_S_memory_20000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_memory_20000000_P_reg_IDX_0 536870912
#define DT_N_S_memory_20000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_memory_20000000_P_reg_IDX_1 196608
#define DT_N_S_memory_20000000_P_reg_EXISTS 1
#define DT_N_S_memory_20000000_P_dma_coherent 0
#define DT_N_S_memory_20000000_P_dma_coherent_EXISTS 1
#define DT_N_S_memory_20000000_P_zephyr_deferred_init 0
#define DT_N_S_memory_20000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_memory_20000000_P_wakeup_source 0
#define DT_N_S_memory_20000000_P_wakeup_source_EXISTS 1
#define DT_N_S_memory_20000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_memory_20000000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/gpio@40020400
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400
 *
 * Binding (compatible = st,stm32-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\st,stm32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_PATH "/soc/pin-controller@40020000/gpio@40020400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FULL_NAME "gpio@40020400"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FULL_NAME_UNQUOTED gpio@40020400
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FULL_NAME_TOKEN gpio_40020400
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FULL_NAME_UPPER_TOKEN GPIO_40020400

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FOREACH_NODELABEL(fn) fn(gpiob)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpiob, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_HASH 5B6ZiPFOwJu5ZVGeuzPdH55YbecC_f_Lt_xjGeIa_TM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_ORD 21
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_ORD_STR_SORTABLE 00021

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_REQUIRES_ORDS \
	9, /* /soc/rcc@40023800 */ \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_SUPPORTS_ORDS \
	24, /* /soc/i2c@40005400 */ \
	28, /* /soc/i2c@40005800 */ \
	47, /* /leds */ \
	48, /* /leds/led_1 */ \
	49, /* /leds/led_2 */ \
	50, /* /leds/led_3 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_IDX_0_C_TOKEN gpiob

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_EXISTS 1
#define DT_N_INST_1_st_stm32_gpio DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400
#define DT_N_NODELABEL_gpiob      DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_REG_IDX_0_VAL_ADDRESS 1073873920 /* 0x40020400 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_COMPAT_MATCHES_st_stm32_gpio 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_COMPAT_MODEL_IDX_0 "stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_reg {1073873920 /* 0x40020400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_reg_IDX_0 1073873920
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_clocks_IDX_0_VAL_bus 48
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_clocks_IDX_0_VAL_bits 2
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_clocks_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_ngpios 16
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_gpio_controller 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_compatible {"st,stm32-gpio"}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_compatible_IDX_0 "st,stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/i2c1_scl_pb8
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_PATH "/soc/pin-controller@40020000/i2c1_scl_pb8"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FULL_NAME "i2c1_scl_pb8"
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FULL_NAME_UNQUOTED i2c1_scl_pb8
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FULL_NAME_TOKEN i2c1_scl_pb8
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FULL_NAME_UPPER_TOKEN I2C1_SCL_PB8

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_CHILD_IDX 22

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FOREACH_NODELABEL(fn) fn(i2c1_scl_pb8)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c1_scl_pb8, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_HASH 8tCp_6oXPPIeTHzWmAx3zKQeOKqXosD5O2nnvmMtMbs

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_ORD 22
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_ORD_STR_SORTABLE 00022

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_SUPPORTS_ORDS \
	24, /* /soc/i2c@40005400 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_IDX_0_C_TOKEN i2c1_scl_pb8

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_EXISTS 1
#define DT_N_NODELABEL_i2c1_scl_pb8 DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_pinmux 772
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_bias_pull_up 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_drive_open_drain 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/i2c1_sda_pb9
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_PATH "/soc/pin-controller@40020000/i2c1_sda_pb9"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FULL_NAME "i2c1_sda_pb9"
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FULL_NAME_UNQUOTED i2c1_sda_pb9
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FULL_NAME_TOKEN i2c1_sda_pb9
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FULL_NAME_UPPER_TOKEN I2C1_SDA_PB9

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_CHILD_IDX 24

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FOREACH_NODELABEL(fn) fn(i2c1_sda_pb9)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c1_sda_pb9, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_HASH 8qR0PIokEoo5mzn1NJBFF8a6BLK54a_eXfL3hvYeVwU

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_ORD 23
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_ORD_STR_SORTABLE 00023

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_SUPPORTS_ORDS \
	24, /* /soc/i2c@40005400 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_IDX_0_C_TOKEN i2c1_sda_pb9

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_EXISTS 1
#define DT_N_NODELABEL_i2c1_sda_pb9 DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_pinmux 804
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_bias_pull_up 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_drive_open_drain 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/i2c@40005400
 *
 * Node identifier: DT_N_S_soc_S_i2c_40005400
 *
 * Binding (compatible = st,stm32-i2c-v1):
 *   $ZEPHYR_BASE\dts\bindings\i2c\st,stm32-i2c-v1.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_i2c_40005400_PATH "/soc/i2c@40005400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_i2c_40005400_FULL_NAME "i2c@40005400"
#define DT_N_S_soc_S_i2c_40005400_FULL_NAME_UNQUOTED i2c@40005400
#define DT_N_S_soc_S_i2c_40005400_FULL_NAME_TOKEN i2c_40005400
#define DT_N_S_soc_S_i2c_40005400_FULL_NAME_UPPER_TOKEN I2C_40005400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_i2c_40005400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_i2c_40005400_CHILD_IDX 11

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_i2c_40005400_NODELABEL_NUM 2
#define DT_N_S_soc_S_i2c_40005400_FOREACH_NODELABEL(fn) fn(i2c1) fn(arduino_i2c)
#define DT_N_S_soc_S_i2c_40005400_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c1, __VA_ARGS__) fn(arduino_i2c, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_i2c_40005400_CHILD_NUM 0
#define DT_N_S_soc_S_i2c_40005400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_i2c_40005400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_i2c_40005400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_40005400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_40005400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_i2c_40005400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_i2c_40005400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_40005400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_40005400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_i2c_40005400_HASH qdcoGqslkp_qGZ59SAaN4H47YRea2PU_8MI_v34YdEo

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_i2c_40005400_ORD 24
#define DT_N_S_soc_S_i2c_40005400_ORD_STR_SORTABLE 00024

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_i2c_40005400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	21, /* /soc/pin-controller@40020000/gpio@40020400 */ \
	22, /* /soc/pin-controller@40020000/i2c1_scl_pb8 */ \
	23, /* /soc/pin-controller@40020000/i2c1_sda_pb9 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_i2c_40005400_SUPPORTS_ORDS \
	25, /* /smbus1 */
#define DT_N_NODELABEL_DT_N_S_soc_S_i2c_40005400_IDX_0_C_TOKEN i2c1
#define DT_N_NODELABEL_DT_N_S_soc_S_i2c_40005400_IDX_1_C_TOKEN arduino_i2c

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_i2c_40005400_EXISTS 1
#define DT_N_INST_0_st_stm32_i2c_v1 DT_N_S_soc_S_i2c_40005400
#define DT_N_NODELABEL_i2c1         DT_N_S_soc_S_i2c_40005400
#define DT_N_NODELABEL_arduino_i2c  DT_N_S_soc_S_i2c_40005400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_i2c_40005400_REG_NUM 1
#define DT_N_S_soc_S_i2c_40005400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_REG_IDX_0_VAL_ADDRESS 1073763328 /* 0x40005400 */
#define DT_N_S_soc_S_i2c_40005400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_i2c_40005400_FOREACH_REG(fn) fn(DT_N_S_soc_S_i2c_40005400, 0)
#define DT_N_S_soc_S_i2c_40005400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, 0)
#define DT_N_S_soc_S_i2c_40005400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_RANGES_NUM 0
#define DT_N_S_soc_S_i2c_40005400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_i2c_40005400_IRQ_NUM 2
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_VAL_irq 31
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_VAL_irq 32
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_i2c_40005400_IRQ_LEVEL 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_event_VAL_irq DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_event_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_event_VAL_priority DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_event_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_event_CONTROLLER DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_error_VAL_irq DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_VAL_irq
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_error_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_error_VAL_priority DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_VAL_priority
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_error_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_error_CONTROLLER DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_CONTROLLER
#define DT_N_S_soc_S_i2c_40005400_COMPAT_MATCHES_st_stm32_i2c_v1 1
#define DT_N_S_soc_S_i2c_40005400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_i2c_40005400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_COMPAT_MODEL_IDX_0 "stm32-i2c-v1"
#define DT_N_S_soc_S_i2c_40005400_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_i2c_40005400_PINCTRL_NUM 1
#define DT_N_S_soc_S_i2c_40005400_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_i2c_40005400_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_i2c_40005400_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_i2c_40005400_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8
#define DT_N_S_soc_S_i2c_40005400_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9

/* Generic property macros: */
#define DT_N_S_soc_S_i2c_40005400_P_reg {1073763328 /* 0x40005400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_i2c_40005400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_reg_IDX_0 1073763328
#define DT_N_S_soc_S_i2c_40005400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_i2c_40005400_P_reg_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_interrupts {31 /* 0x1f */, 0 /* 0x0 */, 32 /* 0x20 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_0 31
#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_2 32
#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_i2c_40005400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 0) \
	fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 1)
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 1)
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_LEN 2
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_names, 0)
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_names, 0)
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_scl_gpios_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_scl_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400
#define DT_N_S_soc_S_i2c_40005400_P_scl_gpios_IDX_0_VAL_pin 8
#define DT_N_S_soc_S_i2c_40005400_P_scl_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_scl_gpios_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_i2c_40005400_P_scl_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_scl_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2c_40005400, scl_gpios, 0, pin) \
	fn(DT_N_S_soc_S_i2c_40005400, scl_gpios, 0, flags)
#define DT_N_S_soc_S_i2c_40005400_P_scl_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, scl_gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005400, scl_gpios, 0, flags)
#define DT_N_S_soc_S_i2c_40005400_P_scl_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_i2c_40005400_P_scl_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, scl_gpios, 0)
#define DT_N_S_soc_S_i2c_40005400_P_scl_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, scl_gpios, 0)
#define DT_N_S_soc_S_i2c_40005400_P_scl_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, scl_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_scl_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, scl_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_scl_gpios_LEN 1
#define DT_N_S_soc_S_i2c_40005400_P_scl_gpios_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_sda_gpios_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_sda_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400
#define DT_N_S_soc_S_i2c_40005400_P_sda_gpios_IDX_0_VAL_pin 9
#define DT_N_S_soc_S_i2c_40005400_P_sda_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_sda_gpios_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_i2c_40005400_P_sda_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_sda_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2c_40005400, sda_gpios, 0, pin) \
	fn(DT_N_S_soc_S_i2c_40005400, sda_gpios, 0, flags)
#define DT_N_S_soc_S_i2c_40005400_P_sda_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, sda_gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005400, sda_gpios, 0, flags)
#define DT_N_S_soc_S_i2c_40005400_P_sda_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_i2c_40005400_P_sda_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, sda_gpios, 0)
#define DT_N_S_soc_S_i2c_40005400_P_sda_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, sda_gpios, 0)
#define DT_N_S_soc_S_i2c_40005400_P_sda_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, sda_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_sda_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, sda_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_sda_gpios_LEN 1
#define DT_N_S_soc_S_i2c_40005400_P_sda_gpios_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_clock_frequency 400000
#define DT_N_S_soc_S_i2c_40005400_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_sq_size 4
#define DT_N_S_soc_S_i2c_40005400_P_sq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_cq_size 4
#define DT_N_S_soc_S_i2c_40005400_P_cq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_status "okay"
#define DT_N_S_soc_S_i2c_40005400_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_i2c_40005400_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_i2c_40005400_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_i2c_40005400_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_i2c_40005400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_i2c_40005400_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, status, 0)
#define DT_N_S_soc_S_i2c_40005400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, status, 0)
#define DT_N_S_soc_S_i2c_40005400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_status_LEN 1
#define DT_N_S_soc_S_i2c_40005400_P_status_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_compatible {"st,stm32-i2c-v1"}
#define DT_N_S_soc_S_i2c_40005400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_compatible_IDX_0 "st,stm32-i2c-v1"
#define DT_N_S_soc_S_i2c_40005400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-i2c-v1
#define DT_N_S_soc_S_i2c_40005400_P_compatible_IDX_0_STRING_TOKEN st_stm32_i2c_v1
#define DT_N_S_soc_S_i2c_40005400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_I2C_V1
#define DT_N_S_soc_S_i2c_40005400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, compatible, 0)
#define DT_N_S_soc_S_i2c_40005400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, compatible, 0)
#define DT_N_S_soc_S_i2c_40005400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_compatible_LEN 1
#define DT_N_S_soc_S_i2c_40005400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names {"event", "error"}
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_0 "event"
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_0_STRING_UNQUOTED event
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_0_STRING_TOKEN event
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN EVENT
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_1 "error"
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_1_STRING_UNQUOTED error
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_1_STRING_TOKEN error
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN ERROR
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 0) \
	fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 1)
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 1)
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_LEN 2
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_i2c_40005400_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_i2c_40005400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_clocks_IDX_0_VAL_bits 2097152
#define DT_N_S_soc_S_i2c_40005400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2c_40005400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_i2c_40005400, clocks, 0, bits)
#define DT_N_S_soc_S_i2c_40005400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005400, clocks, 0, bits)
#define DT_N_S_soc_S_i2c_40005400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_i2c_40005400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, clocks, 0)
#define DT_N_S_soc_S_i2c_40005400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, clocks, 0)
#define DT_N_S_soc_S_i2c_40005400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_clocks_LEN 1
#define DT_N_S_soc_S_i2c_40005400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_dma_coherent 0
#define DT_N_S_soc_S_i2c_40005400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_i2c_40005400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_wakeup_source 0
#define DT_N_S_soc_S_i2c_40005400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_i2c_40005400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /smbus1
 *
 * Node identifier: DT_N_S_smbus1
 *
 * Binding (compatible = st,stm32-smbus):
 *   $ZEPHYR_BASE\dts\bindings\smbus\st,stm32-smbus.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_smbus1_PATH "/smbus1"

/* Node's name with unit-address: */
#define DT_N_S_smbus1_FULL_NAME "smbus1"
#define DT_N_S_smbus1_FULL_NAME_UNQUOTED smbus1
#define DT_N_S_smbus1_FULL_NAME_TOKEN smbus1
#define DT_N_S_smbus1_FULL_NAME_UPPER_TOKEN SMBUS1

/* Node parent (/) identifier: */
#define DT_N_S_smbus1_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_smbus1_CHILD_IDX 12

/* Helpers for dealing with node labels: */
#define DT_N_S_smbus1_NODELABEL_NUM 1
#define DT_N_S_smbus1_FOREACH_NODELABEL(fn) fn(smbus1)
#define DT_N_S_smbus1_FOREACH_NODELABEL_VARGS(fn, ...) fn(smbus1, __VA_ARGS__)
#define DT_N_S_smbus1_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_smbus1_CHILD_NUM 0
#define DT_N_S_smbus1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_smbus1_FOREACH_CHILD(fn) 
#define DT_N_S_smbus1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_smbus1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_smbus1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_smbus1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_smbus1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_smbus1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_smbus1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_smbus1_HASH RRjxCtQo8vEaNES3pUGCHfX2Mp6H0kS5wnsZuRpKBrY

/* Node's dependency ordinal: */
#define DT_N_S_smbus1_ORD 25
#define DT_N_S_smbus1_ORD_STR_SORTABLE 00025

/* Ordinals for what this node depends on directly: */
#define DT_N_S_smbus1_REQUIRES_ORDS \
	0, /* / */ \
	24, /* /soc/i2c@40005400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_smbus1_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_smbus1_IDX_0_C_TOKEN smbus1

/* Existence and alternate IDs: */
#define DT_N_S_smbus1_EXISTS 1
#define DT_N_INST_0_st_stm32_smbus DT_N_S_smbus1
#define DT_N_NODELABEL_smbus1      DT_N_S_smbus1

/* Macros for properties that are special in the specification: */
#define DT_N_S_smbus1_REG_NUM 0
#define DT_N_S_smbus1_FOREACH_REG(fn) 
#define DT_N_S_smbus1_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_smbus1_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_smbus1_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_smbus1_RANGES_NUM 0
#define DT_N_S_smbus1_FOREACH_RANGE(fn) 
#define DT_N_S_smbus1_IRQ_NUM 0
#define DT_N_S_smbus1_IRQ_LEVEL 0
#define DT_N_S_smbus1_COMPAT_MATCHES_st_stm32_smbus 1
#define DT_N_S_smbus1_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_smbus1_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_smbus1_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_smbus1_COMPAT_MODEL_IDX_0 "stm32-smbus"
#define DT_N_S_smbus1_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_smbus1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_smbus1_P_i2c DT_N_S_soc_S_i2c_40005400
#define DT_N_S_smbus1_P_i2c_IDX_0 DT_N_S_soc_S_i2c_40005400
#define DT_N_S_smbus1_P_i2c_IDX_0_PH DT_N_S_soc_S_i2c_40005400
#define DT_N_S_smbus1_P_i2c_IDX_0_EXISTS 1
#define DT_N_S_smbus1_P_i2c_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus1, i2c, 0)
#define DT_N_S_smbus1_P_i2c_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus1, i2c, 0)
#define DT_N_S_smbus1_P_i2c_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus1, i2c, 0, __VA_ARGS__)
#define DT_N_S_smbus1_P_i2c_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus1, i2c, 0, __VA_ARGS__)
#define DT_N_S_smbus1_P_i2c_LEN 1
#define DT_N_S_smbus1_P_i2c_EXISTS 1
#define DT_N_S_smbus1_P_status "disabled"
#define DT_N_S_smbus1_P_status_STRING_UNQUOTED disabled
#define DT_N_S_smbus1_P_status_STRING_TOKEN disabled
#define DT_N_S_smbus1_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_smbus1_P_status_IDX_0 "disabled"
#define DT_N_S_smbus1_P_status_IDX_0_EXISTS 1
#define DT_N_S_smbus1_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_smbus1_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_smbus1_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_smbus1_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus1, status, 0)
#define DT_N_S_smbus1_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus1, status, 0)
#define DT_N_S_smbus1_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus1, status, 0, __VA_ARGS__)
#define DT_N_S_smbus1_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus1, status, 0, __VA_ARGS__)
#define DT_N_S_smbus1_P_status_LEN 1
#define DT_N_S_smbus1_P_status_EXISTS 1
#define DT_N_S_smbus1_P_compatible {"st,stm32-smbus"}
#define DT_N_S_smbus1_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_smbus1_P_compatible_IDX_0 "st,stm32-smbus"
#define DT_N_S_smbus1_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-smbus
#define DT_N_S_smbus1_P_compatible_IDX_0_STRING_TOKEN st_stm32_smbus
#define DT_N_S_smbus1_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SMBUS
#define DT_N_S_smbus1_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus1, compatible, 0)
#define DT_N_S_smbus1_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus1, compatible, 0)
#define DT_N_S_smbus1_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus1, compatible, 0, __VA_ARGS__)
#define DT_N_S_smbus1_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus1, compatible, 0, __VA_ARGS__)
#define DT_N_S_smbus1_P_compatible_LEN 1
#define DT_N_S_smbus1_P_compatible_EXISTS 1
#define DT_N_S_smbus1_P_dma_coherent 0
#define DT_N_S_smbus1_P_dma_coherent_EXISTS 1
#define DT_N_S_smbus1_P_zephyr_deferred_init 0
#define DT_N_S_smbus1_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_smbus1_P_wakeup_source 0
#define DT_N_S_smbus1_P_wakeup_source_EXISTS 1
#define DT_N_S_smbus1_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_smbus1_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/i2c2_scl_pb10
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_PATH "/soc/pin-controller@40020000/i2c2_scl_pb10"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FULL_NAME "i2c2_scl_pb10"
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FULL_NAME_UNQUOTED i2c2_scl_pb10
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FULL_NAME_TOKEN i2c2_scl_pb10
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FULL_NAME_UPPER_TOKEN I2C2_SCL_PB10

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_CHILD_IDX 23

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FOREACH_NODELABEL(fn) fn(i2c2_scl_pb10)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c2_scl_pb10, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_HASH 9DseBQHjwIc8sZlck8RYuPqXV02c9LomZ1ndDGhsLI0

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_ORD 26
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_ORD_STR_SORTABLE 00026

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_SUPPORTS_ORDS \
	28, /* /soc/i2c@40005800 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_IDX_0_C_TOKEN i2c2_scl_pb10

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_EXISTS 1
#define DT_N_NODELABEL_i2c2_scl_pb10 DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_pinmux 836
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_bias_pull_up 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_drive_open_drain 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/i2c2_sda_pb11
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_PATH "/soc/pin-controller@40020000/i2c2_sda_pb11"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FULL_NAME "i2c2_sda_pb11"
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FULL_NAME_UNQUOTED i2c2_sda_pb11
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FULL_NAME_TOKEN i2c2_sda_pb11
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FULL_NAME_UPPER_TOKEN I2C2_SDA_PB11

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_CHILD_IDX 25

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FOREACH_NODELABEL(fn) fn(i2c2_sda_pb11)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c2_sda_pb11, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_HASH lSrlNeJVRpqpnZHuDVCJlWfpY7WtzH7yc7PPmRN00Q4

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_ORD 27
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_ORD_STR_SORTABLE 00027

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_SUPPORTS_ORDS \
	28, /* /soc/i2c@40005800 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_IDX_0_C_TOKEN i2c2_sda_pb11

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_EXISTS 1
#define DT_N_NODELABEL_i2c2_sda_pb11 DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_pinmux 868
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_bias_pull_up 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_drive_open_drain 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/i2c@40005800
 *
 * Node identifier: DT_N_S_soc_S_i2c_40005800
 *
 * Binding (compatible = st,stm32-i2c-v1):
 *   $ZEPHYR_BASE\dts\bindings\i2c\st,stm32-i2c-v1.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_i2c_40005800_PATH "/soc/i2c@40005800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_i2c_40005800_FULL_NAME "i2c@40005800"
#define DT_N_S_soc_S_i2c_40005800_FULL_NAME_UNQUOTED i2c@40005800
#define DT_N_S_soc_S_i2c_40005800_FULL_NAME_TOKEN i2c_40005800
#define DT_N_S_soc_S_i2c_40005800_FULL_NAME_UPPER_TOKEN I2C_40005800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_i2c_40005800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_i2c_40005800_CHILD_IDX 12

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_i2c_40005800_NODELABEL_NUM 1
#define DT_N_S_soc_S_i2c_40005800_FOREACH_NODELABEL(fn) fn(i2c2)
#define DT_N_S_soc_S_i2c_40005800_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c2, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_i2c_40005800_CHILD_NUM 0
#define DT_N_S_soc_S_i2c_40005800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_i2c_40005800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_i2c_40005800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_40005800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_40005800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_i2c_40005800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_i2c_40005800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_40005800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_40005800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_i2c_40005800_HASH eB73TQqq_PUOgKTcnvcwzuS4tWCFU0fUXyPb0bwWGkQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_i2c_40005800_ORD 28
#define DT_N_S_soc_S_i2c_40005800_ORD_STR_SORTABLE 00028

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_i2c_40005800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	21, /* /soc/pin-controller@40020000/gpio@40020400 */ \
	26, /* /soc/pin-controller@40020000/i2c2_scl_pb10 */ \
	27, /* /soc/pin-controller@40020000/i2c2_sda_pb11 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_i2c_40005800_SUPPORTS_ORDS \
	29, /* /smbus2 */
#define DT_N_NODELABEL_DT_N_S_soc_S_i2c_40005800_IDX_0_C_TOKEN i2c2

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_i2c_40005800_EXISTS 1
#define DT_N_INST_1_st_stm32_i2c_v1 DT_N_S_soc_S_i2c_40005800
#define DT_N_NODELABEL_i2c2         DT_N_S_soc_S_i2c_40005800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_i2c_40005800_REG_NUM 1
#define DT_N_S_soc_S_i2c_40005800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_REG_IDX_0_VAL_ADDRESS 1073764352 /* 0x40005800 */
#define DT_N_S_soc_S_i2c_40005800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_i2c_40005800_FOREACH_REG(fn) fn(DT_N_S_soc_S_i2c_40005800, 0)
#define DT_N_S_soc_S_i2c_40005800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, 0)
#define DT_N_S_soc_S_i2c_40005800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_RANGES_NUM 0
#define DT_N_S_soc_S_i2c_40005800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_i2c_40005800_IRQ_NUM 2
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_VAL_irq 33
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_VAL_irq 34
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_i2c_40005800_IRQ_LEVEL 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_event_VAL_irq DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_event_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_event_VAL_priority DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_event_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_event_CONTROLLER DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_error_VAL_irq DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_VAL_irq
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_error_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_error_VAL_priority DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_VAL_priority
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_error_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_error_CONTROLLER DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_CONTROLLER
#define DT_N_S_soc_S_i2c_40005800_COMPAT_MATCHES_st_stm32_i2c_v1 1
#define DT_N_S_soc_S_i2c_40005800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_i2c_40005800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_COMPAT_MODEL_IDX_0 "stm32-i2c-v1"
#define DT_N_S_soc_S_i2c_40005800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_i2c_40005800_PINCTRL_NUM 1
#define DT_N_S_soc_S_i2c_40005800_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_i2c_40005800_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_i2c_40005800_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_i2c_40005800_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10
#define DT_N_S_soc_S_i2c_40005800_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11

/* Generic property macros: */
#define DT_N_S_soc_S_i2c_40005800_P_reg {1073764352 /* 0x40005800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_i2c_40005800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_reg_IDX_0 1073764352
#define DT_N_S_soc_S_i2c_40005800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_i2c_40005800_P_reg_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_interrupts {33 /* 0x21 */, 0 /* 0x0 */, 34 /* 0x22 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_0 33
#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_2 34
#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_i2c_40005800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 0) \
	fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 1)
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 1)
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_LEN 2
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_names, 0)
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_names, 0)
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_scl_gpios_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_scl_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400
#define DT_N_S_soc_S_i2c_40005800_P_scl_gpios_IDX_0_VAL_pin 10
#define DT_N_S_soc_S_i2c_40005800_P_scl_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_scl_gpios_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_i2c_40005800_P_scl_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_scl_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2c_40005800, scl_gpios, 0, pin) \
	fn(DT_N_S_soc_S_i2c_40005800, scl_gpios, 0, flags)
#define DT_N_S_soc_S_i2c_40005800_P_scl_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, scl_gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005800, scl_gpios, 0, flags)
#define DT_N_S_soc_S_i2c_40005800_P_scl_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_i2c_40005800_P_scl_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, scl_gpios, 0)
#define DT_N_S_soc_S_i2c_40005800_P_scl_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, scl_gpios, 0)
#define DT_N_S_soc_S_i2c_40005800_P_scl_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, scl_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_scl_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, scl_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_scl_gpios_LEN 1
#define DT_N_S_soc_S_i2c_40005800_P_scl_gpios_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_sda_gpios_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_sda_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400
#define DT_N_S_soc_S_i2c_40005800_P_sda_gpios_IDX_0_VAL_pin 11
#define DT_N_S_soc_S_i2c_40005800_P_sda_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_sda_gpios_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_i2c_40005800_P_sda_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_sda_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2c_40005800, sda_gpios, 0, pin) \
	fn(DT_N_S_soc_S_i2c_40005800, sda_gpios, 0, flags)
#define DT_N_S_soc_S_i2c_40005800_P_sda_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, sda_gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005800, sda_gpios, 0, flags)
#define DT_N_S_soc_S_i2c_40005800_P_sda_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_i2c_40005800_P_sda_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, sda_gpios, 0)
#define DT_N_S_soc_S_i2c_40005800_P_sda_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, sda_gpios, 0)
#define DT_N_S_soc_S_i2c_40005800_P_sda_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, sda_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_sda_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, sda_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_sda_gpios_LEN 1
#define DT_N_S_soc_S_i2c_40005800_P_sda_gpios_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_clock_frequency 400000
#define DT_N_S_soc_S_i2c_40005800_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_sq_size 4
#define DT_N_S_soc_S_i2c_40005800_P_sq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_cq_size 4
#define DT_N_S_soc_S_i2c_40005800_P_cq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_status "okay"
#define DT_N_S_soc_S_i2c_40005800_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_i2c_40005800_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_i2c_40005800_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_i2c_40005800_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_i2c_40005800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_i2c_40005800_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, status, 0)
#define DT_N_S_soc_S_i2c_40005800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, status, 0)
#define DT_N_S_soc_S_i2c_40005800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_status_LEN 1
#define DT_N_S_soc_S_i2c_40005800_P_status_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_compatible {"st,stm32-i2c-v1"}
#define DT_N_S_soc_S_i2c_40005800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_compatible_IDX_0 "st,stm32-i2c-v1"
#define DT_N_S_soc_S_i2c_40005800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-i2c-v1
#define DT_N_S_soc_S_i2c_40005800_P_compatible_IDX_0_STRING_TOKEN st_stm32_i2c_v1
#define DT_N_S_soc_S_i2c_40005800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_I2C_V1
#define DT_N_S_soc_S_i2c_40005800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, compatible, 0)
#define DT_N_S_soc_S_i2c_40005800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, compatible, 0)
#define DT_N_S_soc_S_i2c_40005800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_compatible_LEN 1
#define DT_N_S_soc_S_i2c_40005800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names {"event", "error"}
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_0 "event"
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_0_STRING_UNQUOTED event
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_0_STRING_TOKEN event
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN EVENT
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_1 "error"
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_1_STRING_UNQUOTED error
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_1_STRING_TOKEN error
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN ERROR
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 0) \
	fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 1)
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 1)
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_LEN 2
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_i2c_40005800_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_i2c_40005800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_clocks_IDX_0_VAL_bits 4194304
#define DT_N_S_soc_S_i2c_40005800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2c_40005800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_i2c_40005800, clocks, 0, bits)
#define DT_N_S_soc_S_i2c_40005800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005800, clocks, 0, bits)
#define DT_N_S_soc_S_i2c_40005800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_i2c_40005800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, clocks, 0)
#define DT_N_S_soc_S_i2c_40005800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, clocks, 0)
#define DT_N_S_soc_S_i2c_40005800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_clocks_LEN 1
#define DT_N_S_soc_S_i2c_40005800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_dma_coherent 0
#define DT_N_S_soc_S_i2c_40005800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_i2c_40005800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_wakeup_source 0
#define DT_N_S_soc_S_i2c_40005800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_i2c_40005800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /smbus2
 *
 * Node identifier: DT_N_S_smbus2
 *
 * Binding (compatible = st,stm32-smbus):
 *   $ZEPHYR_BASE\dts\bindings\smbus\st,stm32-smbus.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_smbus2_PATH "/smbus2"

/* Node's name with unit-address: */
#define DT_N_S_smbus2_FULL_NAME "smbus2"
#define DT_N_S_smbus2_FULL_NAME_UNQUOTED smbus2
#define DT_N_S_smbus2_FULL_NAME_TOKEN smbus2
#define DT_N_S_smbus2_FULL_NAME_UPPER_TOKEN SMBUS2

/* Node parent (/) identifier: */
#define DT_N_S_smbus2_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_smbus2_CHILD_IDX 13

/* Helpers for dealing with node labels: */
#define DT_N_S_smbus2_NODELABEL_NUM 1
#define DT_N_S_smbus2_FOREACH_NODELABEL(fn) fn(smbus2)
#define DT_N_S_smbus2_FOREACH_NODELABEL_VARGS(fn, ...) fn(smbus2, __VA_ARGS__)
#define DT_N_S_smbus2_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_smbus2_CHILD_NUM 0
#define DT_N_S_smbus2_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_smbus2_FOREACH_CHILD(fn) 
#define DT_N_S_smbus2_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_smbus2_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_smbus2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_smbus2_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_smbus2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_smbus2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_smbus2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_smbus2_HASH CeKsUeBLVHACPFrmleKnxYHTPUYQ02SrNC2w1a_Vmm4

/* Node's dependency ordinal: */
#define DT_N_S_smbus2_ORD 29
#define DT_N_S_smbus2_ORD_STR_SORTABLE 00029

/* Ordinals for what this node depends on directly: */
#define DT_N_S_smbus2_REQUIRES_ORDS \
	0, /* / */ \
	28, /* /soc/i2c@40005800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_smbus2_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_smbus2_IDX_0_C_TOKEN smbus2

/* Existence and alternate IDs: */
#define DT_N_S_smbus2_EXISTS 1
#define DT_N_INST_1_st_stm32_smbus DT_N_S_smbus2
#define DT_N_NODELABEL_smbus2      DT_N_S_smbus2

/* Macros for properties that are special in the specification: */
#define DT_N_S_smbus2_REG_NUM 0
#define DT_N_S_smbus2_FOREACH_REG(fn) 
#define DT_N_S_smbus2_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_smbus2_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_smbus2_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_smbus2_RANGES_NUM 0
#define DT_N_S_smbus2_FOREACH_RANGE(fn) 
#define DT_N_S_smbus2_IRQ_NUM 0
#define DT_N_S_smbus2_IRQ_LEVEL 0
#define DT_N_S_smbus2_COMPAT_MATCHES_st_stm32_smbus 1
#define DT_N_S_smbus2_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_smbus2_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_smbus2_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_smbus2_COMPAT_MODEL_IDX_0 "stm32-smbus"
#define DT_N_S_smbus2_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_smbus2_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_smbus2_P_i2c DT_N_S_soc_S_i2c_40005800
#define DT_N_S_smbus2_P_i2c_IDX_0 DT_N_S_soc_S_i2c_40005800
#define DT_N_S_smbus2_P_i2c_IDX_0_PH DT_N_S_soc_S_i2c_40005800
#define DT_N_S_smbus2_P_i2c_IDX_0_EXISTS 1
#define DT_N_S_smbus2_P_i2c_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus2, i2c, 0)
#define DT_N_S_smbus2_P_i2c_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus2, i2c, 0)
#define DT_N_S_smbus2_P_i2c_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus2, i2c, 0, __VA_ARGS__)
#define DT_N_S_smbus2_P_i2c_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus2, i2c, 0, __VA_ARGS__)
#define DT_N_S_smbus2_P_i2c_LEN 1
#define DT_N_S_smbus2_P_i2c_EXISTS 1
#define DT_N_S_smbus2_P_status "disabled"
#define DT_N_S_smbus2_P_status_STRING_UNQUOTED disabled
#define DT_N_S_smbus2_P_status_STRING_TOKEN disabled
#define DT_N_S_smbus2_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_smbus2_P_status_IDX_0 "disabled"
#define DT_N_S_smbus2_P_status_IDX_0_EXISTS 1
#define DT_N_S_smbus2_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_smbus2_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_smbus2_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_smbus2_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus2, status, 0)
#define DT_N_S_smbus2_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus2, status, 0)
#define DT_N_S_smbus2_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus2, status, 0, __VA_ARGS__)
#define DT_N_S_smbus2_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus2, status, 0, __VA_ARGS__)
#define DT_N_S_smbus2_P_status_LEN 1
#define DT_N_S_smbus2_P_status_EXISTS 1
#define DT_N_S_smbus2_P_compatible {"st,stm32-smbus"}
#define DT_N_S_smbus2_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_smbus2_P_compatible_IDX_0 "st,stm32-smbus"
#define DT_N_S_smbus2_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-smbus
#define DT_N_S_smbus2_P_compatible_IDX_0_STRING_TOKEN st_stm32_smbus
#define DT_N_S_smbus2_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SMBUS
#define DT_N_S_smbus2_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus2, compatible, 0)
#define DT_N_S_smbus2_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus2, compatible, 0)
#define DT_N_S_smbus2_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus2, compatible, 0, __VA_ARGS__)
#define DT_N_S_smbus2_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus2, compatible, 0, __VA_ARGS__)
#define DT_N_S_smbus2_P_compatible_LEN 1
#define DT_N_S_smbus2_P_compatible_EXISTS 1
#define DT_N_S_smbus2_P_dma_coherent 0
#define DT_N_S_smbus2_P_dma_coherent_EXISTS 1
#define DT_N_S_smbus2_P_zephyr_deferred_init 0
#define DT_N_S_smbus2_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_smbus2_P_wakeup_source 0
#define DT_N_S_smbus2_P_wakeup_source_EXISTS 1
#define DT_N_S_smbus2_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_smbus2_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/i2c@40005c00
 *
 * Node identifier: DT_N_S_soc_S_i2c_40005c00
 *
 * Binding (compatible = st,stm32-i2c-v1):
 *   $ZEPHYR_BASE\dts\bindings\i2c\st,stm32-i2c-v1.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_i2c_40005c00_PATH "/soc/i2c@40005c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_i2c_40005c00_FULL_NAME "i2c@40005c00"
#define DT_N_S_soc_S_i2c_40005c00_FULL_NAME_UNQUOTED i2c@40005c00
#define DT_N_S_soc_S_i2c_40005c00_FULL_NAME_TOKEN i2c_40005c00
#define DT_N_S_soc_S_i2c_40005c00_FULL_NAME_UPPER_TOKEN I2C_40005C00

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_i2c_40005c00_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_i2c_40005c00_CHILD_IDX 13

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_i2c_40005c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_i2c_40005c00_FOREACH_NODELABEL(fn) fn(i2c3)
#define DT_N_S_soc_S_i2c_40005c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c3, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_i2c_40005c00_CHILD_NUM 0
#define DT_N_S_soc_S_i2c_40005c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_i2c_40005c00_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_i2c_40005c00_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_40005c00_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_40005c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_i2c_40005c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_i2c_40005c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_40005c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_40005c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_i2c_40005c00_HASH 5fJFJ8Y_ydW7n0l4sdfawjHU6iH4mdEbeKnIUA_HHoc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_i2c_40005c00_ORD 30
#define DT_N_S_soc_S_i2c_40005c00_ORD_STR_SORTABLE 00030

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_i2c_40005c00_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_i2c_40005c00_SUPPORTS_ORDS \
	31, /* /smbus3 */
#define DT_N_NODELABEL_DT_N_S_soc_S_i2c_40005c00_IDX_0_C_TOKEN i2c3

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_i2c_40005c00_EXISTS 1
#define DT_N_INST_2_st_stm32_i2c_v1 DT_N_S_soc_S_i2c_40005c00
#define DT_N_NODELABEL_i2c3         DT_N_S_soc_S_i2c_40005c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_i2c_40005c00_REG_NUM 1
#define DT_N_S_soc_S_i2c_40005c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_REG_IDX_0_VAL_ADDRESS 1073765376 /* 0x40005c00 */
#define DT_N_S_soc_S_i2c_40005c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_i2c_40005c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_i2c_40005c00, 0)
#define DT_N_S_soc_S_i2c_40005c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005c00, 0)
#define DT_N_S_soc_S_i2c_40005c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005c00_RANGES_NUM 0
#define DT_N_S_soc_S_i2c_40005c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_i2c_40005c00_IRQ_NUM 2
#define DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_0_VAL_irq 72
#define DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_1_VAL_irq 73
#define DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_i2c_40005c00_IRQ_LEVEL 1
#define DT_N_S_soc_S_i2c_40005c00_IRQ_NAME_event_VAL_irq DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_i2c_40005c00_IRQ_NAME_event_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_IRQ_NAME_event_VAL_priority DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_i2c_40005c00_IRQ_NAME_event_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_IRQ_NAME_event_CONTROLLER DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_i2c_40005c00_IRQ_NAME_error_VAL_irq DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_1_VAL_irq
#define DT_N_S_soc_S_i2c_40005c00_IRQ_NAME_error_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_IRQ_NAME_error_VAL_priority DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_1_VAL_priority
#define DT_N_S_soc_S_i2c_40005c00_IRQ_NAME_error_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_IRQ_NAME_error_CONTROLLER DT_N_S_soc_S_i2c_40005c00_IRQ_IDX_1_CONTROLLER
#define DT_N_S_soc_S_i2c_40005c00_COMPAT_MATCHES_st_stm32_i2c_v1 1
#define DT_N_S_soc_S_i2c_40005c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_i2c_40005c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_COMPAT_MODEL_IDX_0 "stm32-i2c-v1"
#define DT_N_S_soc_S_i2c_40005c00_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_i2c_40005c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_i2c_40005c00_P_reg {1073765376 /* 0x40005c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_i2c_40005c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_reg_IDX_0 1073765376
#define DT_N_S_soc_S_i2c_40005c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_i2c_40005c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_interrupts {72 /* 0x48 */, 0 /* 0x0 */, 73 /* 0x49 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_0 72
#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_2 73
#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_clock_frequency 100000
#define DT_N_S_soc_S_i2c_40005c00_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_sq_size 4
#define DT_N_S_soc_S_i2c_40005c00_P_sq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_cq_size 4
#define DT_N_S_soc_S_i2c_40005c00_P_cq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_status "disabled"
#define DT_N_S_soc_S_i2c_40005c00_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_i2c_40005c00_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_i2c_40005c00_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_i2c_40005c00_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_i2c_40005c00_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_i2c_40005c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005c00, status, 0)
#define DT_N_S_soc_S_i2c_40005c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005c00, status, 0)
#define DT_N_S_soc_S_i2c_40005c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005c00_P_status_LEN 1
#define DT_N_S_soc_S_i2c_40005c00_P_status_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_compatible {"st,stm32-i2c-v1"}
#define DT_N_S_soc_S_i2c_40005c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_compatible_IDX_0 "st,stm32-i2c-v1"
#define DT_N_S_soc_S_i2c_40005c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-i2c-v1
#define DT_N_S_soc_S_i2c_40005c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_i2c_v1
#define DT_N_S_soc_S_i2c_40005c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_I2C_V1
#define DT_N_S_soc_S_i2c_40005c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005c00, compatible, 0)
#define DT_N_S_soc_S_i2c_40005c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005c00, compatible, 0)
#define DT_N_S_soc_S_i2c_40005c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005c00_P_compatible_LEN 1
#define DT_N_S_soc_S_i2c_40005c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names {"event", "error"}
#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_0 "event"
#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_0_STRING_UNQUOTED event
#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_0_STRING_TOKEN event
#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN EVENT
#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_1 "error"
#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_1_STRING_UNQUOTED error
#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_1_STRING_TOKEN error
#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN ERROR
#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005c00, interrupt_names, 0) \
	fn(DT_N_S_soc_S_i2c_40005c00, interrupt_names, 1)
#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005c00, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005c00, interrupt_names, 1)
#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005c00, interrupt_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2c_40005c00, interrupt_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005c00, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005c00, interrupt_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_LEN 2
#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_i2c_40005c00_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_i2c_40005c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_clocks_IDX_0_VAL_bits 8388608
#define DT_N_S_soc_S_i2c_40005c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2c_40005c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_i2c_40005c00, clocks, 0, bits)
#define DT_N_S_soc_S_i2c_40005c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005c00, clocks, 0, bits)
#define DT_N_S_soc_S_i2c_40005c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_i2c_40005c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005c00, clocks, 0)
#define DT_N_S_soc_S_i2c_40005c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005c00, clocks, 0)
#define DT_N_S_soc_S_i2c_40005c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005c00_P_clocks_LEN 1
#define DT_N_S_soc_S_i2c_40005c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_dma_coherent 0
#define DT_N_S_soc_S_i2c_40005c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_i2c_40005c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_wakeup_source 0
#define DT_N_S_soc_S_i2c_40005c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_i2c_40005c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_i2c_40005c00_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /smbus3
 *
 * Node identifier: DT_N_S_smbus3
 *
 * Binding (compatible = st,stm32-smbus):
 *   $ZEPHYR_BASE\dts\bindings\smbus\st,stm32-smbus.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_smbus3_PATH "/smbus3"

/* Node's name with unit-address: */
#define DT_N_S_smbus3_FULL_NAME "smbus3"
#define DT_N_S_smbus3_FULL_NAME_UNQUOTED smbus3
#define DT_N_S_smbus3_FULL_NAME_TOKEN smbus3
#define DT_N_S_smbus3_FULL_NAME_UPPER_TOKEN SMBUS3

/* Node parent (/) identifier: */
#define DT_N_S_smbus3_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_smbus3_CHILD_IDX 14

/* Helpers for dealing with node labels: */
#define DT_N_S_smbus3_NODELABEL_NUM 1
#define DT_N_S_smbus3_FOREACH_NODELABEL(fn) fn(smbus3)
#define DT_N_S_smbus3_FOREACH_NODELABEL_VARGS(fn, ...) fn(smbus3, __VA_ARGS__)
#define DT_N_S_smbus3_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_smbus3_CHILD_NUM 0
#define DT_N_S_smbus3_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_smbus3_FOREACH_CHILD(fn) 
#define DT_N_S_smbus3_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_smbus3_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_smbus3_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_smbus3_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_smbus3_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_smbus3_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_smbus3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_smbus3_HASH ZeVI1g__orT_bhXDEMbeNx9PIwW74xB8lEqisMROKVc

/* Node's dependency ordinal: */
#define DT_N_S_smbus3_ORD 31
#define DT_N_S_smbus3_ORD_STR_SORTABLE 00031

/* Ordinals for what this node depends on directly: */
#define DT_N_S_smbus3_REQUIRES_ORDS \
	0, /* / */ \
	30, /* /soc/i2c@40005c00 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_smbus3_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_smbus3_IDX_0_C_TOKEN smbus3

/* Existence and alternate IDs: */
#define DT_N_S_smbus3_EXISTS 1
#define DT_N_INST_2_st_stm32_smbus DT_N_S_smbus3
#define DT_N_NODELABEL_smbus3      DT_N_S_smbus3

/* Macros for properties that are special in the specification: */
#define DT_N_S_smbus3_REG_NUM 0
#define DT_N_S_smbus3_FOREACH_REG(fn) 
#define DT_N_S_smbus3_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_smbus3_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_smbus3_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_smbus3_RANGES_NUM 0
#define DT_N_S_smbus3_FOREACH_RANGE(fn) 
#define DT_N_S_smbus3_IRQ_NUM 0
#define DT_N_S_smbus3_IRQ_LEVEL 0
#define DT_N_S_smbus3_COMPAT_MATCHES_st_stm32_smbus 1
#define DT_N_S_smbus3_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_smbus3_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_smbus3_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_smbus3_COMPAT_MODEL_IDX_0 "stm32-smbus"
#define DT_N_S_smbus3_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_smbus3_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_smbus3_P_i2c DT_N_S_soc_S_i2c_40005c00
#define DT_N_S_smbus3_P_i2c_IDX_0 DT_N_S_soc_S_i2c_40005c00
#define DT_N_S_smbus3_P_i2c_IDX_0_PH DT_N_S_soc_S_i2c_40005c00
#define DT_N_S_smbus3_P_i2c_IDX_0_EXISTS 1
#define DT_N_S_smbus3_P_i2c_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus3, i2c, 0)
#define DT_N_S_smbus3_P_i2c_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus3, i2c, 0)
#define DT_N_S_smbus3_P_i2c_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus3, i2c, 0, __VA_ARGS__)
#define DT_N_S_smbus3_P_i2c_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus3, i2c, 0, __VA_ARGS__)
#define DT_N_S_smbus3_P_i2c_LEN 1
#define DT_N_S_smbus3_P_i2c_EXISTS 1
#define DT_N_S_smbus3_P_status "disabled"
#define DT_N_S_smbus3_P_status_STRING_UNQUOTED disabled
#define DT_N_S_smbus3_P_status_STRING_TOKEN disabled
#define DT_N_S_smbus3_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_smbus3_P_status_IDX_0 "disabled"
#define DT_N_S_smbus3_P_status_IDX_0_EXISTS 1
#define DT_N_S_smbus3_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_smbus3_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_smbus3_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_smbus3_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus3, status, 0)
#define DT_N_S_smbus3_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus3, status, 0)
#define DT_N_S_smbus3_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus3, status, 0, __VA_ARGS__)
#define DT_N_S_smbus3_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus3, status, 0, __VA_ARGS__)
#define DT_N_S_smbus3_P_status_LEN 1
#define DT_N_S_smbus3_P_status_EXISTS 1
#define DT_N_S_smbus3_P_compatible {"st,stm32-smbus"}
#define DT_N_S_smbus3_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_smbus3_P_compatible_IDX_0 "st,stm32-smbus"
#define DT_N_S_smbus3_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-smbus
#define DT_N_S_smbus3_P_compatible_IDX_0_STRING_TOKEN st_stm32_smbus
#define DT_N_S_smbus3_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SMBUS
#define DT_N_S_smbus3_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus3, compatible, 0)
#define DT_N_S_smbus3_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus3, compatible, 0)
#define DT_N_S_smbus3_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus3, compatible, 0, __VA_ARGS__)
#define DT_N_S_smbus3_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus3, compatible, 0, __VA_ARGS__)
#define DT_N_S_smbus3_P_compatible_LEN 1
#define DT_N_S_smbus3_P_compatible_EXISTS 1
#define DT_N_S_smbus3_P_dma_coherent 0
#define DT_N_S_smbus3_P_dma_coherent_EXISTS 1
#define DT_N_S_smbus3_P_zephyr_deferred_init 0
#define DT_N_S_smbus3_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_smbus3_P_wakeup_source 0
#define DT_N_S_smbus3_P_wakeup_source_EXISTS 1
#define DT_N_S_smbus3_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_smbus3_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /vbat
 *
 * Node identifier: DT_N_S_vbat
 *
 * Binding (compatible = st,stm32-vbat):
 *   $ZEPHYR_BASE\dts\bindings\sensor\st,stm32-vbat.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_vbat_PATH "/vbat"

/* Node's name with unit-address: */
#define DT_N_S_vbat_FULL_NAME "vbat"
#define DT_N_S_vbat_FULL_NAME_UNQUOTED vbat
#define DT_N_S_vbat_FULL_NAME_TOKEN vbat
#define DT_N_S_vbat_FULL_NAME_UPPER_TOKEN VBAT

/* Node parent (/) identifier: */
#define DT_N_S_vbat_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_vbat_CHILD_IDX 10

/* Helpers for dealing with node labels: */
#define DT_N_S_vbat_NODELABEL_NUM 1
#define DT_N_S_vbat_FOREACH_NODELABEL(fn) fn(vbat)
#define DT_N_S_vbat_FOREACH_NODELABEL_VARGS(fn, ...) fn(vbat, __VA_ARGS__)
#define DT_N_S_vbat_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_vbat_CHILD_NUM 0
#define DT_N_S_vbat_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_vbat_FOREACH_CHILD(fn) 
#define DT_N_S_vbat_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_vbat_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_vbat_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_vbat_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_vbat_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_vbat_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_vbat_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_vbat_HASH 6jTjjWCiokAcWwHDg9DIiUBaK7_R_tkCJ6unpENFBIY

/* Node's dependency ordinal: */
#define DT_N_S_vbat_ORD 32
#define DT_N_S_vbat_ORD_STR_SORTABLE 00032

/* Ordinals for what this node depends on directly: */
#define DT_N_S_vbat_REQUIRES_ORDS \
	0, /* / */ \
	12, /* /soc/adc@40012000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_vbat_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_vbat_IDX_0_C_TOKEN vbat

/* Existence and alternate IDs: */
#define DT_N_S_vbat_EXISTS 1
#define DT_N_ALIAS_volt_sensor1   DT_N_S_vbat
#define DT_N_INST_0_st_stm32_vbat DT_N_S_vbat
#define DT_N_NODELABEL_vbat       DT_N_S_vbat

/* Macros for properties that are special in the specification: */
#define DT_N_S_vbat_REG_NUM 0
#define DT_N_S_vbat_FOREACH_REG(fn) 
#define DT_N_S_vbat_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_vbat_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_vbat_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_vbat_RANGES_NUM 0
#define DT_N_S_vbat_FOREACH_RANGE(fn) 
#define DT_N_S_vbat_IRQ_NUM 0
#define DT_N_S_vbat_IRQ_LEVEL 0
#define DT_N_S_vbat_COMPAT_MATCHES_st_stm32_vbat 1
#define DT_N_S_vbat_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_vbat_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_vbat_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_vbat_COMPAT_MODEL_IDX_0 "stm32-vbat"
#define DT_N_S_vbat_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_vbat_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_vbat_P_io_channels_IDX_0_EXISTS 1
#define DT_N_S_vbat_P_io_channels_IDX_0_PH DT_N_S_soc_S_adc_40012000
#define DT_N_S_vbat_P_io_channels_IDX_0_VAL_input 18
#define DT_N_S_vbat_P_io_channels_IDX_0_VAL_input_EXISTS 1
#define DT_N_S_vbat_P_io_channels_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_vbat, io_channels, 0, input)
#define DT_N_S_vbat_P_io_channels_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_vbat, io_channels, 0, input)
#define DT_N_S_vbat_P_io_channels_IDX_0_NUM_CELLS 1
#define DT_N_S_vbat_P_io_channels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vbat, io_channels, 0)
#define DT_N_S_vbat_P_io_channels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vbat, io_channels, 0)
#define DT_N_S_vbat_P_io_channels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vbat, io_channels, 0, __VA_ARGS__)
#define DT_N_S_vbat_P_io_channels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_vbat, io_channels, 0, __VA_ARGS__)
#define DT_N_S_vbat_P_io_channels_LEN 1
#define DT_N_S_vbat_P_io_channels_EXISTS 1
#define DT_N_S_vbat_P_ratio 4
#define DT_N_S_vbat_P_ratio_EXISTS 1
#define DT_N_S_vbat_P_status "okay"
#define DT_N_S_vbat_P_status_STRING_UNQUOTED okay
#define DT_N_S_vbat_P_status_STRING_TOKEN okay
#define DT_N_S_vbat_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_vbat_P_status_IDX_0 "okay"
#define DT_N_S_vbat_P_status_IDX_0_EXISTS 1
#define DT_N_S_vbat_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_vbat_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_vbat_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_vbat_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vbat, status, 0)
#define DT_N_S_vbat_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vbat, status, 0)
#define DT_N_S_vbat_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vbat, status, 0, __VA_ARGS__)
#define DT_N_S_vbat_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_vbat, status, 0, __VA_ARGS__)
#define DT_N_S_vbat_P_status_LEN 1
#define DT_N_S_vbat_P_status_EXISTS 1
#define DT_N_S_vbat_P_compatible {"st,stm32-vbat"}
#define DT_N_S_vbat_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_vbat_P_compatible_IDX_0 "st,stm32-vbat"
#define DT_N_S_vbat_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-vbat
#define DT_N_S_vbat_P_compatible_IDX_0_STRING_TOKEN st_stm32_vbat
#define DT_N_S_vbat_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_VBAT
#define DT_N_S_vbat_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vbat, compatible, 0)
#define DT_N_S_vbat_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vbat, compatible, 0)
#define DT_N_S_vbat_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vbat, compatible, 0, __VA_ARGS__)
#define DT_N_S_vbat_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_vbat, compatible, 0, __VA_ARGS__)
#define DT_N_S_vbat_P_compatible_LEN 1
#define DT_N_S_vbat_P_compatible_EXISTS 1
#define DT_N_S_vbat_P_dma_coherent 0
#define DT_N_S_vbat_P_dma_coherent_EXISTS 1
#define DT_N_S_vbat_P_zephyr_deferred_init 0
#define DT_N_S_vbat_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_vbat_P_wakeup_source 0
#define DT_N_S_vbat_P_wakeup_source_EXISTS 1
#define DT_N_S_vbat_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_vbat_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout/vrefint@2a
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_PATH "/soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout/vrefint@2a"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FULL_NAME "vrefint@2a"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FULL_NAME_UNQUOTED vrefint@2a
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FULL_NAME_TOKEN vrefint_2a
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FULL_NAME_UPPER_TOKEN VREFINT_2A

/* Node parent (/soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout) identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_PARENT DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FOREACH_NODELABEL(fn) fn(vrefint_otp)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FOREACH_NODELABEL_VARGS(fn, ...) fn(vrefint_otp, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00) fn(DT_N_S_soc_S_flash_controller_40023c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_HASH ag6ThkK1wVTjTqOqe66IaXt_HpjldR_ukL6za2gTYHQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_ORD 33
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_ORD_STR_SORTABLE 00033

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_REQUIRES_ORDS \
	15, /* /soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_SUPPORTS_ORDS \
	34, /* /vref */
#define DT_N_NODELABEL_DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_IDX_0_C_TOKEN vrefint_otp

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_EXISTS 1
#define DT_N_NODELABEL_vrefint_otp DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_REG_IDX_0_VAL_ADDRESS 42 /* 0x2a */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_REG_IDX_0_VAL_SIZE 2 /* 0x2 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_P_reg {42 /* 0x2a */, 2 /* 0x2 */}
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_P_reg_IDX_0 42
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_P_reg_IDX_1 2
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_P_read_only 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a_P_read_only_EXISTS 1

/*
 * Devicetree node: /vref
 *
 * Node identifier: DT_N_S_vref
 *
 * Binding (compatible = st,stm32-vref):
 *   $ZEPHYR_BASE\dts\bindings\sensor\st,stm32-vref.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_vref_PATH "/vref"

/* Node's name with unit-address: */
#define DT_N_S_vref_FULL_NAME "vref"
#define DT_N_S_vref_FULL_NAME_UNQUOTED vref
#define DT_N_S_vref_FULL_NAME_TOKEN vref
#define DT_N_S_vref_FULL_NAME_UPPER_TOKEN VREF

/* Node parent (/) identifier: */
#define DT_N_S_vref_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_vref_CHILD_IDX 9

/* Helpers for dealing with node labels: */
#define DT_N_S_vref_NODELABEL_NUM 1
#define DT_N_S_vref_FOREACH_NODELABEL(fn) fn(vref)
#define DT_N_S_vref_FOREACH_NODELABEL_VARGS(fn, ...) fn(vref, __VA_ARGS__)
#define DT_N_S_vref_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_vref_CHILD_NUM 0
#define DT_N_S_vref_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_vref_FOREACH_CHILD(fn) 
#define DT_N_S_vref_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_vref_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_vref_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_vref_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_vref_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_vref_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_vref_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_vref_HASH _KQ_hQT8vlL_HGgSo8B0PN_M_dmG5lMZ2C1aGmWYFog

/* Node's dependency ordinal: */
#define DT_N_S_vref_ORD 34
#define DT_N_S_vref_ORD_STR_SORTABLE 00034

/* Ordinals for what this node depends on directly: */
#define DT_N_S_vref_REQUIRES_ORDS \
	0, /* / */ \
	12, /* /soc/adc@40012000 */ \
	33, /* /soc/flash-controller@40023c00/flash@1fff7a00/nvmem-layout/vrefint@2a */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_vref_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_vref_IDX_0_C_TOKEN vref

/* Existence and alternate IDs: */
#define DT_N_S_vref_EXISTS 1
#define DT_N_ALIAS_volt_sensor0   DT_N_S_vref
#define DT_N_INST_0_st_stm32_vref DT_N_S_vref
#define DT_N_NODELABEL_vref       DT_N_S_vref

/* Macros for properties that are special in the specification: */
#define DT_N_S_vref_REG_NUM 0
#define DT_N_S_vref_FOREACH_REG(fn) 
#define DT_N_S_vref_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_vref_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_vref_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_vref_RANGES_NUM 0
#define DT_N_S_vref_FOREACH_RANGE(fn) 
#define DT_N_S_vref_IRQ_NUM 0
#define DT_N_S_vref_IRQ_LEVEL 0
#define DT_N_S_vref_COMPAT_MATCHES_st_stm32_vref 1
#define DT_N_S_vref_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_vref_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_vref_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_vref_COMPAT_MODEL_IDX_0 "stm32-vref"
#define DT_N_S_vref_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_vref_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_vref_P_nvmem_cells_IDX_0_EXISTS 1
#define DT_N_S_vref_P_nvmem_cells_IDX_0_PH DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a
#define DT_N_S_vref_P_nvmem_cells_IDX_0_FOREACH_CELL(fn) 
#define DT_N_S_vref_P_nvmem_cells_IDX_0_FOREACH_CELL_SEP(fn, sep) 
#define DT_N_S_vref_P_nvmem_cells_IDX_0_NUM_CELLS 0
#define DT_N_S_vref_P_nvmem_cells_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vref, nvmem_cells, 0)
#define DT_N_S_vref_P_nvmem_cells_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vref, nvmem_cells, 0)
#define DT_N_S_vref_P_nvmem_cells_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vref, nvmem_cells, 0, __VA_ARGS__)
#define DT_N_S_vref_P_nvmem_cells_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_vref, nvmem_cells, 0, __VA_ARGS__)
#define DT_N_S_vref_P_nvmem_cells_LEN 1
#define DT_N_S_vref_P_nvmem_cells_EXISTS 1
#define DT_N_S_vref_P_vrefint_cal_mv 3300
#define DT_N_S_vref_P_vrefint_cal_mv_EXISTS 1
#define DT_N_S_vref_P_vrefint_cal_resolution 12
#define DT_N_S_vref_P_vrefint_cal_resolution_IDX_0_ENUM_IDX 0
#define DT_N_S_vref_P_vrefint_cal_resolution_IDX_0_EXISTS 1
#define DT_N_S_vref_P_vrefint_cal_resolution_IDX_0_ENUM_VAL_12_EXISTS 1
#define DT_N_S_vref_P_vrefint_cal_resolution_ENUM_VAL_12_EXISTS 1
#define DT_N_S_vref_P_vrefint_cal_resolution_EXISTS 1
#define DT_N_S_vref_P_status "okay"
#define DT_N_S_vref_P_status_STRING_UNQUOTED okay
#define DT_N_S_vref_P_status_STRING_TOKEN okay
#define DT_N_S_vref_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_vref_P_status_IDX_0 "okay"
#define DT_N_S_vref_P_status_IDX_0_EXISTS 1
#define DT_N_S_vref_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_vref_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_vref_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_vref_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vref, status, 0)
#define DT_N_S_vref_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vref, status, 0)
#define DT_N_S_vref_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vref, status, 0, __VA_ARGS__)
#define DT_N_S_vref_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_vref, status, 0, __VA_ARGS__)
#define DT_N_S_vref_P_status_LEN 1
#define DT_N_S_vref_P_status_EXISTS 1
#define DT_N_S_vref_P_compatible {"st,stm32-vref"}
#define DT_N_S_vref_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_vref_P_compatible_IDX_0 "st,stm32-vref"
#define DT_N_S_vref_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-vref
#define DT_N_S_vref_P_compatible_IDX_0_STRING_TOKEN st_stm32_vref
#define DT_N_S_vref_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_VREF
#define DT_N_S_vref_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vref, compatible, 0)
#define DT_N_S_vref_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vref, compatible, 0)
#define DT_N_S_vref_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vref, compatible, 0, __VA_ARGS__)
#define DT_N_S_vref_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_vref, compatible, 0, __VA_ARGS__)
#define DT_N_S_vref_P_compatible_LEN 1
#define DT_N_S_vref_P_compatible_EXISTS 1
#define DT_N_S_vref_P_dma_coherent 0
#define DT_N_S_vref_P_dma_coherent_EXISTS 1
#define DT_N_S_vref_P_io_channels_IDX_0_EXISTS 1
#define DT_N_S_vref_P_io_channels_IDX_0_PH DT_N_S_soc_S_adc_40012000
#define DT_N_S_vref_P_io_channels_IDX_0_VAL_input 17
#define DT_N_S_vref_P_io_channels_IDX_0_VAL_input_EXISTS 1
#define DT_N_S_vref_P_io_channels_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_vref, io_channels, 0, input)
#define DT_N_S_vref_P_io_channels_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_vref, io_channels, 0, input)
#define DT_N_S_vref_P_io_channels_IDX_0_NUM_CELLS 1
#define DT_N_S_vref_P_io_channels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vref, io_channels, 0)
#define DT_N_S_vref_P_io_channels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vref, io_channels, 0)
#define DT_N_S_vref_P_io_channels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vref, io_channels, 0, __VA_ARGS__)
#define DT_N_S_vref_P_io_channels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_vref, io_channels, 0, __VA_ARGS__)
#define DT_N_S_vref_P_io_channels_LEN 1
#define DT_N_S_vref_P_io_channels_EXISTS 1
#define DT_N_S_vref_P_zephyr_deferred_init 0
#define DT_N_S_vref_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_vref_P_wakeup_source 0
#define DT_N_S_vref_P_wakeup_source_EXISTS 1
#define DT_N_S_vref_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_vref_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /clocks/clk-hsi
 *
 * Node identifier: DT_N_S_clocks_S_clk_hsi
 *
 * Binding (compatible = fixed-clock):
 *   $ZEPHYR_BASE\dts\bindings\clock\fixed-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_clocks_S_clk_hsi_PATH "/clocks/clk-hsi"

/* Node's name with unit-address: */
#define DT_N_S_clocks_S_clk_hsi_FULL_NAME "clk-hsi"
#define DT_N_S_clocks_S_clk_hsi_FULL_NAME_UNQUOTED clk-hsi
#define DT_N_S_clocks_S_clk_hsi_FULL_NAME_TOKEN clk_hsi
#define DT_N_S_clocks_S_clk_hsi_FULL_NAME_UPPER_TOKEN CLK_HSI

/* Node parent (/clocks) identifier: */
#define DT_N_S_clocks_S_clk_hsi_PARENT DT_N_S_clocks

/* Node's index in its parent's list of children: */
#define DT_N_S_clocks_S_clk_hsi_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_clocks_S_clk_hsi_NODELABEL_NUM 1
#define DT_N_S_clocks_S_clk_hsi_FOREACH_NODELABEL(fn) fn(clk_hsi)
#define DT_N_S_clocks_S_clk_hsi_FOREACH_NODELABEL_VARGS(fn, ...) fn(clk_hsi, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hsi_FOREACH_ANCESTOR(fn) fn(DT_N_S_clocks) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_clocks_S_clk_hsi_CHILD_NUM 0
#define DT_N_S_clocks_S_clk_hsi_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_clocks_S_clk_hsi_FOREACH_CHILD(fn) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_clocks_S_clk_hsi_HASH kE6dGnI__HuixEc_o2mPIojHDSoRqqYmExJJycW6WDM

/* Node's dependency ordinal: */
#define DT_N_S_clocks_S_clk_hsi_ORD 35
#define DT_N_S_clocks_S_clk_hsi_ORD_STR_SORTABLE 00035

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clocks_S_clk_hsi_REQUIRES_ORDS \
	6, /* /clocks */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clocks_S_clk_hsi_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_clocks_S_clk_hsi_IDX_0_C_TOKEN clk_hsi

/* Existence and alternate IDs: */
#define DT_N_S_clocks_S_clk_hsi_EXISTS 1
#define DT_N_INST_1_fixed_clock DT_N_S_clocks_S_clk_hsi
#define DT_N_NODELABEL_clk_hsi  DT_N_S_clocks_S_clk_hsi

/* Macros for properties that are special in the specification: */
#define DT_N_S_clocks_S_clk_hsi_REG_NUM 0
#define DT_N_S_clocks_S_clk_hsi_FOREACH_REG(fn) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_clk_hsi_RANGES_NUM 0
#define DT_N_S_clocks_S_clk_hsi_FOREACH_RANGE(fn) 
#define DT_N_S_clocks_S_clk_hsi_IRQ_NUM 0
#define DT_N_S_clocks_S_clk_hsi_IRQ_LEVEL 0
#define DT_N_S_clocks_S_clk_hsi_COMPAT_MATCHES_fixed_clock 1
#define DT_N_S_clocks_S_clk_hsi_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clocks_S_clk_hsi_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_clocks_S_clk_hsi_P_clock_frequency 16000000
#define DT_N_S_clocks_S_clk_hsi_P_clock_frequency_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_status "disabled"
#define DT_N_S_clocks_S_clk_hsi_P_status_STRING_UNQUOTED disabled
#define DT_N_S_clocks_S_clk_hsi_P_status_STRING_TOKEN disabled
#define DT_N_S_clocks_S_clk_hsi_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_clocks_S_clk_hsi_P_status_IDX_0 "disabled"
#define DT_N_S_clocks_S_clk_hsi_P_status_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_clocks_S_clk_hsi_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_hsi, status, 0)
#define DT_N_S_clocks_S_clk_hsi_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hsi, status, 0)
#define DT_N_S_clocks_S_clk_hsi_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hsi, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hsi_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hsi, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hsi_P_status_LEN 1
#define DT_N_S_clocks_S_clk_hsi_P_status_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_compatible {"fixed-clock"}
#define DT_N_S_clocks_S_clk_hsi_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_compatible_IDX_0 "fixed-clock"
#define DT_N_S_clocks_S_clk_hsi_P_compatible_IDX_0_STRING_UNQUOTED fixed-clock
#define DT_N_S_clocks_S_clk_hsi_P_compatible_IDX_0_STRING_TOKEN fixed_clock
#define DT_N_S_clocks_S_clk_hsi_P_compatible_IDX_0_STRING_UPPER_TOKEN FIXED_CLOCK
#define DT_N_S_clocks_S_clk_hsi_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_hsi, compatible, 0)
#define DT_N_S_clocks_S_clk_hsi_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hsi, compatible, 0)
#define DT_N_S_clocks_S_clk_hsi_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hsi, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hsi_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hsi, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hsi_P_compatible_LEN 1
#define DT_N_S_clocks_S_clk_hsi_P_compatible_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_dma_coherent 0
#define DT_N_S_clocks_S_clk_hsi_P_dma_coherent_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_zephyr_deferred_init 0
#define DT_N_S_clocks_S_clk_hsi_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_wakeup_source 0
#define DT_N_S_clocks_S_clk_hsi_P_wakeup_source_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_clocks_S_clk_hsi_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /clocks/clk-lse
 *
 * Node identifier: DT_N_S_clocks_S_clk_lse
 *
 * Binding (compatible = fixed-clock):
 *   $ZEPHYR_BASE\dts\bindings\clock\fixed-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_clocks_S_clk_lse_PATH "/clocks/clk-lse"

/* Node's name with unit-address: */
#define DT_N_S_clocks_S_clk_lse_FULL_NAME "clk-lse"
#define DT_N_S_clocks_S_clk_lse_FULL_NAME_UNQUOTED clk-lse
#define DT_N_S_clocks_S_clk_lse_FULL_NAME_TOKEN clk_lse
#define DT_N_S_clocks_S_clk_lse_FULL_NAME_UPPER_TOKEN CLK_LSE

/* Node parent (/clocks) identifier: */
#define DT_N_S_clocks_S_clk_lse_PARENT DT_N_S_clocks

/* Node's index in its parent's list of children: */
#define DT_N_S_clocks_S_clk_lse_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_clocks_S_clk_lse_NODELABEL_NUM 1
#define DT_N_S_clocks_S_clk_lse_FOREACH_NODELABEL(fn) fn(clk_lse)
#define DT_N_S_clocks_S_clk_lse_FOREACH_NODELABEL_VARGS(fn, ...) fn(clk_lse, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lse_FOREACH_ANCESTOR(fn) fn(DT_N_S_clocks) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_clocks_S_clk_lse_CHILD_NUM 0
#define DT_N_S_clocks_S_clk_lse_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_clocks_S_clk_lse_FOREACH_CHILD(fn) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_clocks_S_clk_lse_HASH RRqOX2XdydrKvwOwHO0Kh3mPfPtUsDJrDySCwF316Ek

/* Node's dependency ordinal: */
#define DT_N_S_clocks_S_clk_lse_ORD 36
#define DT_N_S_clocks_S_clk_lse_ORD_STR_SORTABLE 00036

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clocks_S_clk_lse_REQUIRES_ORDS \
	6, /* /clocks */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clocks_S_clk_lse_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_clocks_S_clk_lse_IDX_0_C_TOKEN clk_lse

/* Existence and alternate IDs: */
#define DT_N_S_clocks_S_clk_lse_EXISTS 1
#define DT_N_INST_2_fixed_clock DT_N_S_clocks_S_clk_lse
#define DT_N_NODELABEL_clk_lse  DT_N_S_clocks_S_clk_lse

/* Macros for properties that are special in the specification: */
#define DT_N_S_clocks_S_clk_lse_REG_NUM 0
#define DT_N_S_clocks_S_clk_lse_FOREACH_REG(fn) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_clk_lse_RANGES_NUM 0
#define DT_N_S_clocks_S_clk_lse_FOREACH_RANGE(fn) 
#define DT_N_S_clocks_S_clk_lse_IRQ_NUM 0
#define DT_N_S_clocks_S_clk_lse_IRQ_LEVEL 0
#define DT_N_S_clocks_S_clk_lse_COMPAT_MATCHES_fixed_clock 1
#define DT_N_S_clocks_S_clk_lse_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clocks_S_clk_lse_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_clocks_S_clk_lse_P_clock_frequency 32768
#define DT_N_S_clocks_S_clk_lse_P_clock_frequency_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_status "disabled"
#define DT_N_S_clocks_S_clk_lse_P_status_STRING_UNQUOTED disabled
#define DT_N_S_clocks_S_clk_lse_P_status_STRING_TOKEN disabled
#define DT_N_S_clocks_S_clk_lse_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_clocks_S_clk_lse_P_status_IDX_0 "disabled"
#define DT_N_S_clocks_S_clk_lse_P_status_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_clocks_S_clk_lse_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_lse, status, 0)
#define DT_N_S_clocks_S_clk_lse_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_lse, status, 0)
#define DT_N_S_clocks_S_clk_lse_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_lse, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lse_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_lse, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lse_P_status_LEN 1
#define DT_N_S_clocks_S_clk_lse_P_status_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_compatible {"fixed-clock"}
#define DT_N_S_clocks_S_clk_lse_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_compatible_IDX_0 "fixed-clock"
#define DT_N_S_clocks_S_clk_lse_P_compatible_IDX_0_STRING_UNQUOTED fixed-clock
#define DT_N_S_clocks_S_clk_lse_P_compatible_IDX_0_STRING_TOKEN fixed_clock
#define DT_N_S_clocks_S_clk_lse_P_compatible_IDX_0_STRING_UPPER_TOKEN FIXED_CLOCK
#define DT_N_S_clocks_S_clk_lse_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_lse, compatible, 0)
#define DT_N_S_clocks_S_clk_lse_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_lse, compatible, 0)
#define DT_N_S_clocks_S_clk_lse_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_lse, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lse_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_lse, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lse_P_compatible_LEN 1
#define DT_N_S_clocks_S_clk_lse_P_compatible_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_dma_coherent 0
#define DT_N_S_clocks_S_clk_lse_P_dma_coherent_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_zephyr_deferred_init 0
#define DT_N_S_clocks_S_clk_lse_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_wakeup_source 0
#define DT_N_S_clocks_S_clk_lse_P_wakeup_source_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_clocks_S_clk_lse_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /clocks/clk-lsi
 *
 * Node identifier: DT_N_S_clocks_S_clk_lsi
 *
 * Binding (compatible = fixed-clock):
 *   $ZEPHYR_BASE\dts\bindings\clock\fixed-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_clocks_S_clk_lsi_PATH "/clocks/clk-lsi"

/* Node's name with unit-address: */
#define DT_N_S_clocks_S_clk_lsi_FULL_NAME "clk-lsi"
#define DT_N_S_clocks_S_clk_lsi_FULL_NAME_UNQUOTED clk-lsi
#define DT_N_S_clocks_S_clk_lsi_FULL_NAME_TOKEN clk_lsi
#define DT_N_S_clocks_S_clk_lsi_FULL_NAME_UPPER_TOKEN CLK_LSI

/* Node parent (/clocks) identifier: */
#define DT_N_S_clocks_S_clk_lsi_PARENT DT_N_S_clocks

/* Node's index in its parent's list of children: */
#define DT_N_S_clocks_S_clk_lsi_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_clocks_S_clk_lsi_NODELABEL_NUM 1
#define DT_N_S_clocks_S_clk_lsi_FOREACH_NODELABEL(fn) fn(clk_lsi)
#define DT_N_S_clocks_S_clk_lsi_FOREACH_NODELABEL_VARGS(fn, ...) fn(clk_lsi, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lsi_FOREACH_ANCESTOR(fn) fn(DT_N_S_clocks) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_clocks_S_clk_lsi_CHILD_NUM 0
#define DT_N_S_clocks_S_clk_lsi_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_clocks_S_clk_lsi_FOREACH_CHILD(fn) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_clocks_S_clk_lsi_HASH y39tlAqwOoFHfznEDn2ZnvWSfYGNtJJvOJBnTUmFguY

/* Node's dependency ordinal: */
#define DT_N_S_clocks_S_clk_lsi_ORD 37
#define DT_N_S_clocks_S_clk_lsi_ORD_STR_SORTABLE 00037

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clocks_S_clk_lsi_REQUIRES_ORDS \
	6, /* /clocks */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clocks_S_clk_lsi_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_clocks_S_clk_lsi_IDX_0_C_TOKEN clk_lsi

/* Existence and alternate IDs: */
#define DT_N_S_clocks_S_clk_lsi_EXISTS 1
#define DT_N_INST_0_fixed_clock DT_N_S_clocks_S_clk_lsi
#define DT_N_NODELABEL_clk_lsi  DT_N_S_clocks_S_clk_lsi

/* Macros for properties that are special in the specification: */
#define DT_N_S_clocks_S_clk_lsi_REG_NUM 0
#define DT_N_S_clocks_S_clk_lsi_FOREACH_REG(fn) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_clk_lsi_RANGES_NUM 0
#define DT_N_S_clocks_S_clk_lsi_FOREACH_RANGE(fn) 
#define DT_N_S_clocks_S_clk_lsi_IRQ_NUM 0
#define DT_N_S_clocks_S_clk_lsi_IRQ_LEVEL 0
#define DT_N_S_clocks_S_clk_lsi_COMPAT_MATCHES_fixed_clock 1
#define DT_N_S_clocks_S_clk_lsi_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clocks_S_clk_lsi_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_clocks_S_clk_lsi_P_clock_frequency 32000
#define DT_N_S_clocks_S_clk_lsi_P_clock_frequency_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_status "okay"
#define DT_N_S_clocks_S_clk_lsi_P_status_STRING_UNQUOTED okay
#define DT_N_S_clocks_S_clk_lsi_P_status_STRING_TOKEN okay
#define DT_N_S_clocks_S_clk_lsi_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_clocks_S_clk_lsi_P_status_IDX_0 "okay"
#define DT_N_S_clocks_S_clk_lsi_P_status_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_clocks_S_clk_lsi_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_lsi, status, 0)
#define DT_N_S_clocks_S_clk_lsi_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_lsi, status, 0)
#define DT_N_S_clocks_S_clk_lsi_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_lsi, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lsi_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_lsi, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lsi_P_status_LEN 1
#define DT_N_S_clocks_S_clk_lsi_P_status_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_compatible {"fixed-clock"}
#define DT_N_S_clocks_S_clk_lsi_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_compatible_IDX_0 "fixed-clock"
#define DT_N_S_clocks_S_clk_lsi_P_compatible_IDX_0_STRING_UNQUOTED fixed-clock
#define DT_N_S_clocks_S_clk_lsi_P_compatible_IDX_0_STRING_TOKEN fixed_clock
#define DT_N_S_clocks_S_clk_lsi_P_compatible_IDX_0_STRING_UPPER_TOKEN FIXED_CLOCK
#define DT_N_S_clocks_S_clk_lsi_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_lsi, compatible, 0)
#define DT_N_S_clocks_S_clk_lsi_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_lsi, compatible, 0)
#define DT_N_S_clocks_S_clk_lsi_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_lsi, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lsi_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_lsi, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lsi_P_compatible_LEN 1
#define DT_N_S_clocks_S_clk_lsi_P_compatible_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_dma_coherent 0
#define DT_N_S_clocks_S_clk_lsi_P_dma_coherent_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_zephyr_deferred_init 0
#define DT_N_S_clocks_S_clk_lsi_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_wakeup_source 0
#define DT_N_S_clocks_S_clk_lsi_P_wakeup_source_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_clocks_S_clk_lsi_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /clocks/plli2s
 *
 * Node identifier: DT_N_S_clocks_S_plli2s
 *
 * Binding (compatible = st,stm32fx-pll-clock):
 *   $ZEPHYR_BASE\dts\bindings\clock\st,stm32fx-pll-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_clocks_S_plli2s_PATH "/clocks/plli2s"

/* Node's name with unit-address: */
#define DT_N_S_clocks_S_plli2s_FULL_NAME "plli2s"
#define DT_N_S_clocks_S_plli2s_FULL_NAME_UNQUOTED plli2s
#define DT_N_S_clocks_S_plli2s_FULL_NAME_TOKEN plli2s
#define DT_N_S_clocks_S_plli2s_FULL_NAME_UPPER_TOKEN PLLI2S

/* Node parent (/clocks) identifier: */
#define DT_N_S_clocks_S_plli2s_PARENT DT_N_S_clocks

/* Node's index in its parent's list of children: */
#define DT_N_S_clocks_S_plli2s_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_clocks_S_plli2s_NODELABEL_NUM 1
#define DT_N_S_clocks_S_plli2s_FOREACH_NODELABEL(fn) fn(plli2s)
#define DT_N_S_clocks_S_plli2s_FOREACH_NODELABEL_VARGS(fn, ...) fn(plli2s, __VA_ARGS__)
#define DT_N_S_clocks_S_plli2s_FOREACH_ANCESTOR(fn) fn(DT_N_S_clocks) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_clocks_S_plli2s_CHILD_NUM 0
#define DT_N_S_clocks_S_plli2s_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_clocks_S_plli2s_FOREACH_CHILD(fn) 
#define DT_N_S_clocks_S_plli2s_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_clocks_S_plli2s_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_clocks_S_plli2s_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_plli2s_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_clocks_S_plli2s_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_clocks_S_plli2s_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_clocks_S_plli2s_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_clocks_S_plli2s_HASH HAsz0Umb1vluPlDeNTHb1jAuqaeaEWaXbSZfjbz0oIU

/* Node's dependency ordinal: */
#define DT_N_S_clocks_S_plli2s_ORD 38
#define DT_N_S_clocks_S_plli2s_ORD_STR_SORTABLE 00038

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clocks_S_plli2s_REQUIRES_ORDS \
	6, /* /clocks */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clocks_S_plli2s_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_clocks_S_plli2s_IDX_0_C_TOKEN plli2s

/* Existence and alternate IDs: */
#define DT_N_S_clocks_S_plli2s_EXISTS 1
#define DT_N_INST_1_st_stm32fx_pll_clock DT_N_S_clocks_S_plli2s
#define DT_N_NODELABEL_plli2s            DT_N_S_clocks_S_plli2s

/* Macros for properties that are special in the specification: */
#define DT_N_S_clocks_S_plli2s_REG_NUM 0
#define DT_N_S_clocks_S_plli2s_FOREACH_REG(fn) 
#define DT_N_S_clocks_S_plli2s_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_clocks_S_plli2s_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_clocks_S_plli2s_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_plli2s_RANGES_NUM 0
#define DT_N_S_clocks_S_plli2s_FOREACH_RANGE(fn) 
#define DT_N_S_clocks_S_plli2s_IRQ_NUM 0
#define DT_N_S_clocks_S_plli2s_IRQ_LEVEL 0
#define DT_N_S_clocks_S_plli2s_COMPAT_MATCHES_st_stm32fx_pll_clock 1
#define DT_N_S_clocks_S_plli2s_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_plli2s_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_clocks_S_plli2s_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_plli2s_COMPAT_MODEL_IDX_0 "stm32fx-pll-clock"
#define DT_N_S_clocks_S_plli2s_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clocks_S_plli2s_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_clocks_S_plli2s_P_status "disabled"
#define DT_N_S_clocks_S_plli2s_P_status_STRING_UNQUOTED disabled
#define DT_N_S_clocks_S_plli2s_P_status_STRING_TOKEN disabled
#define DT_N_S_clocks_S_plli2s_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_clocks_S_plli2s_P_status_IDX_0 "disabled"
#define DT_N_S_clocks_S_plli2s_P_status_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_plli2s_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_clocks_S_plli2s_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_clocks_S_plli2s_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_clocks_S_plli2s_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_plli2s, status, 0)
#define DT_N_S_clocks_S_plli2s_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_plli2s, status, 0)
#define DT_N_S_clocks_S_plli2s_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_plli2s, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_plli2s_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_plli2s, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_plli2s_P_status_LEN 1
#define DT_N_S_clocks_S_plli2s_P_status_EXISTS 1
#define DT_N_S_clocks_S_plli2s_P_compatible {"st,stm32fx-pll-clock"}
#define DT_N_S_clocks_S_plli2s_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_plli2s_P_compatible_IDX_0 "st,stm32fx-pll-clock"
#define DT_N_S_clocks_S_plli2s_P_compatible_IDX_0_STRING_UNQUOTED st,stm32fx-pll-clock
#define DT_N_S_clocks_S_plli2s_P_compatible_IDX_0_STRING_TOKEN st_stm32fx_pll_clock
#define DT_N_S_clocks_S_plli2s_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32FX_PLL_CLOCK
#define DT_N_S_clocks_S_plli2s_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_plli2s, compatible, 0)
#define DT_N_S_clocks_S_plli2s_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_plli2s, compatible, 0)
#define DT_N_S_clocks_S_plli2s_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_plli2s, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_plli2s_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_plli2s, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_plli2s_P_compatible_LEN 1
#define DT_N_S_clocks_S_plli2s_P_compatible_EXISTS 1
#define DT_N_S_clocks_S_plli2s_P_dma_coherent 0
#define DT_N_S_clocks_S_plli2s_P_dma_coherent_EXISTS 1
#define DT_N_S_clocks_S_plli2s_P_zephyr_deferred_init 0
#define DT_N_S_clocks_S_plli2s_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_clocks_S_plli2s_P_wakeup_source 0
#define DT_N_S_clocks_S_plli2s_P_wakeup_source_EXISTS 1
#define DT_N_S_clocks_S_plli2s_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_clocks_S_plli2s_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /clocks/pllsai
 *
 * Node identifier: DT_N_S_clocks_S_pllsai
 *
 * Binding (compatible = st,stm32fx-pll-clock):
 *   $ZEPHYR_BASE\dts\bindings\clock\st,stm32fx-pll-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_clocks_S_pllsai_PATH "/clocks/pllsai"

/* Node's name with unit-address: */
#define DT_N_S_clocks_S_pllsai_FULL_NAME "pllsai"
#define DT_N_S_clocks_S_pllsai_FULL_NAME_UNQUOTED pllsai
#define DT_N_S_clocks_S_pllsai_FULL_NAME_TOKEN pllsai
#define DT_N_S_clocks_S_pllsai_FULL_NAME_UPPER_TOKEN PLLSAI

/* Node parent (/clocks) identifier: */
#define DT_N_S_clocks_S_pllsai_PARENT DT_N_S_clocks

/* Node's index in its parent's list of children: */
#define DT_N_S_clocks_S_pllsai_CHILD_IDX 6

/* Helpers for dealing with node labels: */
#define DT_N_S_clocks_S_pllsai_NODELABEL_NUM 1
#define DT_N_S_clocks_S_pllsai_FOREACH_NODELABEL(fn) fn(pllsai)
#define DT_N_S_clocks_S_pllsai_FOREACH_NODELABEL_VARGS(fn, ...) fn(pllsai, __VA_ARGS__)
#define DT_N_S_clocks_S_pllsai_FOREACH_ANCESTOR(fn) fn(DT_N_S_clocks) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_clocks_S_pllsai_CHILD_NUM 0
#define DT_N_S_clocks_S_pllsai_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_clocks_S_pllsai_FOREACH_CHILD(fn) 
#define DT_N_S_clocks_S_pllsai_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_clocks_S_pllsai_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_clocks_S_pllsai_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_pllsai_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_clocks_S_pllsai_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_clocks_S_pllsai_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_clocks_S_pllsai_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_clocks_S_pllsai_HASH QuxophBroiJKCiRN4RnNLbxpI_Ih0_XL8lKwmknUpjs

/* Node's dependency ordinal: */
#define DT_N_S_clocks_S_pllsai_ORD 39
#define DT_N_S_clocks_S_pllsai_ORD_STR_SORTABLE 00039

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clocks_S_pllsai_REQUIRES_ORDS \
	6, /* /clocks */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clocks_S_pllsai_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_clocks_S_pllsai_IDX_0_C_TOKEN pllsai

/* Existence and alternate IDs: */
#define DT_N_S_clocks_S_pllsai_EXISTS 1
#define DT_N_INST_2_st_stm32fx_pll_clock DT_N_S_clocks_S_pllsai
#define DT_N_NODELABEL_pllsai            DT_N_S_clocks_S_pllsai

/* Macros for properties that are special in the specification: */
#define DT_N_S_clocks_S_pllsai_REG_NUM 0
#define DT_N_S_clocks_S_pllsai_FOREACH_REG(fn) 
#define DT_N_S_clocks_S_pllsai_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_clocks_S_pllsai_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_clocks_S_pllsai_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_pllsai_RANGES_NUM 0
#define DT_N_S_clocks_S_pllsai_FOREACH_RANGE(fn) 
#define DT_N_S_clocks_S_pllsai_IRQ_NUM 0
#define DT_N_S_clocks_S_pllsai_IRQ_LEVEL 0
#define DT_N_S_clocks_S_pllsai_COMPAT_MATCHES_st_stm32fx_pll_clock 1
#define DT_N_S_clocks_S_pllsai_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_pllsai_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_clocks_S_pllsai_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_pllsai_COMPAT_MODEL_IDX_0 "stm32fx-pll-clock"
#define DT_N_S_clocks_S_pllsai_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clocks_S_pllsai_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_clocks_S_pllsai_P_status "disabled"
#define DT_N_S_clocks_S_pllsai_P_status_STRING_UNQUOTED disabled
#define DT_N_S_clocks_S_pllsai_P_status_STRING_TOKEN disabled
#define DT_N_S_clocks_S_pllsai_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_clocks_S_pllsai_P_status_IDX_0 "disabled"
#define DT_N_S_clocks_S_pllsai_P_status_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_pllsai_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_clocks_S_pllsai_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_clocks_S_pllsai_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_clocks_S_pllsai_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_pllsai, status, 0)
#define DT_N_S_clocks_S_pllsai_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_pllsai, status, 0)
#define DT_N_S_clocks_S_pllsai_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_pllsai, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_pllsai_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_pllsai, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_pllsai_P_status_LEN 1
#define DT_N_S_clocks_S_pllsai_P_status_EXISTS 1
#define DT_N_S_clocks_S_pllsai_P_compatible {"st,stm32fx-pll-clock"}
#define DT_N_S_clocks_S_pllsai_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_pllsai_P_compatible_IDX_0 "st,stm32fx-pll-clock"
#define DT_N_S_clocks_S_pllsai_P_compatible_IDX_0_STRING_UNQUOTED st,stm32fx-pll-clock
#define DT_N_S_clocks_S_pllsai_P_compatible_IDX_0_STRING_TOKEN st_stm32fx_pll_clock
#define DT_N_S_clocks_S_pllsai_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32FX_PLL_CLOCK
#define DT_N_S_clocks_S_pllsai_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_pllsai, compatible, 0)
#define DT_N_S_clocks_S_pllsai_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_pllsai, compatible, 0)
#define DT_N_S_clocks_S_pllsai_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_pllsai, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_pllsai_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_pllsai, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_pllsai_P_compatible_LEN 1
#define DT_N_S_clocks_S_pllsai_P_compatible_EXISTS 1
#define DT_N_S_clocks_S_pllsai_P_dma_coherent 0
#define DT_N_S_clocks_S_pllsai_P_dma_coherent_EXISTS 1
#define DT_N_S_clocks_S_pllsai_P_zephyr_deferred_init 0
#define DT_N_S_clocks_S_pllsai_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_clocks_S_pllsai_P_wakeup_source 0
#define DT_N_S_clocks_S_pllsai_P_wakeup_source_EXISTS 1
#define DT_N_S_clocks_S_pllsai_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_clocks_S_pllsai_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /cpus
 *
 * Node identifier: DT_N_S_cpus
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_PATH "/cpus"

/* Node's name with unit-address: */
#define DT_N_S_cpus_FULL_NAME "cpus"
#define DT_N_S_cpus_FULL_NAME_UNQUOTED cpus
#define DT_N_S_cpus_FULL_NAME_TOKEN cpus
#define DT_N_S_cpus_FULL_NAME_UPPER_TOKEN CPUS

/* Node parent (/) identifier: */
#define DT_N_S_cpus_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_NODELABEL_NUM 0
#define DT_N_S_cpus_FOREACH_NODELABEL(fn) 
#define DT_N_S_cpus_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_cpus_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_CHILD_NUM 2
#define DT_N_S_cpus_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_cpus_CHILD_UNIT_ADDR_INT_0 DT_N_S_cpus_S_cpu_0
#define DT_N_S_cpus_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_power_states)
#define DT_N_S_cpus_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_power_states)
#define DT_N_S_cpus_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_power_states, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_power_states)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_power_states)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_power_states, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_cpus_HASH iL3XRGZVvvtpNJqKV0_jvtuXF7m6kgky4nI2ifizwdg

/* Node's dependency ordinal: */
#define DT_N_S_cpus_ORD 40
#define DT_N_S_cpus_ORD_STR_SORTABLE 00040

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_SUPPORTS_ORDS \
	41, /* /cpus/power-states */ \
	43, /* /cpus/cpu@0 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_REG_NUM 0
#define DT_N_S_cpus_FOREACH_REG(fn) 
#define DT_N_S_cpus_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_cpus_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_cpus_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_RANGES_NUM 0
#define DT_N_S_cpus_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_IRQ_NUM 0
#define DT_N_S_cpus_IRQ_LEVEL 0
#define DT_N_S_cpus_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /cpus/power-states
 *
 * Node identifier: DT_N_S_cpus_S_power_states
 */

/* Node's full path: */
#define DT_N_S_cpus_S_power_states_PATH "/cpus/power-states"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_power_states_FULL_NAME "power-states"
#define DT_N_S_cpus_S_power_states_FULL_NAME_UNQUOTED power-states
#define DT_N_S_cpus_S_power_states_FULL_NAME_TOKEN power_states
#define DT_N_S_cpus_S_power_states_FULL_NAME_UPPER_TOKEN POWER_STATES

/* Node parent (/cpus) identifier: */
#define DT_N_S_cpus_S_power_states_PARENT DT_N_S_cpus

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_power_states_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_S_power_states_NODELABEL_NUM 0
#define DT_N_S_cpus_S_power_states_FOREACH_NODELABEL(fn) 
#define DT_N_S_cpus_S_power_states_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_FOREACH_ANCESTOR(fn) fn(DT_N_S_cpus) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_power_states_CHILD_NUM 1
#define DT_N_S_cpus_S_power_states_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_power_states_S_stop)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_power_states_S_stop)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_power_states_S_stop, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_power_states_S_stop, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_power_states_S_stop)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_power_states_S_stop)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_power_states_S_stop, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_power_states_S_stop, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_cpus_S_power_states_HASH qMexuiO6C_SHOSQQCC_3by3odasm1z5VRx723zYLVgY

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_power_states_ORD 41
#define DT_N_S_cpus_S_power_states_ORD_STR_SORTABLE 00041

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_power_states_REQUIRES_ORDS \
	40, /* /cpus */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_power_states_SUPPORTS_ORDS \
	42, /* /cpus/power-states/stop */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_power_states_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_power_states_REG_NUM 0
#define DT_N_S_cpus_S_power_states_FOREACH_REG(fn) 
#define DT_N_S_cpus_S_power_states_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_cpus_S_power_states_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_power_states_RANGES_NUM 0
#define DT_N_S_cpus_S_power_states_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_power_states_IRQ_NUM 0
#define DT_N_S_cpus_S_power_states_IRQ_LEVEL 0
#define DT_N_S_cpus_S_power_states_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_power_states_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /cpus/power-states/stop
 *
 * Node identifier: DT_N_S_cpus_S_power_states_S_stop
 *
 * Binding (compatible = zephyr,power-state):
 *   $ZEPHYR_BASE\dts\bindings\power\zephyr,power-state.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_power_states_S_stop_PATH "/cpus/power-states/stop"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_power_states_S_stop_FULL_NAME "stop"
#define DT_N_S_cpus_S_power_states_S_stop_FULL_NAME_UNQUOTED stop
#define DT_N_S_cpus_S_power_states_S_stop_FULL_NAME_TOKEN stop
#define DT_N_S_cpus_S_power_states_S_stop_FULL_NAME_UPPER_TOKEN STOP

/* Node parent (/cpus/power-states) identifier: */
#define DT_N_S_cpus_S_power_states_S_stop_PARENT DT_N_S_cpus_S_power_states

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_power_states_S_stop_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_S_power_states_S_stop_NODELABEL_NUM 1
#define DT_N_S_cpus_S_power_states_S_stop_FOREACH_NODELABEL(fn) fn(stop)
#define DT_N_S_cpus_S_power_states_S_stop_FOREACH_NODELABEL_VARGS(fn, ...) fn(stop, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_S_stop_FOREACH_ANCESTOR(fn) fn(DT_N_S_cpus_S_power_states) fn(DT_N_S_cpus) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_power_states_S_stop_CHILD_NUM 0
#define DT_N_S_cpus_S_power_states_S_stop_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_cpus_S_power_states_S_stop_FOREACH_CHILD(fn) 
#define DT_N_S_cpus_S_power_states_S_stop_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_cpus_S_power_states_S_stop_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_S_stop_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_power_states_S_stop_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_cpus_S_power_states_S_stop_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_cpus_S_power_states_S_stop_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_S_stop_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_cpus_S_power_states_S_stop_HASH bjdmlraC7R_lBgZaxqx6cOXwoGiyFZoPvLeJocMdHP0

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_power_states_S_stop_ORD 42
#define DT_N_S_cpus_S_power_states_S_stop_ORD_STR_SORTABLE 00042

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_power_states_S_stop_REQUIRES_ORDS \
	41, /* /cpus/power-states */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_power_states_S_stop_SUPPORTS_ORDS \
	43, /* /cpus/cpu@0 */
#define DT_N_NODELABEL_DT_N_S_cpus_S_power_states_S_stop_IDX_0_C_TOKEN stop

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_power_states_S_stop_EXISTS 1
#define DT_N_INST_0_zephyr_power_state DT_N_S_cpus_S_power_states_S_stop
#define DT_N_NODELABEL_stop            DT_N_S_cpus_S_power_states_S_stop

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_power_states_S_stop_REG_NUM 0
#define DT_N_S_cpus_S_power_states_S_stop_FOREACH_REG(fn) 
#define DT_N_S_cpus_S_power_states_S_stop_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_cpus_S_power_states_S_stop_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_S_stop_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_power_states_S_stop_RANGES_NUM 0
#define DT_N_S_cpus_S_power_states_S_stop_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_power_states_S_stop_IRQ_NUM 0
#define DT_N_S_cpus_S_power_states_S_stop_IRQ_LEVEL 0
#define DT_N_S_cpus_S_power_states_S_stop_COMPAT_MATCHES_zephyr_power_state 1
#define DT_N_S_cpus_S_power_states_S_stop_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_stop_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_cpus_S_power_states_S_stop_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_stop_COMPAT_MODEL_IDX_0 "power-state"
#define DT_N_S_cpus_S_power_states_S_stop_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_power_states_S_stop_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_cpus_S_power_states_S_stop_P_power_state_name "suspend-to-idle"
#define DT_N_S_cpus_S_power_states_S_stop_P_power_state_name_STRING_UNQUOTED suspend-to-idle
#define DT_N_S_cpus_S_power_states_S_stop_P_power_state_name_STRING_TOKEN suspend_to_idle
#define DT_N_S_cpus_S_power_states_S_stop_P_power_state_name_STRING_UPPER_TOKEN SUSPEND_TO_IDLE
#define DT_N_S_cpus_S_power_states_S_stop_P_power_state_name_IDX_0 "suspend-to-idle"
#define DT_N_S_cpus_S_power_states_S_stop_P_power_state_name_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_stop_P_power_state_name_IDX_0_ENUM_IDX 2
#define DT_N_S_cpus_S_power_states_S_stop_P_power_state_name_IDX_0_ENUM_VAL_suspend_to_idle_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_stop_P_power_state_name_ENUM_VAL_suspend_to_idle_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_stop_P_power_state_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_power_states_S_stop, power_state_name, 0)
#define DT_N_S_cpus_S_power_states_S_stop_P_power_state_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_power_states_S_stop, power_state_name, 0)
#define DT_N_S_cpus_S_power_states_S_stop_P_power_state_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_power_states_S_stop, power_state_name, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_S_stop_P_power_state_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_power_states_S_stop, power_state_name, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_S_stop_P_power_state_name_LEN 1
#define DT_N_S_cpus_S_power_states_S_stop_P_power_state_name_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_stop_P_min_residency_us 400
#define DT_N_S_cpus_S_power_states_S_stop_P_min_residency_us_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_stop_P_exit_latency_us 300
#define DT_N_S_cpus_S_power_states_S_stop_P_exit_latency_us_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_stop_P_zephyr_pm_device_disabled 0
#define DT_N_S_cpus_S_power_states_S_stop_P_zephyr_pm_device_disabled_EXISTS 1

/*
 * Devicetree node: /cpus/cpu@0
 *
 * Node identifier: DT_N_S_cpus_S_cpu_0
 *
 * Binding (compatible = arm,cortex-m4f):
 *   $ZEPHYR_BASE\dts\bindings\cpu\arm,cortex-m4f.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_cpu_0_PATH "/cpus/cpu@0"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_cpu_0_FULL_NAME "cpu@0"
#define DT_N_S_cpus_S_cpu_0_FULL_NAME_UNQUOTED cpu@0
#define DT_N_S_cpus_S_cpu_0_FULL_NAME_TOKEN cpu_0
#define DT_N_S_cpus_S_cpu_0_FULL_NAME_UPPER_TOKEN CPU_0

/* Node parent (/cpus) identifier: */
#define DT_N_S_cpus_S_cpu_0_PARENT DT_N_S_cpus

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_cpu_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_S_cpu_0_NODELABEL_NUM 1
#define DT_N_S_cpus_S_cpu_0_FOREACH_NODELABEL(fn) fn(cpu0)
#define DT_N_S_cpus_S_cpu_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(cpu0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_cpus) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_cpu_0_CHILD_NUM 0
#define DT_N_S_cpus_S_cpu_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD(fn) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_cpus_S_cpu_0_HASH Su0JBbOtM0QIxe_1ka2Xvgw4rk1QaIlMIj8Rp_v4yVQ

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_cpu_0_ORD 43
#define DT_N_S_cpus_S_cpu_0_ORD_STR_SORTABLE 00043

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_cpu_0_REQUIRES_ORDS \
	40, /* /cpus */ \
	42, /* /cpus/power-states/stop */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_cpu_0_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_cpus_S_cpu_0_IDX_0_C_TOKEN cpu0

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_0_EXISTS 1
#define DT_N_INST_0_arm_cortex_m4f DT_N_S_cpus_S_cpu_0
#define DT_N_NODELABEL_cpu0        DT_N_S_cpus_S_cpu_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_cpu_0_REG_NUM 1
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_cpus_S_cpu_0_FOREACH_REG(fn) fn(DT_N_S_cpus_S_cpu_0, 0)
#define DT_N_S_cpus_S_cpu_0_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, 0)
#define DT_N_S_cpus_S_cpu_0_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_RANGES_NUM 0
#define DT_N_S_cpus_S_cpu_0_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_cpu_0_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_0_IRQ_LEVEL 0
#define DT_N_S_cpus_S_cpu_0_COMPAT_MATCHES_arm_cortex_m4f 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0 "cortex-m4f"
#define DT_N_S_cpus_S_cpu_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_cpu_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_IDX_0 DT_N_S_cpus_S_power_states_S_stop
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_IDX_0_PH DT_N_S_cpus_S_power_states_S_stop
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 0)
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 0)
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_LEN 1
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_compatible {"arm,cortex-m4f"}
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0 "arm,cortex-m4f"
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UNQUOTED arm,cortex-m4f
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_TOKEN arm_cortex_m4f
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_CORTEX_M4F
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_0_P_compatible_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_reg {0 /* 0x0 */}
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0 0
#define DT_N_S_cpus_S_cpu_0_P_reg_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_dma_coherent 0
#define DT_N_S_cpus_S_cpu_0_P_dma_coherent_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_zephyr_deferred_init 0
#define DT_N_S_cpus_S_cpu_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_wakeup_source 0
#define DT_N_S_cpus_S_cpu_0_P_wakeup_source_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/gpio@40020800
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800
 *
 * Binding (compatible = st,stm32-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\st,stm32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_PATH "/soc/pin-controller@40020000/gpio@40020800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FULL_NAME "gpio@40020800"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FULL_NAME_UNQUOTED gpio@40020800
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FULL_NAME_TOKEN gpio_40020800
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FULL_NAME_UPPER_TOKEN GPIO_40020800

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FOREACH_NODELABEL(fn) fn(gpioc)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpioc, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_HASH dkVg2_JRqNLYGR_Am7EW_AsYqMF_0j5GHuZXAVzOI1A

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_ORD 44
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_ORD_STR_SORTABLE 00044

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_REQUIRES_ORDS \
	9, /* /soc/rcc@40023800 */ \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_SUPPORTS_ORDS \
	45, /* /gpio_keys */ \
	46, /* /gpio_keys/button */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_IDX_0_C_TOKEN gpioc

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_EXISTS 1
#define DT_N_INST_2_st_stm32_gpio DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800
#define DT_N_NODELABEL_gpioc      DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_REG_IDX_0_VAL_ADDRESS 1073874944 /* 0x40020800 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_COMPAT_MATCHES_st_stm32_gpio 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_COMPAT_MODEL_IDX_0 "stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_reg {1073874944 /* 0x40020800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_reg_IDX_0 1073874944
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_clocks_IDX_0_VAL_bus 48
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_clocks_IDX_0_VAL_bits 4
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_clocks_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_ngpios 16
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_gpio_controller 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_compatible {"st,stm32-gpio"}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_compatible_IDX_0 "st,stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /gpio_keys
 *
 * Node identifier: DT_N_S_gpio_keys
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\input\gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpio_keys_PATH "/gpio_keys"

/* Node's name with unit-address: */
#define DT_N_S_gpio_keys_FULL_NAME "gpio_keys"
#define DT_N_S_gpio_keys_FULL_NAME_UNQUOTED gpio_keys
#define DT_N_S_gpio_keys_FULL_NAME_TOKEN gpio_keys
#define DT_N_S_gpio_keys_FULL_NAME_UPPER_TOKEN GPIO_KEYS

/* Node parent (/) identifier: */
#define DT_N_S_gpio_keys_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_gpio_keys_CHILD_IDX 19

/* Helpers for dealing with node labels: */
#define DT_N_S_gpio_keys_NODELABEL_NUM 0
#define DT_N_S_gpio_keys_FOREACH_NODELABEL(fn) 
#define DT_N_S_gpio_keys_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_gpio_keys_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_gpio_keys_CHILD_NUM 1
#define DT_N_S_gpio_keys_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_gpio_keys_FOREACH_CHILD(fn) fn(DT_N_S_gpio_keys_S_button)
#define DT_N_S_gpio_keys_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_gpio_keys_S_button)
#define DT_N_S_gpio_keys_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_gpio_keys_S_button, __VA_ARGS__)
#define DT_N_S_gpio_keys_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_keys_S_button, __VA_ARGS__)
#define DT_N_S_gpio_keys_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_gpio_keys_S_button)
#define DT_N_S_gpio_keys_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_gpio_keys_S_button)
#define DT_N_S_gpio_keys_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_gpio_keys_S_button, __VA_ARGS__)
#define DT_N_S_gpio_keys_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_keys_S_button, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_gpio_keys_HASH o_cyM_1oGxkDdZvjWwmF_qWSV_TFQR0RmVqGE69cQ78

/* Node's dependency ordinal: */
#define DT_N_S_gpio_keys_ORD 45
#define DT_N_S_gpio_keys_ORD_STR_SORTABLE 00045

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpio_keys_REQUIRES_ORDS \
	0, /* / */ \
	44, /* /soc/pin-controller@40020000/gpio@40020800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpio_keys_SUPPORTS_ORDS \
	46, /* /gpio_keys/button */

/* Existence and alternate IDs: */
#define DT_N_S_gpio_keys_EXISTS 1
#define DT_N_INST_0_gpio_keys DT_N_S_gpio_keys

/* Macros for properties that are special in the specification: */
#define DT_N_S_gpio_keys_REG_NUM 0
#define DT_N_S_gpio_keys_FOREACH_REG(fn) 
#define DT_N_S_gpio_keys_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_gpio_keys_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_gpio_keys_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_gpio_keys_RANGES_NUM 0
#define DT_N_S_gpio_keys_FOREACH_RANGE(fn) 
#define DT_N_S_gpio_keys_IRQ_NUM 0
#define DT_N_S_gpio_keys_IRQ_LEVEL 0
#define DT_N_S_gpio_keys_COMPAT_MATCHES_gpio_keys 1
#define DT_N_S_gpio_keys_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_gpio_keys_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_gpio_keys_P_debounce_interval_ms 30
#define DT_N_S_gpio_keys_P_debounce_interval_ms_EXISTS 1
#define DT_N_S_gpio_keys_P_polling_mode 0
#define DT_N_S_gpio_keys_P_polling_mode_EXISTS 1
#define DT_N_S_gpio_keys_P_zephyr_suspend_action "disconnect-with-pupd"
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_STRING_UNQUOTED disconnect-with-pupd
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_STRING_TOKEN disconnect_with_pupd
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_STRING_UPPER_TOKEN DISCONNECT_WITH_PUPD
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_IDX_0 "disconnect-with-pupd"
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_IDX_0_EXISTS 1
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_IDX_0_ENUM_IDX 1
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_IDX_0_ENUM_VAL_disconnect_with_pupd_EXISTS 1
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_ENUM_VAL_disconnect_with_pupd_EXISTS 1
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_FOREACH_PROP_ELEM(fn) fn(DT_N_S_gpio_keys, zephyr_suspend_action, 0)
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_gpio_keys, zephyr_suspend_action, 0)
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_gpio_keys, zephyr_suspend_action, 0, __VA_ARGS__)
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_keys, zephyr_suspend_action, 0, __VA_ARGS__)
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_LEN 1
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_EXISTS 1
#define DT_N_S_gpio_keys_P_compatible {"gpio-keys"}
#define DT_N_S_gpio_keys_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_gpio_keys_P_compatible_IDX_0 "gpio-keys"
#define DT_N_S_gpio_keys_P_compatible_IDX_0_STRING_UNQUOTED gpio-keys
#define DT_N_S_gpio_keys_P_compatible_IDX_0_STRING_TOKEN gpio_keys
#define DT_N_S_gpio_keys_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_KEYS
#define DT_N_S_gpio_keys_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_gpio_keys, compatible, 0)
#define DT_N_S_gpio_keys_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_gpio_keys, compatible, 0)
#define DT_N_S_gpio_keys_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_gpio_keys, compatible, 0, __VA_ARGS__)
#define DT_N_S_gpio_keys_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_keys, compatible, 0, __VA_ARGS__)
#define DT_N_S_gpio_keys_P_compatible_LEN 1
#define DT_N_S_gpio_keys_P_compatible_EXISTS 1
#define DT_N_S_gpio_keys_P_dma_coherent 0
#define DT_N_S_gpio_keys_P_dma_coherent_EXISTS 1
#define DT_N_S_gpio_keys_P_zephyr_deferred_init 0
#define DT_N_S_gpio_keys_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_gpio_keys_P_wakeup_source 0
#define DT_N_S_gpio_keys_P_wakeup_source_EXISTS 1
#define DT_N_S_gpio_keys_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_gpio_keys_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /gpio_keys/button
 *
 * Node identifier: DT_N_S_gpio_keys_S_button
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpio_keys_S_button_PATH "/gpio_keys/button"

/* Node's name with unit-address: */
#define DT_N_S_gpio_keys_S_button_FULL_NAME "button"
#define DT_N_S_gpio_keys_S_button_FULL_NAME_UNQUOTED button
#define DT_N_S_gpio_keys_S_button_FULL_NAME_TOKEN button
#define DT_N_S_gpio_keys_S_button_FULL_NAME_UPPER_TOKEN BUTTON

/* Node parent (/gpio_keys) identifier: */
#define DT_N_S_gpio_keys_S_button_PARENT DT_N_S_gpio_keys

/* Node's index in its parent's list of children: */
#define DT_N_S_gpio_keys_S_button_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_gpio_keys_S_button_NODELABEL_NUM 1
#define DT_N_S_gpio_keys_S_button_FOREACH_NODELABEL(fn) fn(user_button)
#define DT_N_S_gpio_keys_S_button_FOREACH_NODELABEL_VARGS(fn, ...) fn(user_button, __VA_ARGS__)
#define DT_N_S_gpio_keys_S_button_FOREACH_ANCESTOR(fn) fn(DT_N_S_gpio_keys) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_gpio_keys_S_button_CHILD_NUM 0
#define DT_N_S_gpio_keys_S_button_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_gpio_keys_S_button_FOREACH_CHILD(fn) 
#define DT_N_S_gpio_keys_S_button_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_gpio_keys_S_button_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_gpio_keys_S_button_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_gpio_keys_S_button_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_gpio_keys_S_button_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_gpio_keys_S_button_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_gpio_keys_S_button_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_gpio_keys_S_button_HASH xGyp172f7ymL2kzXZ3NEGIppYDK1YGb1Ay3RG1U6EkA

/* Node's dependency ordinal: */
#define DT_N_S_gpio_keys_S_button_ORD 46
#define DT_N_S_gpio_keys_S_button_ORD_STR_SORTABLE 00046

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpio_keys_S_button_REQUIRES_ORDS \
	44, /* /soc/pin-controller@40020000/gpio@40020800 */ \
	45, /* /gpio_keys */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpio_keys_S_button_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_gpio_keys_S_button_IDX_0_C_TOKEN user_button

/* Existence and alternate IDs: */
#define DT_N_S_gpio_keys_S_button_EXISTS 1
#define DT_N_ALIAS_sw0             DT_N_S_gpio_keys_S_button
#define DT_N_NODELABEL_user_button DT_N_S_gpio_keys_S_button

/* Macros for properties that are special in the specification: */
#define DT_N_S_gpio_keys_S_button_REG_NUM 0
#define DT_N_S_gpio_keys_S_button_FOREACH_REG(fn) 
#define DT_N_S_gpio_keys_S_button_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_gpio_keys_S_button_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_gpio_keys_S_button_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_gpio_keys_S_button_RANGES_NUM 0
#define DT_N_S_gpio_keys_S_button_FOREACH_RANGE(fn) 
#define DT_N_S_gpio_keys_S_button_IRQ_NUM 0
#define DT_N_S_gpio_keys_S_button_IRQ_LEVEL 0
#define DT_N_S_gpio_keys_S_button_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_gpio_keys_S_button_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_gpio_keys_S_button_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_gpio_keys_S_button_P_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800
#define DT_N_S_gpio_keys_S_button_P_gpios_IDX_0_VAL_pin 13
#define DT_N_S_gpio_keys_S_button_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_gpio_keys_S_button_P_gpios_IDX_0_VAL_flags 0
#define DT_N_S_gpio_keys_S_button_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_gpio_keys_S_button_P_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_gpio_keys_S_button, gpios, 0, pin) \
	fn(DT_N_S_gpio_keys_S_button, gpios, 0, flags)
#define DT_N_S_gpio_keys_S_button_P_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_gpio_keys_S_button, gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_gpio_keys_S_button, gpios, 0, flags)
#define DT_N_S_gpio_keys_S_button_P_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_gpio_keys_S_button_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_gpio_keys_S_button, gpios, 0)
#define DT_N_S_gpio_keys_S_button_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_gpio_keys_S_button, gpios, 0)
#define DT_N_S_gpio_keys_S_button_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_gpio_keys_S_button, gpios, 0, __VA_ARGS__)
#define DT_N_S_gpio_keys_S_button_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_keys_S_button, gpios, 0, __VA_ARGS__)
#define DT_N_S_gpio_keys_S_button_P_gpios_LEN 1
#define DT_N_S_gpio_keys_S_button_P_gpios_EXISTS 1
#define DT_N_S_gpio_keys_S_button_P_label "User"
#define DT_N_S_gpio_keys_S_button_P_label_STRING_UNQUOTED User
#define DT_N_S_gpio_keys_S_button_P_label_STRING_TOKEN User
#define DT_N_S_gpio_keys_S_button_P_label_STRING_UPPER_TOKEN USER
#define DT_N_S_gpio_keys_S_button_P_label_IDX_0 "User"
#define DT_N_S_gpio_keys_S_button_P_label_IDX_0_EXISTS 1
#define DT_N_S_gpio_keys_S_button_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_gpio_keys_S_button, label, 0)
#define DT_N_S_gpio_keys_S_button_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_gpio_keys_S_button, label, 0)
#define DT_N_S_gpio_keys_S_button_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_gpio_keys_S_button, label, 0, __VA_ARGS__)
#define DT_N_S_gpio_keys_S_button_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_keys_S_button, label, 0, __VA_ARGS__)
#define DT_N_S_gpio_keys_S_button_P_label_LEN 1
#define DT_N_S_gpio_keys_S_button_P_label_EXISTS 1
#define DT_N_S_gpio_keys_S_button_P_zephyr_code 11
#define DT_N_S_gpio_keys_S_button_P_zephyr_code_EXISTS 1

/*
 * Devicetree node: /leds
 *
 * Node identifier: DT_N_S_leds
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE\dts\bindings\led\gpio-leds.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_PATH "/leds"

/* Node's name with unit-address: */
#define DT_N_S_leds_FULL_NAME "leds"
#define DT_N_S_leds_FULL_NAME_UNQUOTED leds
#define DT_N_S_leds_FULL_NAME_TOKEN leds
#define DT_N_S_leds_FULL_NAME_UPPER_TOKEN LEDS

/* Node parent (/) identifier: */
#define DT_N_S_leds_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_CHILD_IDX 18

/* Helpers for dealing with node labels: */
#define DT_N_S_leds_NODELABEL_NUM 1
#define DT_N_S_leds_FOREACH_NODELABEL(fn) fn(leds)
#define DT_N_S_leds_FOREACH_NODELABEL_VARGS(fn, ...) fn(leds, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_CHILD_NUM 3
#define DT_N_S_leds_CHILD_NUM_STATUS_OKAY 3
#define DT_N_S_leds_FOREACH_CHILD(fn) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3)
#define DT_N_S_leds_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_leds_S_led_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3)
#define DT_N_S_leds_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_leds_S_led_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_leds_HASH bMroFUocDdjE3kJ38dK18mDvlCOPoyya5kIIs76irj8

/* Node's dependency ordinal: */
#define DT_N_S_leds_ORD 47
#define DT_N_S_leds_ORD_STR_SORTABLE 00047

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_REQUIRES_ORDS \
	0, /* / */ \
	21, /* /soc/pin-controller@40020000/gpio@40020400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_SUPPORTS_ORDS \
	48, /* /leds/led_1 */ \
	49, /* /leds/led_2 */ \
	50, /* /leds/led_3 */
#define DT_N_NODELABEL_DT_N_S_leds_IDX_0_C_TOKEN leds

/* Existence and alternate IDs: */
#define DT_N_S_leds_EXISTS 1
#define DT_N_INST_0_gpio_leds DT_N_S_leds
#define DT_N_NODELABEL_leds   DT_N_S_leds

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_REG_NUM 0
#define DT_N_S_leds_FOREACH_REG(fn) 
#define DT_N_S_leds_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_leds_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_leds_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_RANGES_NUM 0
#define DT_N_S_leds_FOREACH_RANGE(fn) 
#define DT_N_S_leds_IRQ_NUM 0
#define DT_N_S_leds_IRQ_LEVEL 0
#define DT_N_S_leds_COMPAT_MATCHES_gpio_leds 1
#define DT_N_S_leds_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_P_compatible {"gpio-leds"}
#define DT_N_S_leds_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_leds_P_compatible_IDX_0 "gpio-leds"
#define DT_N_S_leds_P_compatible_IDX_0_STRING_UNQUOTED gpio-leds
#define DT_N_S_leds_P_compatible_IDX_0_STRING_TOKEN gpio_leds
#define DT_N_S_leds_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_LEDS
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds, compatible, 0)
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds, compatible, 0)
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__)
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__)
#define DT_N_S_leds_P_compatible_LEN 1
#define DT_N_S_leds_P_compatible_EXISTS 1

/*
 * Devicetree node: /leds/led_1
 *
 * Node identifier: DT_N_S_leds_S_led_1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_S_led_1_PATH "/leds/led_1"

/* Node's name with unit-address: */
#define DT_N_S_leds_S_led_1_FULL_NAME "led_1"
#define DT_N_S_leds_S_led_1_FULL_NAME_UNQUOTED led_1
#define DT_N_S_leds_S_led_1_FULL_NAME_TOKEN led_1
#define DT_N_S_leds_S_led_1_FULL_NAME_UPPER_TOKEN LED_1

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_1_PARENT DT_N_S_leds

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_S_led_1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_leds_S_led_1_NODELABEL_NUM 1
#define DT_N_S_leds_S_led_1_FOREACH_NODELABEL(fn) fn(green_led_1)
#define DT_N_S_leds_S_led_1_FOREACH_NODELABEL_VARGS(fn, ...) fn(green_led_1, __VA_ARGS__)
#define DT_N_S_leds_S_led_1_FOREACH_ANCESTOR(fn) fn(DT_N_S_leds) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_S_led_1_CHILD_NUM 0
#define DT_N_S_leds_S_led_1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_leds_S_led_1_FOREACH_CHILD(fn) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_leds_S_led_1_HASH iXGpSU4KdWdLNkNXyuDlz5Q9aavHPvjTPItAJ_Q0T5c

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_1_ORD 48
#define DT_N_S_leds_S_led_1_ORD_STR_SORTABLE 00048

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_1_REQUIRES_ORDS \
	21, /* /soc/pin-controller@40020000/gpio@40020400 */ \
	47, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_1_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_leds_S_led_1_IDX_0_C_TOKEN green_led_1

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_1_EXISTS 1
#define DT_N_ALIAS_led0            DT_N_S_leds_S_led_1
#define DT_N_NODELABEL_green_led_1 DT_N_S_leds_S_led_1

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_S_led_1_REG_NUM 0
#define DT_N_S_leds_S_led_1_FOREACH_REG(fn) 
#define DT_N_S_leds_S_led_1_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_leds_S_led_1_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_1_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_1_RANGES_NUM 0
#define DT_N_S_leds_S_led_1_FOREACH_RANGE(fn) 
#define DT_N_S_leds_S_led_1_IRQ_NUM 0
#define DT_N_S_leds_S_led_1_IRQ_LEVEL 0
#define DT_N_S_leds_S_led_1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_S_led_1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin 0
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags 0
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_leds_S_led_1, gpios, 0, pin) \
	fn(DT_N_S_leds_S_led_1, gpios, 0, flags)
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_leds_S_led_1, gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_1, gpios, 0, flags)
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_1, gpios, 0)
#define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_1, gpios, 0)
#define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_1, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_1, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_1_P_gpios_LEN 1
#define DT_N_S_leds_S_led_1_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_1_P_label "User LD1"
#define DT_N_S_leds_S_led_1_P_label_STRING_UNQUOTED User LD1
#define DT_N_S_leds_S_led_1_P_label_STRING_TOKEN User_LD1
#define DT_N_S_leds_S_led_1_P_label_STRING_UPPER_TOKEN USER_LD1
#define DT_N_S_leds_S_led_1_P_label_IDX_0 "User LD1"
#define DT_N_S_leds_S_led_1_P_label_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_1, label, 0)
#define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_1, label, 0)
#define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_1, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_1, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_1_P_label_LEN 1
#define DT_N_S_leds_S_led_1_P_label_EXISTS 1

/*
 * Devicetree node: /leds/led_2
 *
 * Node identifier: DT_N_S_leds_S_led_2
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_S_led_2_PATH "/leds/led_2"

/* Node's name with unit-address: */
#define DT_N_S_leds_S_led_2_FULL_NAME "led_2"
#define DT_N_S_leds_S_led_2_FULL_NAME_UNQUOTED led_2
#define DT_N_S_leds_S_led_2_FULL_NAME_TOKEN led_2
#define DT_N_S_leds_S_led_2_FULL_NAME_UPPER_TOKEN LED_2

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_2_PARENT DT_N_S_leds

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_S_led_2_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_leds_S_led_2_NODELABEL_NUM 1
#define DT_N_S_leds_S_led_2_FOREACH_NODELABEL(fn) fn(blue_led_1)
#define DT_N_S_leds_S_led_2_FOREACH_NODELABEL_VARGS(fn, ...) fn(blue_led_1, __VA_ARGS__)
#define DT_N_S_leds_S_led_2_FOREACH_ANCESTOR(fn) fn(DT_N_S_leds) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_S_led_2_CHILD_NUM 0
#define DT_N_S_leds_S_led_2_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_leds_S_led_2_FOREACH_CHILD(fn) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_leds_S_led_2_HASH KsPGInVliEI1PRs0DmyETNF7dyG4frBo_Z_DeHCKQaA

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_2_ORD 49
#define DT_N_S_leds_S_led_2_ORD_STR_SORTABLE 00049

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_2_REQUIRES_ORDS \
	21, /* /soc/pin-controller@40020000/gpio@40020400 */ \
	47, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_2_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_leds_S_led_2_IDX_0_C_TOKEN blue_led_1

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_2_EXISTS 1
#define DT_N_ALIAS_led1           DT_N_S_leds_S_led_2
#define DT_N_NODELABEL_blue_led_1 DT_N_S_leds_S_led_2

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_S_led_2_REG_NUM 0
#define DT_N_S_leds_S_led_2_FOREACH_REG(fn) 
#define DT_N_S_leds_S_led_2_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_leds_S_led_2_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_2_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_2_RANGES_NUM 0
#define DT_N_S_leds_S_led_2_FOREACH_RANGE(fn) 
#define DT_N_S_leds_S_led_2_IRQ_NUM 0
#define DT_N_S_leds_S_led_2_IRQ_LEVEL 0
#define DT_N_S_leds_S_led_2_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_S_led_2_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin 7
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags 0
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_leds_S_led_2, gpios, 0, pin) \
	fn(DT_N_S_leds_S_led_2, gpios, 0, flags)
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_leds_S_led_2, gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_2, gpios, 0, flags)
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_2, gpios, 0)
#define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_2, gpios, 0)
#define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_2, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_2, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_2_P_gpios_LEN 1
#define DT_N_S_leds_S_led_2_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_2_P_label "User LD2"
#define DT_N_S_leds_S_led_2_P_label_STRING_UNQUOTED User LD2
#define DT_N_S_leds_S_led_2_P_label_STRING_TOKEN User_LD2
#define DT_N_S_leds_S_led_2_P_label_STRING_UPPER_TOKEN USER_LD2
#define DT_N_S_leds_S_led_2_P_label_IDX_0 "User LD2"
#define DT_N_S_leds_S_led_2_P_label_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_2, label, 0)
#define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_2, label, 0)
#define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_2, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_2, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_2_P_label_LEN 1
#define DT_N_S_leds_S_led_2_P_label_EXISTS 1

/*
 * Devicetree node: /leds/led_3
 *
 * Node identifier: DT_N_S_leds_S_led_3
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_S_led_3_PATH "/leds/led_3"

/* Node's name with unit-address: */
#define DT_N_S_leds_S_led_3_FULL_NAME "led_3"
#define DT_N_S_leds_S_led_3_FULL_NAME_UNQUOTED led_3
#define DT_N_S_leds_S_led_3_FULL_NAME_TOKEN led_3
#define DT_N_S_leds_S_led_3_FULL_NAME_UPPER_TOKEN LED_3

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_3_PARENT DT_N_S_leds

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_S_led_3_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_leds_S_led_3_NODELABEL_NUM 1
#define DT_N_S_leds_S_led_3_FOREACH_NODELABEL(fn) fn(red_led_1)
#define DT_N_S_leds_S_led_3_FOREACH_NODELABEL_VARGS(fn, ...) fn(red_led_1, __VA_ARGS__)
#define DT_N_S_leds_S_led_3_FOREACH_ANCESTOR(fn) fn(DT_N_S_leds) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_S_led_3_CHILD_NUM 0
#define DT_N_S_leds_S_led_3_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_leds_S_led_3_FOREACH_CHILD(fn) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_leds_S_led_3_HASH pLTfITNsOL3nhJnRmoaWMqapL5v7uTq7eUydfMIb7KA

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_3_ORD 50
#define DT_N_S_leds_S_led_3_ORD_STR_SORTABLE 00050

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_3_REQUIRES_ORDS \
	21, /* /soc/pin-controller@40020000/gpio@40020400 */ \
	47, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_3_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_leds_S_led_3_IDX_0_C_TOKEN red_led_1

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_3_EXISTS 1
#define DT_N_ALIAS_led2          DT_N_S_leds_S_led_3
#define DT_N_NODELABEL_red_led_1 DT_N_S_leds_S_led_3

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_S_led_3_REG_NUM 0
#define DT_N_S_leds_S_led_3_FOREACH_REG(fn) 
#define DT_N_S_leds_S_led_3_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_leds_S_led_3_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_3_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_3_RANGES_NUM 0
#define DT_N_S_leds_S_led_3_FOREACH_RANGE(fn) 
#define DT_N_S_leds_S_led_3_IRQ_NUM 0
#define DT_N_S_leds_S_led_3_IRQ_LEVEL 0
#define DT_N_S_leds_S_led_3_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_S_led_3_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_pin 14
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_flags 0
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_leds_S_led_3, gpios, 0, pin) \
	fn(DT_N_S_leds_S_led_3, gpios, 0, flags)
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_leds_S_led_3, gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_3, gpios, 0, flags)
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_3, gpios, 0)
#define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_3, gpios, 0)
#define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_3, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_3, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_3_P_gpios_LEN 1
#define DT_N_S_leds_S_led_3_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_3_P_label "User LD3"
#define DT_N_S_leds_S_led_3_P_label_STRING_UNQUOTED User LD3
#define DT_N_S_leds_S_led_3_P_label_STRING_TOKEN User_LD3
#define DT_N_S_leds_S_led_3_P_label_STRING_UPPER_TOKEN USER_LD3
#define DT_N_S_leds_S_led_3_P_label_IDX_0 "User LD3"
#define DT_N_S_leds_S_led_3_P_label_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_3, label, 0)
#define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_3, label, 0)
#define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_3, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_3, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_3_P_label_LEN 1
#define DT_N_S_leds_S_led_3_P_label_EXISTS 1

/*
 * Devicetree node: /mcos
 *
 * Node identifier: DT_N_S_mcos
 */

/* Node's full path: */
#define DT_N_S_mcos_PATH "/mcos"

/* Node's name with unit-address: */
#define DT_N_S_mcos_FULL_NAME "mcos"
#define DT_N_S_mcos_FULL_NAME_UNQUOTED mcos
#define DT_N_S_mcos_FULL_NAME_TOKEN mcos
#define DT_N_S_mcos_FULL_NAME_UPPER_TOKEN MCOS

/* Node parent (/) identifier: */
#define DT_N_S_mcos_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_mcos_CHILD_IDX 6

/* Helpers for dealing with node labels: */
#define DT_N_S_mcos_NODELABEL_NUM 0
#define DT_N_S_mcos_FOREACH_NODELABEL(fn) 
#define DT_N_S_mcos_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_mcos_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_mcos_CHILD_NUM 2
#define DT_N_S_mcos_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_mcos_FOREACH_CHILD(fn) fn(DT_N_S_mcos_S_mco1) fn(DT_N_S_mcos_S_mco2)
#define DT_N_S_mcos_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_mcos_S_mco1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_mcos_S_mco2)
#define DT_N_S_mcos_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_mcos_S_mco1, __VA_ARGS__) fn(DT_N_S_mcos_S_mco2, __VA_ARGS__)
#define DT_N_S_mcos_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mcos_S_mco1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_mcos_S_mco2, __VA_ARGS__)
#define DT_N_S_mcos_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_mcos_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_mcos_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_mcos_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_mcos_HASH 6SPQgIfzgP5rJNinRk1zLBq_DlKqwei9gyXlUnsq0Fg

/* Node's dependency ordinal: */
#define DT_N_S_mcos_ORD 51
#define DT_N_S_mcos_ORD_STR_SORTABLE 00051

/* Ordinals for what this node depends on directly: */
#define DT_N_S_mcos_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_mcos_SUPPORTS_ORDS \
	52, /* /mcos/mco1 */ \
	53, /* /mcos/mco2 */

/* Existence and alternate IDs: */
#define DT_N_S_mcos_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_mcos_REG_NUM 0
#define DT_N_S_mcos_FOREACH_REG(fn) 
#define DT_N_S_mcos_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_mcos_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_mcos_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_mcos_RANGES_NUM 0
#define DT_N_S_mcos_FOREACH_RANGE(fn) 
#define DT_N_S_mcos_IRQ_NUM 0
#define DT_N_S_mcos_IRQ_LEVEL 0
#define DT_N_S_mcos_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_mcos_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /mcos/mco1
 *
 * Node identifier: DT_N_S_mcos_S_mco1
 *
 * Binding (compatible = st,stm32-clock-mco):
 *   $ZEPHYR_BASE\dts\bindings\clock\st,stm32-clock-mco.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_mcos_S_mco1_PATH "/mcos/mco1"

/* Node's name with unit-address: */
#define DT_N_S_mcos_S_mco1_FULL_NAME "mco1"
#define DT_N_S_mcos_S_mco1_FULL_NAME_UNQUOTED mco1
#define DT_N_S_mcos_S_mco1_FULL_NAME_TOKEN mco1
#define DT_N_S_mcos_S_mco1_FULL_NAME_UPPER_TOKEN MCO1

/* Node parent (/mcos) identifier: */
#define DT_N_S_mcos_S_mco1_PARENT DT_N_S_mcos

/* Node's index in its parent's list of children: */
#define DT_N_S_mcos_S_mco1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_mcos_S_mco1_NODELABEL_NUM 1
#define DT_N_S_mcos_S_mco1_FOREACH_NODELABEL(fn) fn(mco1)
#define DT_N_S_mcos_S_mco1_FOREACH_NODELABEL_VARGS(fn, ...) fn(mco1, __VA_ARGS__)
#define DT_N_S_mcos_S_mco1_FOREACH_ANCESTOR(fn) fn(DT_N_S_mcos) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_mcos_S_mco1_CHILD_NUM 0
#define DT_N_S_mcos_S_mco1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_mcos_S_mco1_FOREACH_CHILD(fn) 
#define DT_N_S_mcos_S_mco1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_mcos_S_mco1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_mcos_S_mco1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_mcos_S_mco1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_mcos_S_mco1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_mcos_S_mco1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_mcos_S_mco1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_mcos_S_mco1_HASH fXW21upYnb1ZV4bEuBvKCXEcbrABE4XfjXq4dwS7rfY

/* Node's dependency ordinal: */
#define DT_N_S_mcos_S_mco1_ORD 52
#define DT_N_S_mcos_S_mco1_ORD_STR_SORTABLE 00052

/* Ordinals for what this node depends on directly: */
#define DT_N_S_mcos_S_mco1_REQUIRES_ORDS \
	51, /* /mcos */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_mcos_S_mco1_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_mcos_S_mco1_IDX_0_C_TOKEN mco1

/* Existence and alternate IDs: */
#define DT_N_S_mcos_S_mco1_EXISTS 1
#define DT_N_INST_0_st_stm32_clock_mco DT_N_S_mcos_S_mco1
#define DT_N_NODELABEL_mco1            DT_N_S_mcos_S_mco1

/* Macros for properties that are special in the specification: */
#define DT_N_S_mcos_S_mco1_REG_NUM 0
#define DT_N_S_mcos_S_mco1_FOREACH_REG(fn) 
#define DT_N_S_mcos_S_mco1_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_mcos_S_mco1_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_mcos_S_mco1_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_mcos_S_mco1_RANGES_NUM 0
#define DT_N_S_mcos_S_mco1_FOREACH_RANGE(fn) 
#define DT_N_S_mcos_S_mco1_IRQ_NUM 0
#define DT_N_S_mcos_S_mco1_IRQ_LEVEL 0
#define DT_N_S_mcos_S_mco1_COMPAT_MATCHES_st_stm32_clock_mco 1
#define DT_N_S_mcos_S_mco1_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_mcos_S_mco1_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_mcos_S_mco1_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_mcos_S_mco1_COMPAT_MODEL_IDX_0 "stm32-clock-mco"
#define DT_N_S_mcos_S_mco1_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_mcos_S_mco1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_mcos_S_mco1_P_clock_names {"clksel"}
#define DT_N_S_mcos_S_mco1_P_clock_names_IDX_0_ENUM_IDX 0
#define DT_N_S_mcos_S_mco1_P_clock_names_IDX_0_EXISTS 1
#define DT_N_S_mcos_S_mco1_P_clock_names_IDX_0_ENUM_VAL_clksel_EXISTS 1
#define DT_N_S_mcos_S_mco1_P_clock_names_ENUM_VAL_clksel_EXISTS 1
#define DT_N_S_mcos_S_mco1_P_clock_names_IDX_0 "clksel"
#define DT_N_S_mcos_S_mco1_P_clock_names_IDX_0_STRING_UNQUOTED clksel
#define DT_N_S_mcos_S_mco1_P_clock_names_IDX_0_STRING_TOKEN clksel
#define DT_N_S_mcos_S_mco1_P_clock_names_IDX_0_STRING_UPPER_TOKEN CLKSEL
#define DT_N_S_mcos_S_mco1_P_clock_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mcos_S_mco1, clock_names, 0)
#define DT_N_S_mcos_S_mco1_P_clock_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mcos_S_mco1, clock_names, 0)
#define DT_N_S_mcos_S_mco1_P_clock_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mcos_S_mco1, clock_names, 0, __VA_ARGS__)
#define DT_N_S_mcos_S_mco1_P_clock_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mcos_S_mco1, clock_names, 0, __VA_ARGS__)
#define DT_N_S_mcos_S_mco1_P_clock_names_LEN 1
#define DT_N_S_mcos_S_mco1_P_clock_names_EXISTS 1
#define DT_N_S_mcos_S_mco1_P_status "disabled"
#define DT_N_S_mcos_S_mco1_P_status_STRING_UNQUOTED disabled
#define DT_N_S_mcos_S_mco1_P_status_STRING_TOKEN disabled
#define DT_N_S_mcos_S_mco1_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_mcos_S_mco1_P_status_IDX_0 "disabled"
#define DT_N_S_mcos_S_mco1_P_status_IDX_0_EXISTS 1
#define DT_N_S_mcos_S_mco1_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_mcos_S_mco1_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_mcos_S_mco1_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_mcos_S_mco1_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mcos_S_mco1, status, 0)
#define DT_N_S_mcos_S_mco1_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mcos_S_mco1, status, 0)
#define DT_N_S_mcos_S_mco1_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mcos_S_mco1, status, 0, __VA_ARGS__)
#define DT_N_S_mcos_S_mco1_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mcos_S_mco1, status, 0, __VA_ARGS__)
#define DT_N_S_mcos_S_mco1_P_status_LEN 1
#define DT_N_S_mcos_S_mco1_P_status_EXISTS 1
#define DT_N_S_mcos_S_mco1_P_compatible {"st,stm32-clock-mco"}
#define DT_N_S_mcos_S_mco1_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_mcos_S_mco1_P_compatible_IDX_0 "st,stm32-clock-mco"
#define DT_N_S_mcos_S_mco1_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-clock-mco
#define DT_N_S_mcos_S_mco1_P_compatible_IDX_0_STRING_TOKEN st_stm32_clock_mco
#define DT_N_S_mcos_S_mco1_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_CLOCK_MCO
#define DT_N_S_mcos_S_mco1_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mcos_S_mco1, compatible, 0)
#define DT_N_S_mcos_S_mco1_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mcos_S_mco1, compatible, 0)
#define DT_N_S_mcos_S_mco1_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mcos_S_mco1, compatible, 0, __VA_ARGS__)
#define DT_N_S_mcos_S_mco1_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mcos_S_mco1, compatible, 0, __VA_ARGS__)
#define DT_N_S_mcos_S_mco1_P_compatible_LEN 1
#define DT_N_S_mcos_S_mco1_P_compatible_EXISTS 1
#define DT_N_S_mcos_S_mco1_P_dma_coherent 0
#define DT_N_S_mcos_S_mco1_P_dma_coherent_EXISTS 1
#define DT_N_S_mcos_S_mco1_P_zephyr_deferred_init 0
#define DT_N_S_mcos_S_mco1_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_mcos_S_mco1_P_wakeup_source 0
#define DT_N_S_mcos_S_mco1_P_wakeup_source_EXISTS 1
#define DT_N_S_mcos_S_mco1_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_mcos_S_mco1_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /mcos/mco2
 *
 * Node identifier: DT_N_S_mcos_S_mco2
 *
 * Binding (compatible = st,stm32-clock-mco):
 *   $ZEPHYR_BASE\dts\bindings\clock\st,stm32-clock-mco.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_mcos_S_mco2_PATH "/mcos/mco2"

/* Node's name with unit-address: */
#define DT_N_S_mcos_S_mco2_FULL_NAME "mco2"
#define DT_N_S_mcos_S_mco2_FULL_NAME_UNQUOTED mco2
#define DT_N_S_mcos_S_mco2_FULL_NAME_TOKEN mco2
#define DT_N_S_mcos_S_mco2_FULL_NAME_UPPER_TOKEN MCO2

/* Node parent (/mcos) identifier: */
#define DT_N_S_mcos_S_mco2_PARENT DT_N_S_mcos

/* Node's index in its parent's list of children: */
#define DT_N_S_mcos_S_mco2_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_mcos_S_mco2_NODELABEL_NUM 1
#define DT_N_S_mcos_S_mco2_FOREACH_NODELABEL(fn) fn(mco2)
#define DT_N_S_mcos_S_mco2_FOREACH_NODELABEL_VARGS(fn, ...) fn(mco2, __VA_ARGS__)
#define DT_N_S_mcos_S_mco2_FOREACH_ANCESTOR(fn) fn(DT_N_S_mcos) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_mcos_S_mco2_CHILD_NUM 0
#define DT_N_S_mcos_S_mco2_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_mcos_S_mco2_FOREACH_CHILD(fn) 
#define DT_N_S_mcos_S_mco2_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_mcos_S_mco2_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_mcos_S_mco2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_mcos_S_mco2_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_mcos_S_mco2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_mcos_S_mco2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_mcos_S_mco2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_mcos_S_mco2_HASH irDa5qZM1apmLNBL8AyfbwMybA8MLSxOkE_OVqE7xC0

/* Node's dependency ordinal: */
#define DT_N_S_mcos_S_mco2_ORD 53
#define DT_N_S_mcos_S_mco2_ORD_STR_SORTABLE 00053

/* Ordinals for what this node depends on directly: */
#define DT_N_S_mcos_S_mco2_REQUIRES_ORDS \
	51, /* /mcos */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_mcos_S_mco2_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_mcos_S_mco2_IDX_0_C_TOKEN mco2

/* Existence and alternate IDs: */
#define DT_N_S_mcos_S_mco2_EXISTS 1
#define DT_N_INST_1_st_stm32_clock_mco DT_N_S_mcos_S_mco2
#define DT_N_NODELABEL_mco2            DT_N_S_mcos_S_mco2

/* Macros for properties that are special in the specification: */
#define DT_N_S_mcos_S_mco2_REG_NUM 0
#define DT_N_S_mcos_S_mco2_FOREACH_REG(fn) 
#define DT_N_S_mcos_S_mco2_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_mcos_S_mco2_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_mcos_S_mco2_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_mcos_S_mco2_RANGES_NUM 0
#define DT_N_S_mcos_S_mco2_FOREACH_RANGE(fn) 
#define DT_N_S_mcos_S_mco2_IRQ_NUM 0
#define DT_N_S_mcos_S_mco2_IRQ_LEVEL 0
#define DT_N_S_mcos_S_mco2_COMPAT_MATCHES_st_stm32_clock_mco 1
#define DT_N_S_mcos_S_mco2_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_mcos_S_mco2_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_mcos_S_mco2_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_mcos_S_mco2_COMPAT_MODEL_IDX_0 "stm32-clock-mco"
#define DT_N_S_mcos_S_mco2_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_mcos_S_mco2_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_mcos_S_mco2_P_clock_names {"clksel"}
#define DT_N_S_mcos_S_mco2_P_clock_names_IDX_0_ENUM_IDX 0
#define DT_N_S_mcos_S_mco2_P_clock_names_IDX_0_EXISTS 1
#define DT_N_S_mcos_S_mco2_P_clock_names_IDX_0_ENUM_VAL_clksel_EXISTS 1
#define DT_N_S_mcos_S_mco2_P_clock_names_ENUM_VAL_clksel_EXISTS 1
#define DT_N_S_mcos_S_mco2_P_clock_names_IDX_0 "clksel"
#define DT_N_S_mcos_S_mco2_P_clock_names_IDX_0_STRING_UNQUOTED clksel
#define DT_N_S_mcos_S_mco2_P_clock_names_IDX_0_STRING_TOKEN clksel
#define DT_N_S_mcos_S_mco2_P_clock_names_IDX_0_STRING_UPPER_TOKEN CLKSEL
#define DT_N_S_mcos_S_mco2_P_clock_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mcos_S_mco2, clock_names, 0)
#define DT_N_S_mcos_S_mco2_P_clock_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mcos_S_mco2, clock_names, 0)
#define DT_N_S_mcos_S_mco2_P_clock_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mcos_S_mco2, clock_names, 0, __VA_ARGS__)
#define DT_N_S_mcos_S_mco2_P_clock_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mcos_S_mco2, clock_names, 0, __VA_ARGS__)
#define DT_N_S_mcos_S_mco2_P_clock_names_LEN 1
#define DT_N_S_mcos_S_mco2_P_clock_names_EXISTS 1
#define DT_N_S_mcos_S_mco2_P_status "disabled"
#define DT_N_S_mcos_S_mco2_P_status_STRING_UNQUOTED disabled
#define DT_N_S_mcos_S_mco2_P_status_STRING_TOKEN disabled
#define DT_N_S_mcos_S_mco2_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_mcos_S_mco2_P_status_IDX_0 "disabled"
#define DT_N_S_mcos_S_mco2_P_status_IDX_0_EXISTS 1
#define DT_N_S_mcos_S_mco2_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_mcos_S_mco2_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_mcos_S_mco2_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_mcos_S_mco2_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mcos_S_mco2, status, 0)
#define DT_N_S_mcos_S_mco2_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mcos_S_mco2, status, 0)
#define DT_N_S_mcos_S_mco2_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mcos_S_mco2, status, 0, __VA_ARGS__)
#define DT_N_S_mcos_S_mco2_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mcos_S_mco2, status, 0, __VA_ARGS__)
#define DT_N_S_mcos_S_mco2_P_status_LEN 1
#define DT_N_S_mcos_S_mco2_P_status_EXISTS 1
#define DT_N_S_mcos_S_mco2_P_compatible {"st,stm32-clock-mco"}
#define DT_N_S_mcos_S_mco2_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_mcos_S_mco2_P_compatible_IDX_0 "st,stm32-clock-mco"
#define DT_N_S_mcos_S_mco2_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-clock-mco
#define DT_N_S_mcos_S_mco2_P_compatible_IDX_0_STRING_TOKEN st_stm32_clock_mco
#define DT_N_S_mcos_S_mco2_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_CLOCK_MCO
#define DT_N_S_mcos_S_mco2_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mcos_S_mco2, compatible, 0)
#define DT_N_S_mcos_S_mco2_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mcos_S_mco2, compatible, 0)
#define DT_N_S_mcos_S_mco2_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mcos_S_mco2, compatible, 0, __VA_ARGS__)
#define DT_N_S_mcos_S_mco2_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mcos_S_mco2, compatible, 0, __VA_ARGS__)
#define DT_N_S_mcos_S_mco2_P_compatible_LEN 1
#define DT_N_S_mcos_S_mco2_P_compatible_EXISTS 1
#define DT_N_S_mcos_S_mco2_P_dma_coherent 0
#define DT_N_S_mcos_S_mco2_P_dma_coherent_EXISTS 1
#define DT_N_S_mcos_S_mco2_P_zephyr_deferred_init 0
#define DT_N_S_mcos_S_mco2_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_mcos_S_mco2_P_wakeup_source 0
#define DT_N_S_mcos_S_mco2_P_wakeup_source_EXISTS 1
#define DT_N_S_mcos_S_mco2_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_mcos_S_mco2_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/gpio@40020000
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000
 *
 * Binding (compatible = st,stm32-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\st,stm32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_PATH "/soc/pin-controller@40020000/gpio@40020000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FULL_NAME "gpio@40020000"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FULL_NAME_UNQUOTED gpio@40020000
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FULL_NAME_TOKEN gpio_40020000
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FULL_NAME_UPPER_TOKEN GPIO_40020000

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FOREACH_NODELABEL(fn) fn(gpioa)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpioa, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_HASH P0cLvJju4eewDxVsIQNhAexO3B7UusUgY4KkiA6lSow

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_ORD 54
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_ORD_STR_SORTABLE 00054

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_REQUIRES_ORDS \
	9, /* /soc/rcc@40023800 */ \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_SUPPORTS_ORDS \
	55, /* /power@40007000 */ \
	56, /* /power@40007000/wkup-pin@1 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_IDX_0_C_TOKEN gpioa

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_EXISTS 1
#define DT_N_INST_0_st_stm32_gpio DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000
#define DT_N_NODELABEL_gpioa      DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_REG_IDX_0_VAL_ADDRESS 1073872896 /* 0x40020000 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_COMPAT_MATCHES_st_stm32_gpio 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_COMPAT_MODEL_IDX_0 "stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_reg {1073872896 /* 0x40020000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_reg_IDX_0 1073872896
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_clocks_IDX_0_VAL_bus 48
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_clocks_IDX_0_VAL_bits 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_clocks_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_ngpios 16
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_gpio_controller 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_compatible {"st,stm32-gpio"}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_compatible_IDX_0 "st,stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /power@40007000
 *
 * Node identifier: DT_N_S_power_40007000
 *
 * Binding (compatible = st,stm32-pwr):
 *   $ZEPHYR_BASE\dts\bindings\power\st,stm32-pwr.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_power_40007000_PATH "/power@40007000"

/* Node's name with unit-address: */
#define DT_N_S_power_40007000_FULL_NAME "power@40007000"
#define DT_N_S_power_40007000_FULL_NAME_UNQUOTED power@40007000
#define DT_N_S_power_40007000_FULL_NAME_TOKEN power_40007000
#define DT_N_S_power_40007000_FULL_NAME_UPPER_TOKEN POWER_40007000

/* Node parent (/) identifier: */
#define DT_N_S_power_40007000_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_power_40007000_CHILD_IDX 7

/* Helpers for dealing with node labels: */
#define DT_N_S_power_40007000_NODELABEL_NUM 1
#define DT_N_S_power_40007000_FOREACH_NODELABEL(fn) fn(pwr)
#define DT_N_S_power_40007000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwr, __VA_ARGS__)
#define DT_N_S_power_40007000_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_power_40007000_CHILD_NUM 1
#define DT_N_S_power_40007000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_power_40007000_CHILD_UNIT_ADDR_INT_1 DT_N_S_power_40007000_S_wkup_pin_1
#define DT_N_S_power_40007000_FOREACH_CHILD(fn) fn(DT_N_S_power_40007000_S_wkup_pin_1)
#define DT_N_S_power_40007000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_power_40007000_S_wkup_pin_1)
#define DT_N_S_power_40007000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_power_40007000_S_wkup_pin_1, __VA_ARGS__)
#define DT_N_S_power_40007000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_power_40007000_S_wkup_pin_1, __VA_ARGS__)
#define DT_N_S_power_40007000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_power_40007000_S_wkup_pin_1)
#define DT_N_S_power_40007000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_power_40007000_S_wkup_pin_1)
#define DT_N_S_power_40007000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_power_40007000_S_wkup_pin_1, __VA_ARGS__)
#define DT_N_S_power_40007000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_power_40007000_S_wkup_pin_1, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_power_40007000_HASH ApvxhmhUbwGCc5BcrKCWBdPiZnaFEfb6b6OpZuT1v7g

/* Node's dependency ordinal: */
#define DT_N_S_power_40007000_ORD 55
#define DT_N_S_power_40007000_ORD_STR_SORTABLE 00055

/* Ordinals for what this node depends on directly: */
#define DT_N_S_power_40007000_REQUIRES_ORDS \
	0, /* / */ \
	54, /* /soc/pin-controller@40020000/gpio@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_power_40007000_SUPPORTS_ORDS \
	56, /* /power@40007000/wkup-pin@1 */
#define DT_N_NODELABEL_DT_N_S_power_40007000_IDX_0_C_TOKEN pwr

/* Existence and alternate IDs: */
#define DT_N_S_power_40007000_EXISTS 1
#define DT_N_INST_0_st_stm32_pwr DT_N_S_power_40007000
#define DT_N_NODELABEL_pwr       DT_N_S_power_40007000

/* Macros for properties that are special in the specification: */
#define DT_N_S_power_40007000_REG_NUM 1
#define DT_N_S_power_40007000_REG_IDX_0_EXISTS 1
#define DT_N_S_power_40007000_REG_IDX_0_VAL_ADDRESS 1073770496 /* 0x40007000 */
#define DT_N_S_power_40007000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_power_40007000_FOREACH_REG(fn) fn(DT_N_S_power_40007000, 0)
#define DT_N_S_power_40007000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_power_40007000, 0)
#define DT_N_S_power_40007000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_power_40007000, 0, __VA_ARGS__)
#define DT_N_S_power_40007000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_power_40007000, 0, __VA_ARGS__)
#define DT_N_S_power_40007000_RANGES_NUM 0
#define DT_N_S_power_40007000_FOREACH_RANGE(fn) 
#define DT_N_S_power_40007000_IRQ_NUM 0
#define DT_N_S_power_40007000_IRQ_LEVEL 0
#define DT_N_S_power_40007000_COMPAT_MATCHES_st_stm32_pwr 1
#define DT_N_S_power_40007000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_power_40007000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_power_40007000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_power_40007000_COMPAT_MODEL_IDX_0 "stm32-pwr"
#define DT_N_S_power_40007000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_power_40007000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_power_40007000_P_reg {1073770496 /* 0x40007000 */, 1024 /* 0x400 */}
#define DT_N_S_power_40007000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_power_40007000_P_reg_IDX_0 1073770496
#define DT_N_S_power_40007000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_power_40007000_P_reg_IDX_1 1024
#define DT_N_S_power_40007000_P_reg_EXISTS 1
#define DT_N_S_power_40007000_P_wkup_pins_nb 1
#define DT_N_S_power_40007000_P_wkup_pins_nb_EXISTS 1
#define DT_N_S_power_40007000_P_wkup_pins_pol 0
#define DT_N_S_power_40007000_P_wkup_pins_pol_EXISTS 1
#define DT_N_S_power_40007000_P_wkup_pins_pupd 0
#define DT_N_S_power_40007000_P_wkup_pins_pupd_EXISTS 1
#define DT_N_S_power_40007000_P_status "disabled"
#define DT_N_S_power_40007000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_power_40007000_P_status_STRING_TOKEN disabled
#define DT_N_S_power_40007000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_power_40007000_P_status_IDX_0 "disabled"
#define DT_N_S_power_40007000_P_status_IDX_0_EXISTS 1
#define DT_N_S_power_40007000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_power_40007000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_power_40007000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_power_40007000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_power_40007000, status, 0)
#define DT_N_S_power_40007000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_power_40007000, status, 0)
#define DT_N_S_power_40007000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_power_40007000, status, 0, __VA_ARGS__)
#define DT_N_S_power_40007000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_power_40007000, status, 0, __VA_ARGS__)
#define DT_N_S_power_40007000_P_status_LEN 1
#define DT_N_S_power_40007000_P_status_EXISTS 1
#define DT_N_S_power_40007000_P_compatible {"st,stm32-pwr"}
#define DT_N_S_power_40007000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_power_40007000_P_compatible_IDX_0 "st,stm32-pwr"
#define DT_N_S_power_40007000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwr
#define DT_N_S_power_40007000_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwr
#define DT_N_S_power_40007000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWR
#define DT_N_S_power_40007000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_power_40007000, compatible, 0)
#define DT_N_S_power_40007000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_power_40007000, compatible, 0)
#define DT_N_S_power_40007000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_power_40007000, compatible, 0, __VA_ARGS__)
#define DT_N_S_power_40007000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_power_40007000, compatible, 0, __VA_ARGS__)
#define DT_N_S_power_40007000_P_compatible_LEN 1
#define DT_N_S_power_40007000_P_compatible_EXISTS 1
#define DT_N_S_power_40007000_P_dma_coherent 0
#define DT_N_S_power_40007000_P_dma_coherent_EXISTS 1
#define DT_N_S_power_40007000_P_zephyr_deferred_init 0
#define DT_N_S_power_40007000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_power_40007000_P_wakeup_source 0
#define DT_N_S_power_40007000_P_wakeup_source_EXISTS 1
#define DT_N_S_power_40007000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_power_40007000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /power@40007000/wkup-pin@1
 *
 * Node identifier: DT_N_S_power_40007000_S_wkup_pin_1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_power_40007000_S_wkup_pin_1_PATH "/power@40007000/wkup-pin@1"

/* Node's name with unit-address: */
#define DT_N_S_power_40007000_S_wkup_pin_1_FULL_NAME "wkup-pin@1"
#define DT_N_S_power_40007000_S_wkup_pin_1_FULL_NAME_UNQUOTED wkup-pin@1
#define DT_N_S_power_40007000_S_wkup_pin_1_FULL_NAME_TOKEN wkup_pin_1
#define DT_N_S_power_40007000_S_wkup_pin_1_FULL_NAME_UPPER_TOKEN WKUP_PIN_1

/* Node parent (/power@40007000) identifier: */
#define DT_N_S_power_40007000_S_wkup_pin_1_PARENT DT_N_S_power_40007000

/* Node's index in its parent's list of children: */
#define DT_N_S_power_40007000_S_wkup_pin_1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_power_40007000_S_wkup_pin_1_NODELABEL_NUM 0
#define DT_N_S_power_40007000_S_wkup_pin_1_FOREACH_NODELABEL(fn) 
#define DT_N_S_power_40007000_S_wkup_pin_1_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_power_40007000_S_wkup_pin_1_FOREACH_ANCESTOR(fn) fn(DT_N_S_power_40007000) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_power_40007000_S_wkup_pin_1_CHILD_NUM 0
#define DT_N_S_power_40007000_S_wkup_pin_1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_power_40007000_S_wkup_pin_1_FOREACH_CHILD(fn) 
#define DT_N_S_power_40007000_S_wkup_pin_1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_power_40007000_S_wkup_pin_1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_power_40007000_S_wkup_pin_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_power_40007000_S_wkup_pin_1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_power_40007000_S_wkup_pin_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_power_40007000_S_wkup_pin_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_power_40007000_S_wkup_pin_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_power_40007000_S_wkup_pin_1_HASH f6o5SzvImsRBOENsjzGMOdwz0FHtupEOt6tBmk8_pNE

/* Node's dependency ordinal: */
#define DT_N_S_power_40007000_S_wkup_pin_1_ORD 56
#define DT_N_S_power_40007000_S_wkup_pin_1_ORD_STR_SORTABLE 00056

/* Ordinals for what this node depends on directly: */
#define DT_N_S_power_40007000_S_wkup_pin_1_REQUIRES_ORDS \
	54, /* /soc/pin-controller@40020000/gpio@40020000 */ \
	55, /* /power@40007000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_power_40007000_S_wkup_pin_1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_power_40007000_S_wkup_pin_1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_power_40007000_S_wkup_pin_1_REG_NUM 1
#define DT_N_S_power_40007000_S_wkup_pin_1_REG_IDX_0_EXISTS 1
#define DT_N_S_power_40007000_S_wkup_pin_1_REG_IDX_0_VAL_ADDRESS 1 /* 0x1 */
#define DT_N_S_power_40007000_S_wkup_pin_1_FOREACH_REG(fn) fn(DT_N_S_power_40007000_S_wkup_pin_1, 0)
#define DT_N_S_power_40007000_S_wkup_pin_1_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_power_40007000_S_wkup_pin_1, 0)
#define DT_N_S_power_40007000_S_wkup_pin_1_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_power_40007000_S_wkup_pin_1, 0, __VA_ARGS__)
#define DT_N_S_power_40007000_S_wkup_pin_1_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_power_40007000_S_wkup_pin_1, 0, __VA_ARGS__)
#define DT_N_S_power_40007000_S_wkup_pin_1_RANGES_NUM 0
#define DT_N_S_power_40007000_S_wkup_pin_1_FOREACH_RANGE(fn) 
#define DT_N_S_power_40007000_S_wkup_pin_1_IRQ_NUM 0
#define DT_N_S_power_40007000_S_wkup_pin_1_IRQ_LEVEL 0
#define DT_N_S_power_40007000_S_wkup_pin_1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_power_40007000_S_wkup_pin_1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_power_40007000_S_wkup_pin_1_P_reg {1 /* 0x1 */}
#define DT_N_S_power_40007000_S_wkup_pin_1_P_reg_IDX_0_EXISTS 1
#define DT_N_S_power_40007000_S_wkup_pin_1_P_reg_IDX_0 1
#define DT_N_S_power_40007000_S_wkup_pin_1_P_reg_EXISTS 1
#define DT_N_S_power_40007000_S_wkup_pin_1_P_wkup_gpios_IDX_0_EXISTS 1
#define DT_N_S_power_40007000_S_wkup_pin_1_P_wkup_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000
#define DT_N_S_power_40007000_S_wkup_pin_1_P_wkup_gpios_IDX_0_VAL_pin 0
#define DT_N_S_power_40007000_S_wkup_pin_1_P_wkup_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_power_40007000_S_wkup_pin_1_P_wkup_gpios_IDX_0_VAL_flags 1
#define DT_N_S_power_40007000_S_wkup_pin_1_P_wkup_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_power_40007000_S_wkup_pin_1_P_wkup_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_power_40007000_S_wkup_pin_1, wkup_gpios, 0, pin) \
	fn(DT_N_S_power_40007000_S_wkup_pin_1, wkup_gpios, 0, flags)
#define DT_N_S_power_40007000_S_wkup_pin_1_P_wkup_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_power_40007000_S_wkup_pin_1, wkup_gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_power_40007000_S_wkup_pin_1, wkup_gpios, 0, flags)
#define DT_N_S_power_40007000_S_wkup_pin_1_P_wkup_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_power_40007000_S_wkup_pin_1_P_wkup_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_power_40007000_S_wkup_pin_1, wkup_gpios, 0)
#define DT_N_S_power_40007000_S_wkup_pin_1_P_wkup_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_power_40007000_S_wkup_pin_1, wkup_gpios, 0)
#define DT_N_S_power_40007000_S_wkup_pin_1_P_wkup_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_power_40007000_S_wkup_pin_1, wkup_gpios, 0, __VA_ARGS__)
#define DT_N_S_power_40007000_S_wkup_pin_1_P_wkup_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_power_40007000_S_wkup_pin_1, wkup_gpios, 0, __VA_ARGS__)
#define DT_N_S_power_40007000_S_wkup_pin_1_P_wkup_gpios_LEN 1
#define DT_N_S_power_40007000_S_wkup_pin_1_P_wkup_gpios_EXISTS 1

/*
 * Devicetree node: /soc/adc@40012100
 *
 * Node identifier: DT_N_S_soc_S_adc_40012100
 *
 * Binding (compatible = st,stm32f4-adc):
 *   $ZEPHYR_BASE\dts\bindings\adc\st,stm32f4-adc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_adc_40012100_PATH "/soc/adc@40012100"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_adc_40012100_FULL_NAME "adc@40012100"
#define DT_N_S_soc_S_adc_40012100_FULL_NAME_UNQUOTED adc@40012100
#define DT_N_S_soc_S_adc_40012100_FULL_NAME_TOKEN adc_40012100
#define DT_N_S_soc_S_adc_40012100_FULL_NAME_UPPER_TOKEN ADC_40012100

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_adc_40012100_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_adc_40012100_CHILD_IDX 48

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_adc_40012100_NODELABEL_NUM 1
#define DT_N_S_soc_S_adc_40012100_FOREACH_NODELABEL(fn) fn(adc2)
#define DT_N_S_soc_S_adc_40012100_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc2, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_adc_40012100_CHILD_NUM 0
#define DT_N_S_soc_S_adc_40012100_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_adc_40012100_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_adc_40012100_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_adc_40012100_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_adc_40012100_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_adc_40012100_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_adc_40012100_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_adc_40012100_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_adc_40012100_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_adc_40012100_HASH SjSaDQ7zaVOKEBMaoQfd9Nvj_nVrGQh0tq0a6V2sQP0

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_adc_40012100_ORD 57
#define DT_N_S_soc_S_adc_40012100_ORD_STR_SORTABLE 00057

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_adc_40012100_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_adc_40012100_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_adc_40012100_IDX_0_C_TOKEN adc2

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_adc_40012100_EXISTS 1
#define DT_N_INST_1_st_stm32f4_adc DT_N_S_soc_S_adc_40012100
#define DT_N_INST_1_st_stm32_adc   DT_N_S_soc_S_adc_40012100
#define DT_N_NODELABEL_adc2        DT_N_S_soc_S_adc_40012100

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_adc_40012100_REG_NUM 1
#define DT_N_S_soc_S_adc_40012100_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_REG_IDX_0_VAL_ADDRESS 1073815808 /* 0x40012100 */
#define DT_N_S_soc_S_adc_40012100_REG_IDX_0_VAL_SIZE 80 /* 0x50 */
#define DT_N_S_soc_S_adc_40012100_FOREACH_REG(fn) fn(DT_N_S_soc_S_adc_40012100, 0)
#define DT_N_S_soc_S_adc_40012100_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012100, 0)
#define DT_N_S_soc_S_adc_40012100_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012100, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012100, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_RANGES_NUM 0
#define DT_N_S_soc_S_adc_40012100_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_adc_40012100_IRQ_NUM 1
#define DT_N_S_soc_S_adc_40012100_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_IRQ_IDX_0_VAL_irq 18
#define DT_N_S_soc_S_adc_40012100_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_adc_40012100_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_adc_40012100_IRQ_LEVEL 1
#define DT_N_S_soc_S_adc_40012100_COMPAT_MATCHES_st_stm32f4_adc 1
#define DT_N_S_soc_S_adc_40012100_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_adc_40012100_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_COMPAT_MODEL_IDX_0 "stm32f4-adc"
#define DT_N_S_soc_S_adc_40012100_COMPAT_MATCHES_st_stm32_adc 1
#define DT_N_S_soc_S_adc_40012100_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_adc_40012100_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_COMPAT_MODEL_IDX_1 "stm32-adc"
#define DT_N_S_soc_S_adc_40012100_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_adc_40012100_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_adc_40012100_P_reg {1073815808 /* 0x40012100 */, 80 /* 0x50 */}
#define DT_N_S_soc_S_adc_40012100_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_reg_IDX_0 1073815808
#define DT_N_S_soc_S_adc_40012100_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_reg_IDX_1 80
#define DT_N_S_soc_S_adc_40012100_P_reg_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_adc_40012100_P_clocks_IDX_0_VAL_bus 68
#define DT_N_S_soc_S_adc_40012100_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_clocks_IDX_0_VAL_bits 512
#define DT_N_S_soc_S_adc_40012100_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_adc_40012100, clocks, 0, bus) \
	fn(DT_N_S_soc_S_adc_40012100, clocks, 0, bits)
#define DT_N_S_soc_S_adc_40012100_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012100, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, clocks, 0, bits)
#define DT_N_S_soc_S_adc_40012100_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_adc_40012100_P_clocks_IDX_0_NAME "adcx"
#define DT_N_S_soc_S_adc_40012100_P_clocks_NAME_adcx_IDX 0
#define DT_N_S_soc_S_adc_40012100_P_clocks_NAME_adcx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_adc_40012100, clocks, adcx, bus) \
	fn(DT_N_S_soc_S_adc_40012100, clocks, adcx, bits)
#define DT_N_S_soc_S_adc_40012100_P_clocks_NAME_adcx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012100, clocks, adcx, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, clocks, adcx, bits)
#define DT_N_S_soc_S_adc_40012100_P_clocks_NAME_adcx_NUM_CELLS 2
#define DT_N_S_soc_S_adc_40012100_P_clocks_NAME_adcx_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_adc_40012100_P_clocks_NAME_adcx_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_clocks_NAME_adcx_VAL_bus DT_N_S_soc_S_adc_40012100_P_clocks_IDX_0_VAL_bus
#define DT_N_S_soc_S_adc_40012100_P_clocks_NAME_adcx_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_clocks_NAME_adcx_VAL_bits DT_N_S_soc_S_adc_40012100_P_clocks_IDX_0_VAL_bits
#define DT_N_S_soc_S_adc_40012100_P_clocks_NAME_adcx_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012100, clocks, 0)
#define DT_N_S_soc_S_adc_40012100_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012100, clocks, 0)
#define DT_N_S_soc_S_adc_40012100_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012100, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012100, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_clocks_LEN 1
#define DT_N_S_soc_S_adc_40012100_P_clocks_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_clock_names {"adcx"}
#define DT_N_S_soc_S_adc_40012100_P_clock_names_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_adc_40012100_P_clock_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_clock_names_IDX_0_ENUM_VAL_adcx_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_clock_names_ENUM_VAL_adcx_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_clock_names_IDX_0 "adcx"
#define DT_N_S_soc_S_adc_40012100_P_clock_names_IDX_0_STRING_UNQUOTED adcx
#define DT_N_S_soc_S_adc_40012100_P_clock_names_IDX_0_STRING_TOKEN adcx
#define DT_N_S_soc_S_adc_40012100_P_clock_names_IDX_0_STRING_UPPER_TOKEN ADCX
#define DT_N_S_soc_S_adc_40012100_P_clock_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012100, clock_names, 0)
#define DT_N_S_soc_S_adc_40012100_P_clock_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012100, clock_names, 0)
#define DT_N_S_soc_S_adc_40012100_P_clock_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012100, clock_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_clock_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012100, clock_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_clock_names_LEN 1
#define DT_N_S_soc_S_adc_40012100_P_clock_names_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_interrupts {18 /* 0x12 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_adc_40012100_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_interrupts_IDX_0 18
#define DT_N_S_soc_S_adc_40012100_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_adc_40012100_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_clock_source "SYNC"
#define DT_N_S_soc_S_adc_40012100_P_st_adc_clock_source_STRING_UNQUOTED SYNC
#define DT_N_S_soc_S_adc_40012100_P_st_adc_clock_source_STRING_TOKEN SYNC
#define DT_N_S_soc_S_adc_40012100_P_st_adc_clock_source_STRING_UPPER_TOKEN SYNC
#define DT_N_S_soc_S_adc_40012100_P_st_adc_clock_source_IDX_0 "SYNC"
#define DT_N_S_soc_S_adc_40012100_P_st_adc_clock_source_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_clock_source_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_adc_40012100_P_st_adc_clock_source_IDX_0_ENUM_VAL_sync_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_clock_source_ENUM_VAL_sync_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_clock_source_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012100, st_adc_clock_source, 0)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_clock_source_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012100, st_adc_clock_source, 0)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012100, st_adc_clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_clock_source_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012100, st_adc_clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_clock_source_LEN 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_clock_source_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_vref_mv 3300
#define DT_N_S_soc_S_adc_40012100_P_vref_mv_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_resolutions {12 /* 0xc */, 10 /* 0xa */, 8 /* 0x8 */, 6 /* 0x6 */}
#define DT_N_S_soc_S_adc_40012100_P_st_adc_resolutions_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_resolutions_IDX_0 12
#define DT_N_S_soc_S_adc_40012100_P_st_adc_resolutions_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_resolutions_IDX_1 10
#define DT_N_S_soc_S_adc_40012100_P_st_adc_resolutions_IDX_2_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_resolutions_IDX_2 8
#define DT_N_S_soc_S_adc_40012100_P_st_adc_resolutions_IDX_3_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_resolutions_IDX_3 6
#define DT_N_S_soc_S_adc_40012100_P_st_adc_resolutions_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012100, st_adc_resolutions, 0) \
	fn(DT_N_S_soc_S_adc_40012100, st_adc_resolutions, 1) \
	fn(DT_N_S_soc_S_adc_40012100, st_adc_resolutions, 2) \
	fn(DT_N_S_soc_S_adc_40012100, st_adc_resolutions, 3)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_resolutions_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012100, st_adc_resolutions, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, st_adc_resolutions, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, st_adc_resolutions, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, st_adc_resolutions, 3)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_resolutions_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012100, st_adc_resolutions, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012100, st_adc_resolutions, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012100, st_adc_resolutions, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012100, st_adc_resolutions, 3, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_resolutions_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012100, st_adc_resolutions, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, st_adc_resolutions, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, st_adc_resolutions, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, st_adc_resolutions, 3, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_resolutions_LEN 4
#define DT_N_S_soc_S_adc_40012100_P_st_adc_resolutions_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_sampling_times {3 /* 0x3 */, 15 /* 0xf */, 28 /* 0x1c */, 56 /* 0x38 */, 84 /* 0x54 */, 112 /* 0x70 */, 144 /* 0x90 */, 480 /* 0x1e0 */}
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_IDX_0 3
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_IDX_1 15
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_IDX_2_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_IDX_2 28
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_IDX_3_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_IDX_3 56
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_IDX_4_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_IDX_4 84
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_IDX_5_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_IDX_5 112
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_IDX_6_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_IDX_6 144
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_IDX_7_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_IDX_7 480
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012100, sampling_times, 0) \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 1) \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 2) \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 3) \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 4) \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 5) \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 6) \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 7)
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012100, sampling_times, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 7)
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012100, sampling_times, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 7, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012100, sampling_times, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, sampling_times, 7, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_LEN 8
#define DT_N_S_soc_S_adc_40012100_P_sampling_times_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_sequencer "programmable"
#define DT_N_S_soc_S_adc_40012100_P_st_adc_sequencer_STRING_UNQUOTED programmable
#define DT_N_S_soc_S_adc_40012100_P_st_adc_sequencer_STRING_TOKEN programmable
#define DT_N_S_soc_S_adc_40012100_P_st_adc_sequencer_STRING_UPPER_TOKEN PROGRAMMABLE
#define DT_N_S_soc_S_adc_40012100_P_st_adc_sequencer_IDX_0 "programmable"
#define DT_N_S_soc_S_adc_40012100_P_st_adc_sequencer_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_sequencer_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_sequencer_IDX_0_ENUM_VAL_programmable_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_sequencer_ENUM_VAL_programmable_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_sequencer_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012100, st_adc_sequencer, 0)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_sequencer_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012100, st_adc_sequencer, 0)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_sequencer_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012100, st_adc_sequencer, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_sequencer_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012100, st_adc_sequencer, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_sequencer_LEN 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_sequencer_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_oversampler "none"
#define DT_N_S_soc_S_adc_40012100_P_st_adc_oversampler_STRING_UNQUOTED none
#define DT_N_S_soc_S_adc_40012100_P_st_adc_oversampler_STRING_TOKEN none
#define DT_N_S_soc_S_adc_40012100_P_st_adc_oversampler_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_adc_40012100_P_st_adc_oversampler_IDX_0 "none"
#define DT_N_S_soc_S_adc_40012100_P_st_adc_oversampler_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_oversampler_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_adc_40012100_P_st_adc_oversampler_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_oversampler_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_oversampler_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012100, st_adc_oversampler, 0)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_oversampler_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012100, st_adc_oversampler, 0)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_oversampler_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012100, st_adc_oversampler, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_oversampler_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012100, st_adc_oversampler, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_oversampler_LEN 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_oversampler_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_internal_regulator "none"
#define DT_N_S_soc_S_adc_40012100_P_st_adc_internal_regulator_STRING_UNQUOTED none
#define DT_N_S_soc_S_adc_40012100_P_st_adc_internal_regulator_STRING_TOKEN none
#define DT_N_S_soc_S_adc_40012100_P_st_adc_internal_regulator_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_adc_40012100_P_st_adc_internal_regulator_IDX_0 "none"
#define DT_N_S_soc_S_adc_40012100_P_st_adc_internal_regulator_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_internal_regulator_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_adc_40012100_P_st_adc_internal_regulator_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_internal_regulator_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_internal_regulator_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012100, st_adc_internal_regulator, 0)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_internal_regulator_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012100, st_adc_internal_regulator, 0)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_internal_regulator_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012100, st_adc_internal_regulator, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_internal_regulator_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012100, st_adc_internal_regulator, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_st_adc_internal_regulator_LEN 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_internal_regulator_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_has_deep_powerdown 0
#define DT_N_S_soc_S_adc_40012100_P_st_adc_has_deep_powerdown_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_has_channel_preselection 0
#define DT_N_S_soc_S_adc_40012100_P_st_adc_has_channel_preselection_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_has_differential_support 0
#define DT_N_S_soc_S_adc_40012100_P_st_adc_has_differential_support_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_has_injected_support 1
#define DT_N_S_soc_S_adc_40012100_P_st_adc_has_injected_support_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_status "disabled"
#define DT_N_S_soc_S_adc_40012100_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_adc_40012100_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_adc_40012100_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_adc_40012100_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_adc_40012100_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_adc_40012100_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012100, status, 0)
#define DT_N_S_soc_S_adc_40012100_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012100, status, 0)
#define DT_N_S_soc_S_adc_40012100_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012100, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012100, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_status_LEN 1
#define DT_N_S_soc_S_adc_40012100_P_status_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_compatible {"st,stm32f4-adc", "st,stm32-adc"}
#define DT_N_S_soc_S_adc_40012100_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_compatible_IDX_0 "st,stm32f4-adc"
#define DT_N_S_soc_S_adc_40012100_P_compatible_IDX_0_STRING_UNQUOTED st,stm32f4-adc
#define DT_N_S_soc_S_adc_40012100_P_compatible_IDX_0_STRING_TOKEN st_stm32f4_adc
#define DT_N_S_soc_S_adc_40012100_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32F4_ADC
#define DT_N_S_soc_S_adc_40012100_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_compatible_IDX_1 "st,stm32-adc"
#define DT_N_S_soc_S_adc_40012100_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-adc
#define DT_N_S_soc_S_adc_40012100_P_compatible_IDX_1_STRING_TOKEN st_stm32_adc
#define DT_N_S_soc_S_adc_40012100_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_ADC
#define DT_N_S_soc_S_adc_40012100_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012100, compatible, 0) \
	fn(DT_N_S_soc_S_adc_40012100, compatible, 1)
#define DT_N_S_soc_S_adc_40012100_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012100, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, compatible, 1)
#define DT_N_S_soc_S_adc_40012100_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012100, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012100, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012100, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012100, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012100_P_compatible_LEN 2
#define DT_N_S_soc_S_adc_40012100_P_compatible_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_dma_coherent 0
#define DT_N_S_soc_S_adc_40012100_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_adc_40012100_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_wakeup_source 0
#define DT_N_S_soc_S_adc_40012100_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_adc_40012100_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_adc_40012100_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/adc@40012200
 *
 * Node identifier: DT_N_S_soc_S_adc_40012200
 *
 * Binding (compatible = st,stm32f4-adc):
 *   $ZEPHYR_BASE\dts\bindings\adc\st,stm32f4-adc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_adc_40012200_PATH "/soc/adc@40012200"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_adc_40012200_FULL_NAME "adc@40012200"
#define DT_N_S_soc_S_adc_40012200_FULL_NAME_UNQUOTED adc@40012200
#define DT_N_S_soc_S_adc_40012200_FULL_NAME_TOKEN adc_40012200
#define DT_N_S_soc_S_adc_40012200_FULL_NAME_UPPER_TOKEN ADC_40012200

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_adc_40012200_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_adc_40012200_CHILD_IDX 49

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_adc_40012200_NODELABEL_NUM 1
#define DT_N_S_soc_S_adc_40012200_FOREACH_NODELABEL(fn) fn(adc3)
#define DT_N_S_soc_S_adc_40012200_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc3, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_adc_40012200_CHILD_NUM 0
#define DT_N_S_soc_S_adc_40012200_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_adc_40012200_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_adc_40012200_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_adc_40012200_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_adc_40012200_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_adc_40012200_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_adc_40012200_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_adc_40012200_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_adc_40012200_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_adc_40012200_HASH 0s5T8_84n4whbgEXiq2pHz_dqQKIZJugZngDt77LC5g

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_adc_40012200_ORD 58
#define DT_N_S_soc_S_adc_40012200_ORD_STR_SORTABLE 00058

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_adc_40012200_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_adc_40012200_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_adc_40012200_IDX_0_C_TOKEN adc3

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_adc_40012200_EXISTS 1
#define DT_N_INST_2_st_stm32f4_adc DT_N_S_soc_S_adc_40012200
#define DT_N_INST_2_st_stm32_adc   DT_N_S_soc_S_adc_40012200
#define DT_N_NODELABEL_adc3        DT_N_S_soc_S_adc_40012200

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_adc_40012200_REG_NUM 1
#define DT_N_S_soc_S_adc_40012200_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_REG_IDX_0_VAL_ADDRESS 1073816064 /* 0x40012200 */
#define DT_N_S_soc_S_adc_40012200_REG_IDX_0_VAL_SIZE 80 /* 0x50 */
#define DT_N_S_soc_S_adc_40012200_FOREACH_REG(fn) fn(DT_N_S_soc_S_adc_40012200, 0)
#define DT_N_S_soc_S_adc_40012200_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012200, 0)
#define DT_N_S_soc_S_adc_40012200_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012200, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012200, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_RANGES_NUM 0
#define DT_N_S_soc_S_adc_40012200_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_adc_40012200_IRQ_NUM 1
#define DT_N_S_soc_S_adc_40012200_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_IRQ_IDX_0_VAL_irq 18
#define DT_N_S_soc_S_adc_40012200_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_adc_40012200_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_adc_40012200_IRQ_LEVEL 1
#define DT_N_S_soc_S_adc_40012200_COMPAT_MATCHES_st_stm32f4_adc 1
#define DT_N_S_soc_S_adc_40012200_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_adc_40012200_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_COMPAT_MODEL_IDX_0 "stm32f4-adc"
#define DT_N_S_soc_S_adc_40012200_COMPAT_MATCHES_st_stm32_adc 1
#define DT_N_S_soc_S_adc_40012200_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_adc_40012200_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_COMPAT_MODEL_IDX_1 "stm32-adc"
#define DT_N_S_soc_S_adc_40012200_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_adc_40012200_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_adc_40012200_P_reg {1073816064 /* 0x40012200 */, 80 /* 0x50 */}
#define DT_N_S_soc_S_adc_40012200_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_reg_IDX_0 1073816064
#define DT_N_S_soc_S_adc_40012200_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_reg_IDX_1 80
#define DT_N_S_soc_S_adc_40012200_P_reg_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_adc_40012200_P_clocks_IDX_0_VAL_bus 68
#define DT_N_S_soc_S_adc_40012200_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_clocks_IDX_0_VAL_bits 1024
#define DT_N_S_soc_S_adc_40012200_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_adc_40012200, clocks, 0, bus) \
	fn(DT_N_S_soc_S_adc_40012200, clocks, 0, bits)
#define DT_N_S_soc_S_adc_40012200_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012200, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, clocks, 0, bits)
#define DT_N_S_soc_S_adc_40012200_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_adc_40012200_P_clocks_IDX_0_NAME "adcx"
#define DT_N_S_soc_S_adc_40012200_P_clocks_NAME_adcx_IDX 0
#define DT_N_S_soc_S_adc_40012200_P_clocks_NAME_adcx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_adc_40012200, clocks, adcx, bus) \
	fn(DT_N_S_soc_S_adc_40012200, clocks, adcx, bits)
#define DT_N_S_soc_S_adc_40012200_P_clocks_NAME_adcx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012200, clocks, adcx, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, clocks, adcx, bits)
#define DT_N_S_soc_S_adc_40012200_P_clocks_NAME_adcx_NUM_CELLS 2
#define DT_N_S_soc_S_adc_40012200_P_clocks_NAME_adcx_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_adc_40012200_P_clocks_NAME_adcx_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_clocks_NAME_adcx_VAL_bus DT_N_S_soc_S_adc_40012200_P_clocks_IDX_0_VAL_bus
#define DT_N_S_soc_S_adc_40012200_P_clocks_NAME_adcx_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_clocks_NAME_adcx_VAL_bits DT_N_S_soc_S_adc_40012200_P_clocks_IDX_0_VAL_bits
#define DT_N_S_soc_S_adc_40012200_P_clocks_NAME_adcx_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012200, clocks, 0)
#define DT_N_S_soc_S_adc_40012200_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012200, clocks, 0)
#define DT_N_S_soc_S_adc_40012200_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012200, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012200, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_clocks_LEN 1
#define DT_N_S_soc_S_adc_40012200_P_clocks_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_clock_names {"adcx"}
#define DT_N_S_soc_S_adc_40012200_P_clock_names_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_adc_40012200_P_clock_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_clock_names_IDX_0_ENUM_VAL_adcx_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_clock_names_ENUM_VAL_adcx_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_clock_names_IDX_0 "adcx"
#define DT_N_S_soc_S_adc_40012200_P_clock_names_IDX_0_STRING_UNQUOTED adcx
#define DT_N_S_soc_S_adc_40012200_P_clock_names_IDX_0_STRING_TOKEN adcx
#define DT_N_S_soc_S_adc_40012200_P_clock_names_IDX_0_STRING_UPPER_TOKEN ADCX
#define DT_N_S_soc_S_adc_40012200_P_clock_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012200, clock_names, 0)
#define DT_N_S_soc_S_adc_40012200_P_clock_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012200, clock_names, 0)
#define DT_N_S_soc_S_adc_40012200_P_clock_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012200, clock_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_clock_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012200, clock_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_clock_names_LEN 1
#define DT_N_S_soc_S_adc_40012200_P_clock_names_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_interrupts {18 /* 0x12 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_adc_40012200_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_interrupts_IDX_0 18
#define DT_N_S_soc_S_adc_40012200_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_adc_40012200_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_clock_source "SYNC"
#define DT_N_S_soc_S_adc_40012200_P_st_adc_clock_source_STRING_UNQUOTED SYNC
#define DT_N_S_soc_S_adc_40012200_P_st_adc_clock_source_STRING_TOKEN SYNC
#define DT_N_S_soc_S_adc_40012200_P_st_adc_clock_source_STRING_UPPER_TOKEN SYNC
#define DT_N_S_soc_S_adc_40012200_P_st_adc_clock_source_IDX_0 "SYNC"
#define DT_N_S_soc_S_adc_40012200_P_st_adc_clock_source_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_clock_source_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_adc_40012200_P_st_adc_clock_source_IDX_0_ENUM_VAL_sync_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_clock_source_ENUM_VAL_sync_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_clock_source_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012200, st_adc_clock_source, 0)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_clock_source_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012200, st_adc_clock_source, 0)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012200, st_adc_clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_clock_source_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012200, st_adc_clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_clock_source_LEN 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_clock_source_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_vref_mv 3300
#define DT_N_S_soc_S_adc_40012200_P_vref_mv_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_resolutions {12 /* 0xc */, 10 /* 0xa */, 8 /* 0x8 */, 6 /* 0x6 */}
#define DT_N_S_soc_S_adc_40012200_P_st_adc_resolutions_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_resolutions_IDX_0 12
#define DT_N_S_soc_S_adc_40012200_P_st_adc_resolutions_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_resolutions_IDX_1 10
#define DT_N_S_soc_S_adc_40012200_P_st_adc_resolutions_IDX_2_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_resolutions_IDX_2 8
#define DT_N_S_soc_S_adc_40012200_P_st_adc_resolutions_IDX_3_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_resolutions_IDX_3 6
#define DT_N_S_soc_S_adc_40012200_P_st_adc_resolutions_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012200, st_adc_resolutions, 0) \
	fn(DT_N_S_soc_S_adc_40012200, st_adc_resolutions, 1) \
	fn(DT_N_S_soc_S_adc_40012200, st_adc_resolutions, 2) \
	fn(DT_N_S_soc_S_adc_40012200, st_adc_resolutions, 3)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_resolutions_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012200, st_adc_resolutions, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, st_adc_resolutions, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, st_adc_resolutions, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, st_adc_resolutions, 3)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_resolutions_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012200, st_adc_resolutions, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012200, st_adc_resolutions, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012200, st_adc_resolutions, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012200, st_adc_resolutions, 3, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_resolutions_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012200, st_adc_resolutions, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, st_adc_resolutions, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, st_adc_resolutions, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, st_adc_resolutions, 3, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_resolutions_LEN 4
#define DT_N_S_soc_S_adc_40012200_P_st_adc_resolutions_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_sampling_times {3 /* 0x3 */, 15 /* 0xf */, 28 /* 0x1c */, 56 /* 0x38 */, 84 /* 0x54 */, 112 /* 0x70 */, 144 /* 0x90 */, 480 /* 0x1e0 */}
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_IDX_0 3
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_IDX_1 15
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_IDX_2_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_IDX_2 28
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_IDX_3_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_IDX_3 56
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_IDX_4_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_IDX_4 84
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_IDX_5_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_IDX_5 112
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_IDX_6_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_IDX_6 144
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_IDX_7_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_IDX_7 480
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012200, sampling_times, 0) \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 1) \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 2) \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 3) \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 4) \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 5) \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 6) \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 7)
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012200, sampling_times, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 7)
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012200, sampling_times, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 7, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012200, sampling_times, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, sampling_times, 7, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_LEN 8
#define DT_N_S_soc_S_adc_40012200_P_sampling_times_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_sequencer "programmable"
#define DT_N_S_soc_S_adc_40012200_P_st_adc_sequencer_STRING_UNQUOTED programmable
#define DT_N_S_soc_S_adc_40012200_P_st_adc_sequencer_STRING_TOKEN programmable
#define DT_N_S_soc_S_adc_40012200_P_st_adc_sequencer_STRING_UPPER_TOKEN PROGRAMMABLE
#define DT_N_S_soc_S_adc_40012200_P_st_adc_sequencer_IDX_0 "programmable"
#define DT_N_S_soc_S_adc_40012200_P_st_adc_sequencer_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_sequencer_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_sequencer_IDX_0_ENUM_VAL_programmable_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_sequencer_ENUM_VAL_programmable_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_sequencer_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012200, st_adc_sequencer, 0)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_sequencer_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012200, st_adc_sequencer, 0)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_sequencer_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012200, st_adc_sequencer, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_sequencer_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012200, st_adc_sequencer, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_sequencer_LEN 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_sequencer_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_oversampler "none"
#define DT_N_S_soc_S_adc_40012200_P_st_adc_oversampler_STRING_UNQUOTED none
#define DT_N_S_soc_S_adc_40012200_P_st_adc_oversampler_STRING_TOKEN none
#define DT_N_S_soc_S_adc_40012200_P_st_adc_oversampler_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_adc_40012200_P_st_adc_oversampler_IDX_0 "none"
#define DT_N_S_soc_S_adc_40012200_P_st_adc_oversampler_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_oversampler_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_adc_40012200_P_st_adc_oversampler_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_oversampler_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_oversampler_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012200, st_adc_oversampler, 0)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_oversampler_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012200, st_adc_oversampler, 0)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_oversampler_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012200, st_adc_oversampler, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_oversampler_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012200, st_adc_oversampler, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_oversampler_LEN 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_oversampler_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_internal_regulator "none"
#define DT_N_S_soc_S_adc_40012200_P_st_adc_internal_regulator_STRING_UNQUOTED none
#define DT_N_S_soc_S_adc_40012200_P_st_adc_internal_regulator_STRING_TOKEN none
#define DT_N_S_soc_S_adc_40012200_P_st_adc_internal_regulator_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_adc_40012200_P_st_adc_internal_regulator_IDX_0 "none"
#define DT_N_S_soc_S_adc_40012200_P_st_adc_internal_regulator_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_internal_regulator_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_adc_40012200_P_st_adc_internal_regulator_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_internal_regulator_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_internal_regulator_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012200, st_adc_internal_regulator, 0)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_internal_regulator_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012200, st_adc_internal_regulator, 0)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_internal_regulator_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012200, st_adc_internal_regulator, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_internal_regulator_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012200, st_adc_internal_regulator, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_st_adc_internal_regulator_LEN 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_internal_regulator_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_has_deep_powerdown 0
#define DT_N_S_soc_S_adc_40012200_P_st_adc_has_deep_powerdown_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_has_channel_preselection 0
#define DT_N_S_soc_S_adc_40012200_P_st_adc_has_channel_preselection_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_has_differential_support 0
#define DT_N_S_soc_S_adc_40012200_P_st_adc_has_differential_support_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_has_injected_support 1
#define DT_N_S_soc_S_adc_40012200_P_st_adc_has_injected_support_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_status "disabled"
#define DT_N_S_soc_S_adc_40012200_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_adc_40012200_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_adc_40012200_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_adc_40012200_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_adc_40012200_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_adc_40012200_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012200, status, 0)
#define DT_N_S_soc_S_adc_40012200_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012200, status, 0)
#define DT_N_S_soc_S_adc_40012200_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012200, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012200, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_status_LEN 1
#define DT_N_S_soc_S_adc_40012200_P_status_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_compatible {"st,stm32f4-adc", "st,stm32-adc"}
#define DT_N_S_soc_S_adc_40012200_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_compatible_IDX_0 "st,stm32f4-adc"
#define DT_N_S_soc_S_adc_40012200_P_compatible_IDX_0_STRING_UNQUOTED st,stm32f4-adc
#define DT_N_S_soc_S_adc_40012200_P_compatible_IDX_0_STRING_TOKEN st_stm32f4_adc
#define DT_N_S_soc_S_adc_40012200_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32F4_ADC
#define DT_N_S_soc_S_adc_40012200_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_compatible_IDX_1 "st,stm32-adc"
#define DT_N_S_soc_S_adc_40012200_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-adc
#define DT_N_S_soc_S_adc_40012200_P_compatible_IDX_1_STRING_TOKEN st_stm32_adc
#define DT_N_S_soc_S_adc_40012200_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_ADC
#define DT_N_S_soc_S_adc_40012200_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40012200, compatible, 0) \
	fn(DT_N_S_soc_S_adc_40012200, compatible, 1)
#define DT_N_S_soc_S_adc_40012200_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40012200, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, compatible, 1)
#define DT_N_S_soc_S_adc_40012200_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40012200, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_40012200, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40012200, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_40012200, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40012200_P_compatible_LEN 2
#define DT_N_S_soc_S_adc_40012200_P_compatible_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_dma_coherent 0
#define DT_N_S_soc_S_adc_40012200_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_adc_40012200_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_wakeup_source 0
#define DT_N_S_soc_S_adc_40012200_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_adc_40012200_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_adc_40012200_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/can@40006400
 *
 * Node identifier: DT_N_S_soc_S_can_40006400
 *
 * Binding (compatible = st,stm32-bxcan):
 *   $ZEPHYR_BASE\dts\bindings\can\st,stm32-bxcan.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_can_40006400_PATH "/soc/can@40006400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_can_40006400_FULL_NAME "can@40006400"
#define DT_N_S_soc_S_can_40006400_FULL_NAME_UNQUOTED can@40006400
#define DT_N_S_soc_S_can_40006400_FULL_NAME_TOKEN can_40006400
#define DT_N_S_soc_S_can_40006400_FULL_NAME_UPPER_TOKEN CAN_40006400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_can_40006400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_can_40006400_CHILD_IDX 44

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_can_40006400_NODELABEL_NUM 1
#define DT_N_S_soc_S_can_40006400_FOREACH_NODELABEL(fn) fn(can1)
#define DT_N_S_soc_S_can_40006400_FOREACH_NODELABEL_VARGS(fn, ...) fn(can1, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_can_40006400_CHILD_NUM 0
#define DT_N_S_soc_S_can_40006400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_can_40006400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_can_40006400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_can_40006400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_can_40006400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_can_40006400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_can_40006400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_can_40006400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_can_40006400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_can_40006400_HASH val_iOcNyNmh6jx1XoeAlpOC9DwQRToiiXS2PS43mJQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_can_40006400_ORD 59
#define DT_N_S_soc_S_can_40006400_ORD_STR_SORTABLE 00059

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_can_40006400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_can_40006400_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_can_40006400_IDX_0_C_TOKEN can1

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_can_40006400_EXISTS 1
#define DT_N_INST_0_st_stm32_bxcan DT_N_S_soc_S_can_40006400
#define DT_N_NODELABEL_can1        DT_N_S_soc_S_can_40006400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_can_40006400_REG_NUM 1
#define DT_N_S_soc_S_can_40006400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_REG_IDX_0_VAL_ADDRESS 1073767424 /* 0x40006400 */
#define DT_N_S_soc_S_can_40006400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_can_40006400_FOREACH_REG(fn) fn(DT_N_S_soc_S_can_40006400, 0)
#define DT_N_S_soc_S_can_40006400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006400, 0)
#define DT_N_S_soc_S_can_40006400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_can_40006400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_40006400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_RANGES_NUM 0
#define DT_N_S_soc_S_can_40006400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_can_40006400_IRQ_NUM 4
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_0_VAL_irq 19
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_1_VAL_irq 20
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_2_VAL_irq 21
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_2_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_2_VAL_priority 0
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_2_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_2_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_3_VAL_irq 22
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_3_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_3_VAL_priority 0
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_3_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_3_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_can_40006400_IRQ_LEVEL 1
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_tx_VAL_irq DT_N_S_soc_S_can_40006400_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_tx_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_tx_VAL_priority DT_N_S_soc_S_can_40006400_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_tx_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_tx_CONTROLLER DT_N_S_soc_S_can_40006400_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_rx0_VAL_irq DT_N_S_soc_S_can_40006400_IRQ_IDX_1_VAL_irq
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_rx0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_rx0_VAL_priority DT_N_S_soc_S_can_40006400_IRQ_IDX_1_VAL_priority
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_rx0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_rx0_CONTROLLER DT_N_S_soc_S_can_40006400_IRQ_IDX_1_CONTROLLER
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_rx1_VAL_irq DT_N_S_soc_S_can_40006400_IRQ_IDX_2_VAL_irq
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_rx1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_rx1_VAL_priority DT_N_S_soc_S_can_40006400_IRQ_IDX_2_VAL_priority
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_rx1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_rx1_CONTROLLER DT_N_S_soc_S_can_40006400_IRQ_IDX_2_CONTROLLER
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_sce_VAL_irq DT_N_S_soc_S_can_40006400_IRQ_IDX_3_VAL_irq
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_sce_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_sce_VAL_priority DT_N_S_soc_S_can_40006400_IRQ_IDX_3_VAL_priority
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_sce_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_sce_CONTROLLER DT_N_S_soc_S_can_40006400_IRQ_IDX_3_CONTROLLER
#define DT_N_S_soc_S_can_40006400_COMPAT_MATCHES_st_stm32_bxcan 1
#define DT_N_S_soc_S_can_40006400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_can_40006400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_COMPAT_MODEL_IDX_0 "stm32-bxcan"
#define DT_N_S_soc_S_can_40006400_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_can_40006400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_can_40006400_P_reg {1073767424 /* 0x40006400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_can_40006400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_reg_IDX_0 1073767424
#define DT_N_S_soc_S_can_40006400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_can_40006400_P_reg_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupts {19 /* 0x13 */, 0 /* 0x0 */, 20 /* 0x14 */, 0 /* 0x0 */, 21 /* 0x15 */, 0 /* 0x0 */, 22 /* 0x16 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_0 19
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_2 20
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_4_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_4 21
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_5_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_5 0
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_6_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_6 22
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_7_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_7 0
#define DT_N_S_soc_S_can_40006400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_can_40006400_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_can_40006400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_clocks_IDX_0_VAL_bits 33554432
#define DT_N_S_soc_S_can_40006400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_can_40006400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_can_40006400, clocks, 0, bits)
#define DT_N_S_soc_S_can_40006400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, clocks, 0, bits)
#define DT_N_S_soc_S_can_40006400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_can_40006400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_40006400, clocks, 0)
#define DT_N_S_soc_S_can_40006400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006400, clocks, 0)
#define DT_N_S_soc_S_can_40006400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_40006400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_40006400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_clocks_LEN 1
#define DT_N_S_soc_S_can_40006400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_status "disabled"
#define DT_N_S_soc_S_can_40006400_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_can_40006400_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_can_40006400_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_can_40006400_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_can_40006400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_can_40006400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_40006400, status, 0)
#define DT_N_S_soc_S_can_40006400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006400, status, 0)
#define DT_N_S_soc_S_can_40006400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_40006400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_40006400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_status_LEN 1
#define DT_N_S_soc_S_can_40006400_P_status_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_compatible {"st,stm32-bxcan"}
#define DT_N_S_soc_S_can_40006400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_compatible_IDX_0 "st,stm32-bxcan"
#define DT_N_S_soc_S_can_40006400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-bxcan
#define DT_N_S_soc_S_can_40006400_P_compatible_IDX_0_STRING_TOKEN st_stm32_bxcan
#define DT_N_S_soc_S_can_40006400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_BXCAN
#define DT_N_S_soc_S_can_40006400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_40006400, compatible, 0)
#define DT_N_S_soc_S_can_40006400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006400, compatible, 0)
#define DT_N_S_soc_S_can_40006400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_40006400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_40006400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_compatible_LEN 1
#define DT_N_S_soc_S_can_40006400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupt_names {"TX", "RX0", "RX1", "SCE"}
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_0 "TX"
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_0_STRING_UNQUOTED TX
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_0_STRING_TOKEN TX
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN TX
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_1 "RX0"
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_1_STRING_UNQUOTED RX0
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_1_STRING_TOKEN RX0
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN RX0
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_2_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_2 "RX1"
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_2_STRING_UNQUOTED RX1
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_2_STRING_TOKEN RX1
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN RX1
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_3_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_3 "SCE"
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_3_STRING_UNQUOTED SCE
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_3_STRING_TOKEN SCE
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_3_STRING_UPPER_TOKEN SCE
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_40006400, interrupt_names, 0) \
	fn(DT_N_S_soc_S_can_40006400, interrupt_names, 1) \
	fn(DT_N_S_soc_S_can_40006400, interrupt_names, 2) \
	fn(DT_N_S_soc_S_can_40006400, interrupt_names, 3)
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006400, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, interrupt_names, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, interrupt_names, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, interrupt_names, 3)
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_40006400, interrupt_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_can_40006400, interrupt_names, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_can_40006400, interrupt_names, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_can_40006400, interrupt_names, 3, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_40006400, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, interrupt_names, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, interrupt_names, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, interrupt_names, 3, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_LEN 4
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_dma_coherent 0
#define DT_N_S_soc_S_can_40006400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_can_40006400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_wakeup_source 0
#define DT_N_S_soc_S_can_40006400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_can_40006400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/can@40006800
 *
 * Node identifier: DT_N_S_soc_S_can_40006800
 *
 * Binding (compatible = st,stm32-bxcan):
 *   $ZEPHYR_BASE\dts\bindings\can\st,stm32-bxcan.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_can_40006800_PATH "/soc/can@40006800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_can_40006800_FULL_NAME "can@40006800"
#define DT_N_S_soc_S_can_40006800_FULL_NAME_UNQUOTED can@40006800
#define DT_N_S_soc_S_can_40006800_FULL_NAME_TOKEN can_40006800
#define DT_N_S_soc_S_can_40006800_FULL_NAME_UPPER_TOKEN CAN_40006800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_can_40006800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_can_40006800_CHILD_IDX 45

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_can_40006800_NODELABEL_NUM 1
#define DT_N_S_soc_S_can_40006800_FOREACH_NODELABEL(fn) fn(can2)
#define DT_N_S_soc_S_can_40006800_FOREACH_NODELABEL_VARGS(fn, ...) fn(can2, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_can_40006800_CHILD_NUM 0
#define DT_N_S_soc_S_can_40006800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_can_40006800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_can_40006800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_can_40006800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_can_40006800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_can_40006800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_can_40006800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_can_40006800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_can_40006800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_can_40006800_HASH y20CprTbiBzqYzfZOxJkE92qZmllpADEfqqY6Kr4g_s

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_can_40006800_ORD 60
#define DT_N_S_soc_S_can_40006800_ORD_STR_SORTABLE 00060

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_can_40006800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_can_40006800_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_can_40006800_IDX_0_C_TOKEN can2

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_can_40006800_EXISTS 1
#define DT_N_INST_1_st_stm32_bxcan DT_N_S_soc_S_can_40006800
#define DT_N_NODELABEL_can2        DT_N_S_soc_S_can_40006800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_can_40006800_REG_NUM 1
#define DT_N_S_soc_S_can_40006800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006800_REG_IDX_0_VAL_ADDRESS 1073768448 /* 0x40006800 */
#define DT_N_S_soc_S_can_40006800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_can_40006800_FOREACH_REG(fn) fn(DT_N_S_soc_S_can_40006800, 0)
#define DT_N_S_soc_S_can_40006800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006800, 0)
#define DT_N_S_soc_S_can_40006800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_can_40006800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_40006800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006800_RANGES_NUM 0
#define DT_N_S_soc_S_can_40006800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_can_40006800_IRQ_NUM 4
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_0_VAL_irq 63
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_1_VAL_irq 64
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_2_VAL_irq 65
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_2_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_2_VAL_priority 0
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_2_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_2_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_3_VAL_irq 66
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_3_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_3_VAL_priority 0
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_3_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_IDX_3_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_can_40006800_IRQ_LEVEL 1
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_tx_VAL_irq DT_N_S_soc_S_can_40006800_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_tx_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_tx_VAL_priority DT_N_S_soc_S_can_40006800_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_tx_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_tx_CONTROLLER DT_N_S_soc_S_can_40006800_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_rx0_VAL_irq DT_N_S_soc_S_can_40006800_IRQ_IDX_1_VAL_irq
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_rx0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_rx0_VAL_priority DT_N_S_soc_S_can_40006800_IRQ_IDX_1_VAL_priority
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_rx0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_rx0_CONTROLLER DT_N_S_soc_S_can_40006800_IRQ_IDX_1_CONTROLLER
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_rx1_VAL_irq DT_N_S_soc_S_can_40006800_IRQ_IDX_2_VAL_irq
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_rx1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_rx1_VAL_priority DT_N_S_soc_S_can_40006800_IRQ_IDX_2_VAL_priority
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_rx1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_rx1_CONTROLLER DT_N_S_soc_S_can_40006800_IRQ_IDX_2_CONTROLLER
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_sce_VAL_irq DT_N_S_soc_S_can_40006800_IRQ_IDX_3_VAL_irq
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_sce_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_sce_VAL_priority DT_N_S_soc_S_can_40006800_IRQ_IDX_3_VAL_priority
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_sce_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006800_IRQ_NAME_sce_CONTROLLER DT_N_S_soc_S_can_40006800_IRQ_IDX_3_CONTROLLER
#define DT_N_S_soc_S_can_40006800_COMPAT_MATCHES_st_stm32_bxcan 1
#define DT_N_S_soc_S_can_40006800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_can_40006800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006800_COMPAT_MODEL_IDX_0 "stm32-bxcan"
#define DT_N_S_soc_S_can_40006800_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_can_40006800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_can_40006800_P_reg {1073768448 /* 0x40006800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_can_40006800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_reg_IDX_0 1073768448
#define DT_N_S_soc_S_can_40006800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_can_40006800_P_reg_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_interrupts {63 /* 0x3f */, 0 /* 0x0 */, 64 /* 0x40 */, 0 /* 0x0 */, 65 /* 0x41 */, 0 /* 0x0 */, 66 /* 0x42 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_can_40006800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_interrupts_IDX_0 63
#define DT_N_S_soc_S_can_40006800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_can_40006800_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_interrupts_IDX_2 64
#define DT_N_S_soc_S_can_40006800_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_can_40006800_P_interrupts_IDX_4_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_interrupts_IDX_4 65
#define DT_N_S_soc_S_can_40006800_P_interrupts_IDX_5_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_interrupts_IDX_5 0
#define DT_N_S_soc_S_can_40006800_P_interrupts_IDX_6_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_interrupts_IDX_6 66
#define DT_N_S_soc_S_can_40006800_P_interrupts_IDX_7_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_interrupts_IDX_7 0
#define DT_N_S_soc_S_can_40006800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_can_40006800_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_can_40006800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_clocks_IDX_0_VAL_bits 100663296
#define DT_N_S_soc_S_can_40006800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_can_40006800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_can_40006800, clocks, 0, bits)
#define DT_N_S_soc_S_can_40006800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006800, clocks, 0, bits)
#define DT_N_S_soc_S_can_40006800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_can_40006800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_40006800, clocks, 0)
#define DT_N_S_soc_S_can_40006800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006800, clocks, 0)
#define DT_N_S_soc_S_can_40006800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_40006800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_40006800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006800_P_clocks_LEN 1
#define DT_N_S_soc_S_can_40006800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_master_can_reg 1073767424
#define DT_N_S_soc_S_can_40006800_P_master_can_reg_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_status "disabled"
#define DT_N_S_soc_S_can_40006800_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_can_40006800_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_can_40006800_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_can_40006800_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_can_40006800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_can_40006800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_40006800, status, 0)
#define DT_N_S_soc_S_can_40006800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006800, status, 0)
#define DT_N_S_soc_S_can_40006800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_40006800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_40006800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006800_P_status_LEN 1
#define DT_N_S_soc_S_can_40006800_P_status_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_compatible {"st,stm32-bxcan"}
#define DT_N_S_soc_S_can_40006800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_compatible_IDX_0 "st,stm32-bxcan"
#define DT_N_S_soc_S_can_40006800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-bxcan
#define DT_N_S_soc_S_can_40006800_P_compatible_IDX_0_STRING_TOKEN st_stm32_bxcan
#define DT_N_S_soc_S_can_40006800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_BXCAN
#define DT_N_S_soc_S_can_40006800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_40006800, compatible, 0)
#define DT_N_S_soc_S_can_40006800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006800, compatible, 0)
#define DT_N_S_soc_S_can_40006800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_40006800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_40006800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006800_P_compatible_LEN 1
#define DT_N_S_soc_S_can_40006800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_interrupt_names {"TX", "RX0", "RX1", "SCE"}
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_0 "TX"
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_0_STRING_UNQUOTED TX
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_0_STRING_TOKEN TX
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN TX
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_1 "RX0"
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_1_STRING_UNQUOTED RX0
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_1_STRING_TOKEN RX0
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN RX0
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_2_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_2 "RX1"
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_2_STRING_UNQUOTED RX1
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_2_STRING_TOKEN RX1
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN RX1
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_3_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_3 "SCE"
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_3_STRING_UNQUOTED SCE
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_3_STRING_TOKEN SCE
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_IDX_3_STRING_UPPER_TOKEN SCE
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_40006800, interrupt_names, 0) \
	fn(DT_N_S_soc_S_can_40006800, interrupt_names, 1) \
	fn(DT_N_S_soc_S_can_40006800, interrupt_names, 2) \
	fn(DT_N_S_soc_S_can_40006800, interrupt_names, 3)
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006800, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006800, interrupt_names, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006800, interrupt_names, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006800, interrupt_names, 3)
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_40006800, interrupt_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_can_40006800, interrupt_names, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_can_40006800, interrupt_names, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_can_40006800, interrupt_names, 3, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_40006800, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006800, interrupt_names, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006800, interrupt_names, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006800, interrupt_names, 3, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_LEN 4
#define DT_N_S_soc_S_can_40006800_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_dma_coherent 0
#define DT_N_S_soc_S_can_40006800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_can_40006800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_wakeup_source 0
#define DT_N_S_soc_S_can_40006800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_can_40006800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_can_40006800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/dac_out1_pa4
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_PATH "/soc/pin-controller@40020000/dac_out1_pa4"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FULL_NAME "dac_out1_pa4"
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FULL_NAME_UNQUOTED dac_out1_pa4
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FULL_NAME_TOKEN dac_out1_pa4
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FULL_NAME_UPPER_TOKEN DAC_OUT1_PA4

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_CHILD_IDX 12

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FOREACH_NODELABEL(fn) fn(dac_out1_pa4)
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FOREACH_NODELABEL_VARGS(fn, ...) fn(dac_out1_pa4, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_HASH YB9JiGmxjeThuwfFjvaMrAyc_VZRrZ4yDdRtTRvatlI

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_ORD 61
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_ORD_STR_SORTABLE 00061

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_SUPPORTS_ORDS \
	62, /* /soc/dac@40007400 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_IDX_0_C_TOKEN dac_out1_pa4

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_EXISTS 1
#define DT_N_NODELABEL_dac_out1_pa4 DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_pinmux 144
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/dac@40007400
 *
 * Node identifier: DT_N_S_soc_S_dac_40007400
 *
 * Binding (compatible = st,stm32-dac):
 *   $ZEPHYR_BASE\dts\bindings\dac\st,stm32-dac.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_dac_40007400_PATH "/soc/dac@40007400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_dac_40007400_FULL_NAME "dac@40007400"
#define DT_N_S_soc_S_dac_40007400_FULL_NAME_UNQUOTED dac@40007400
#define DT_N_S_soc_S_dac_40007400_FULL_NAME_TOKEN dac_40007400
#define DT_N_S_soc_S_dac_40007400_FULL_NAME_UPPER_TOKEN DAC_40007400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_dac_40007400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_dac_40007400_CHILD_IDX 50

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_dac_40007400_NODELABEL_NUM 1
#define DT_N_S_soc_S_dac_40007400_FOREACH_NODELABEL(fn) fn(dac1)
#define DT_N_S_soc_S_dac_40007400_FOREACH_NODELABEL_VARGS(fn, ...) fn(dac1, __VA_ARGS__)
#define DT_N_S_soc_S_dac_40007400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_dac_40007400_CHILD_NUM 0
#define DT_N_S_soc_S_dac_40007400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_dac_40007400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_dac_40007400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_dac_40007400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_dac_40007400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_dac_40007400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_dac_40007400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_dac_40007400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_dac_40007400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_dac_40007400_HASH AEmTXTZMLBfEYJhhkd3MmBxYI__rcYzmOjJiV2l9668

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_dac_40007400_ORD 62
#define DT_N_S_soc_S_dac_40007400_ORD_STR_SORTABLE 00062

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_dac_40007400_REQUIRES_ORDS \
	4, /* /soc */ \
	9, /* /soc/rcc@40023800 */ \
	61, /* /soc/pin-controller@40020000/dac_out1_pa4 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_dac_40007400_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_dac_40007400_IDX_0_C_TOKEN dac1

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_dac_40007400_EXISTS 1
#define DT_N_INST_0_st_stm32_dac DT_N_S_soc_S_dac_40007400
#define DT_N_NODELABEL_dac1      DT_N_S_soc_S_dac_40007400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_dac_40007400_REG_NUM 1
#define DT_N_S_soc_S_dac_40007400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_REG_IDX_0_VAL_ADDRESS 1073771520 /* 0x40007400 */
#define DT_N_S_soc_S_dac_40007400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_dac_40007400_FOREACH_REG(fn) fn(DT_N_S_soc_S_dac_40007400, 0)
#define DT_N_S_soc_S_dac_40007400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_dac_40007400, 0)
#define DT_N_S_soc_S_dac_40007400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_40007400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_40007400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_40007400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_40007400_RANGES_NUM 0
#define DT_N_S_soc_S_dac_40007400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_dac_40007400_IRQ_NUM 0
#define DT_N_S_soc_S_dac_40007400_IRQ_LEVEL 0
#define DT_N_S_soc_S_dac_40007400_COMPAT_MATCHES_st_stm32_dac 1
#define DT_N_S_soc_S_dac_40007400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_dac_40007400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_COMPAT_MODEL_IDX_0 "stm32-dac"
#define DT_N_S_soc_S_dac_40007400_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_dac_40007400_PINCTRL_NUM 1
#define DT_N_S_soc_S_dac_40007400_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_dac_40007400_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_dac_40007400_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_dac_40007400_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4

/* Generic property macros: */
#define DT_N_S_soc_S_dac_40007400_P_reg {1073771520 /* 0x40007400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_dac_40007400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_reg_IDX_0 1073771520
#define DT_N_S_soc_S_dac_40007400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_dac_40007400_P_reg_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_VAL_bits 536870912
#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_dac_40007400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_dac_40007400, clocks, 0, bits)
#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_dac_40007400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_dac_40007400, clocks, 0, bits)
#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_dac_40007400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dac_40007400, clocks, 0)
#define DT_N_S_soc_S_dac_40007400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dac_40007400, clocks, 0)
#define DT_N_S_soc_S_dac_40007400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_40007400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_40007400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_40007400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_40007400_P_clocks_LEN 1
#define DT_N_S_soc_S_dac_40007400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_status "okay"
#define DT_N_S_soc_S_dac_40007400_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_dac_40007400_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_dac_40007400_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_dac_40007400_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_dac_40007400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_dac_40007400_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dac_40007400, status, 0)
#define DT_N_S_soc_S_dac_40007400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dac_40007400, status, 0)
#define DT_N_S_soc_S_dac_40007400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_40007400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_40007400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_40007400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_40007400_P_status_LEN 1
#define DT_N_S_soc_S_dac_40007400_P_status_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_compatible {"st,stm32-dac"}
#define DT_N_S_soc_S_dac_40007400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_compatible_IDX_0 "st,stm32-dac"
#define DT_N_S_soc_S_dac_40007400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-dac
#define DT_N_S_soc_S_dac_40007400_P_compatible_IDX_0_STRING_TOKEN st_stm32_dac
#define DT_N_S_soc_S_dac_40007400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_DAC
#define DT_N_S_soc_S_dac_40007400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dac_40007400, compatible, 0)
#define DT_N_S_soc_S_dac_40007400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dac_40007400, compatible, 0)
#define DT_N_S_soc_S_dac_40007400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_40007400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_40007400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_40007400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_40007400_P_compatible_LEN 1
#define DT_N_S_soc_S_dac_40007400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_dma_coherent 0
#define DT_N_S_soc_S_dac_40007400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_dac_40007400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_wakeup_source 0
#define DT_N_S_soc_S_dac_40007400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_dac_40007400_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dac_40007400, pinctrl_0, 0)
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dac_40007400, pinctrl_0, 0)
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_40007400, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_40007400, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dac_40007400, pinctrl_names, 0)
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dac_40007400, pinctrl_names, 0)
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_40007400, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_40007400, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_EXISTS 1

/*
 * Devicetree node: /soc/rcc@40023800/reset-controller
 *
 * Node identifier: DT_N_S_soc_S_rcc_40023800_S_reset_controller
 *
 * Binding (compatible = st,stm32-rcc-rctl):
 *   $ZEPHYR_BASE\dts\bindings\reset\st,stm32-rcc-rctl.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_PATH "/soc/rcc@40023800/reset-controller"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FULL_NAME "reset-controller"
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FULL_NAME_UNQUOTED reset-controller
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FULL_NAME_TOKEN reset_controller
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FULL_NAME_UPPER_TOKEN RESET_CONTROLLER

/* Node parent (/soc/rcc@40023800) identifier: */
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_PARENT DT_N_S_soc_S_rcc_40023800

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_NODELABEL_NUM 1
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FOREACH_NODELABEL(fn) fn(rctl)
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FOREACH_NODELABEL_VARGS(fn, ...) fn(rctl, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_rcc_40023800) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_CHILD_NUM 0
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_HASH 6QG5_n0iq_njH0teBLjvF7pQWGSe0Ij3_J_h8E498kM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_ORD 63
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_ORD_STR_SORTABLE 00063

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_REQUIRES_ORDS \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_SUPPORTS_ORDS \
	64, /* /soc/display-controller@40016800 */ \
	71, /* /soc/sdmmc@40012c00 */ \
	72, /* /soc/serial@40004400 */ \
	75, /* /soc/serial@40004800 */ \
	76, /* /soc/serial@40004c00 */ \
	77, /* /soc/serial@40005000 */ \
	78, /* /soc/serial@40007800 */ \
	79, /* /soc/serial@40007c00 */ \
	80, /* /soc/serial@40011000 */ \
	83, /* /soc/serial@40011400 */ \
	137, /* /soc/timers@40000000 */ \
	141, /* /soc/timers@40000400 */ \
	145, /* /soc/timers@40000800 */ \
	149, /* /soc/timers@40000c00 */ \
	153, /* /soc/timers@40001000 */ \
	155, /* /soc/timers@40001400 */ \
	157, /* /soc/timers@40001800 */ \
	160, /* /soc/timers@40001c00 */ \
	163, /* /soc/timers@40002000 */ \
	166, /* /soc/timers@40010000 */ \
	171, /* /soc/timers@40010400 */ \
	175, /* /soc/timers@40014000 */ \
	178, /* /soc/timers@40014400 */ \
	181, /* /soc/timers@40014800 */
#define DT_N_NODELABEL_DT_N_S_soc_S_rcc_40023800_S_reset_controller_IDX_0_C_TOKEN rctl

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_EXISTS 1
#define DT_N_INST_0_st_stm32_rcc_rctl DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_NODELABEL_rctl           DT_N_S_soc_S_rcc_40023800_S_reset_controller

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_REG_NUM 0
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FOREACH_REG(fn) 
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_RANGES_NUM 0
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_IRQ_NUM 0
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_IRQ_LEVEL 0
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_COMPAT_MATCHES_st_stm32_rcc_rctl 1
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_COMPAT_MODEL_IDX_0 "stm32-rcc-rctl"
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_set_bit_to_deassert 0
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_set_bit_to_deassert_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_compatible {"st,stm32-rcc-rctl"}
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_compatible_IDX_0 "st,stm32-rcc-rctl"
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-rcc-rctl
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_compatible_IDX_0_STRING_TOKEN st_stm32_rcc_rctl
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_RCC_RCTL
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rcc_40023800_S_reset_controller, compatible, 0)
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rcc_40023800_S_reset_controller, compatible, 0)
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rcc_40023800_S_reset_controller, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rcc_40023800_S_reset_controller, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_compatible_LEN 1
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_compatible_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_dma_coherent 0
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_wakeup_source 0
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_rcc_40023800_S_reset_controller_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/display-controller@40016800
 *
 * Node identifier: DT_N_S_soc_S_display_controller_40016800
 *
 * Binding (compatible = st,stm32-ltdc):
 *   $ZEPHYR_BASE\dts\bindings\display\st,stm32-ltdc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_display_controller_40016800_PATH "/soc/display-controller@40016800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_display_controller_40016800_FULL_NAME "display-controller@40016800"
#define DT_N_S_soc_S_display_controller_40016800_FULL_NAME_UNQUOTED display-controller@40016800
#define DT_N_S_soc_S_display_controller_40016800_FULL_NAME_TOKEN display_controller_40016800
#define DT_N_S_soc_S_display_controller_40016800_FULL_NAME_UPPER_TOKEN DISPLAY_CONTROLLER_40016800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_display_controller_40016800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_display_controller_40016800_CHILD_IDX 58

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_display_controller_40016800_NODELABEL_NUM 1
#define DT_N_S_soc_S_display_controller_40016800_FOREACH_NODELABEL(fn) fn(ltdc)
#define DT_N_S_soc_S_display_controller_40016800_FOREACH_NODELABEL_VARGS(fn, ...) fn(ltdc, __VA_ARGS__)
#define DT_N_S_soc_S_display_controller_40016800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_display_controller_40016800_CHILD_NUM 0
#define DT_N_S_soc_S_display_controller_40016800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_display_controller_40016800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_display_controller_40016800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_display_controller_40016800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_display_controller_40016800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_display_controller_40016800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_display_controller_40016800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_display_controller_40016800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_display_controller_40016800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_display_controller_40016800_HASH l8tUSrk2Tc2CtQpr3dVaxucfg5MmAeDJZNNuPSoZJ3M

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_display_controller_40016800_ORD 64
#define DT_N_S_soc_S_display_controller_40016800_ORD_STR_SORTABLE 00064

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_display_controller_40016800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_display_controller_40016800_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_display_controller_40016800_IDX_0_C_TOKEN ltdc

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_display_controller_40016800_EXISTS 1
#define DT_N_INST_0_st_stm32_ltdc DT_N_S_soc_S_display_controller_40016800
#define DT_N_NODELABEL_ltdc       DT_N_S_soc_S_display_controller_40016800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_display_controller_40016800_REG_NUM 1
#define DT_N_S_soc_S_display_controller_40016800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_REG_IDX_0_VAL_ADDRESS 1073833984 /* 0x40016800 */
#define DT_N_S_soc_S_display_controller_40016800_REG_IDX_0_VAL_SIZE 512 /* 0x200 */
#define DT_N_S_soc_S_display_controller_40016800_FOREACH_REG(fn) fn(DT_N_S_soc_S_display_controller_40016800, 0)
#define DT_N_S_soc_S_display_controller_40016800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_display_controller_40016800, 0)
#define DT_N_S_soc_S_display_controller_40016800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_display_controller_40016800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_display_controller_40016800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_display_controller_40016800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_display_controller_40016800_RANGES_NUM 0
#define DT_N_S_soc_S_display_controller_40016800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_display_controller_40016800_IRQ_NUM 2
#define DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_0_VAL_irq 88
#define DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_1_VAL_irq 89
#define DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_display_controller_40016800_IRQ_LEVEL 1
#define DT_N_S_soc_S_display_controller_40016800_IRQ_NAME_ltdc_VAL_irq DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_display_controller_40016800_IRQ_NAME_ltdc_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_IRQ_NAME_ltdc_VAL_priority DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_display_controller_40016800_IRQ_NAME_ltdc_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_IRQ_NAME_ltdc_CONTROLLER DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_display_controller_40016800_IRQ_NAME_ltdc_er_VAL_irq DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_1_VAL_irq
#define DT_N_S_soc_S_display_controller_40016800_IRQ_NAME_ltdc_er_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_IRQ_NAME_ltdc_er_VAL_priority DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_1_VAL_priority
#define DT_N_S_soc_S_display_controller_40016800_IRQ_NAME_ltdc_er_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_IRQ_NAME_ltdc_er_CONTROLLER DT_N_S_soc_S_display_controller_40016800_IRQ_IDX_1_CONTROLLER
#define DT_N_S_soc_S_display_controller_40016800_COMPAT_MATCHES_st_stm32_ltdc 1
#define DT_N_S_soc_S_display_controller_40016800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_display_controller_40016800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_COMPAT_MODEL_IDX_0 "stm32-ltdc"
#define DT_N_S_soc_S_display_controller_40016800_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_display_controller_40016800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_display_controller_40016800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_display_controller_40016800_P_clocks_IDX_0_VAL_bus 68
#define DT_N_S_soc_S_display_controller_40016800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_clocks_IDX_0_VAL_bits 67108864
#define DT_N_S_soc_S_display_controller_40016800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_display_controller_40016800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_display_controller_40016800, clocks, 0, bits)
#define DT_N_S_soc_S_display_controller_40016800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_display_controller_40016800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_display_controller_40016800, clocks, 0, bits)
#define DT_N_S_soc_S_display_controller_40016800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_display_controller_40016800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_display_controller_40016800, clocks, 0)
#define DT_N_S_soc_S_display_controller_40016800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_display_controller_40016800, clocks, 0)
#define DT_N_S_soc_S_display_controller_40016800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_display_controller_40016800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_display_controller_40016800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_display_controller_40016800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_display_controller_40016800_P_clocks_LEN 1
#define DT_N_S_soc_S_display_controller_40016800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_display_controller_40016800_P_resets_IDX_0_VAL_id 1178
#define DT_N_S_soc_S_display_controller_40016800_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_display_controller_40016800, resets, 0, id)
#define DT_N_S_soc_S_display_controller_40016800_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_display_controller_40016800, resets, 0, id)
#define DT_N_S_soc_S_display_controller_40016800_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_display_controller_40016800_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_display_controller_40016800, resets, 0)
#define DT_N_S_soc_S_display_controller_40016800_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_display_controller_40016800, resets, 0)
#define DT_N_S_soc_S_display_controller_40016800_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_display_controller_40016800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_display_controller_40016800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_display_controller_40016800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_display_controller_40016800_P_resets_LEN 1
#define DT_N_S_soc_S_display_controller_40016800_P_resets_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_interrupts {88 /* 0x58 */, 0 /* 0x0 */, 89 /* 0x59 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_display_controller_40016800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_interrupts_IDX_0 88
#define DT_N_S_soc_S_display_controller_40016800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_display_controller_40016800_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_interrupts_IDX_2 89
#define DT_N_S_soc_S_display_controller_40016800_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_display_controller_40016800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_status "disabled"
#define DT_N_S_soc_S_display_controller_40016800_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_display_controller_40016800_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_display_controller_40016800_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_display_controller_40016800_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_display_controller_40016800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_display_controller_40016800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_display_controller_40016800, status, 0)
#define DT_N_S_soc_S_display_controller_40016800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_display_controller_40016800, status, 0)
#define DT_N_S_soc_S_display_controller_40016800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_display_controller_40016800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_display_controller_40016800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_display_controller_40016800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_display_controller_40016800_P_status_LEN 1
#define DT_N_S_soc_S_display_controller_40016800_P_status_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_compatible {"st,stm32-ltdc"}
#define DT_N_S_soc_S_display_controller_40016800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_compatible_IDX_0 "st,stm32-ltdc"
#define DT_N_S_soc_S_display_controller_40016800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-ltdc
#define DT_N_S_soc_S_display_controller_40016800_P_compatible_IDX_0_STRING_TOKEN st_stm32_ltdc
#define DT_N_S_soc_S_display_controller_40016800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_LTDC
#define DT_N_S_soc_S_display_controller_40016800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_display_controller_40016800, compatible, 0)
#define DT_N_S_soc_S_display_controller_40016800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_display_controller_40016800, compatible, 0)
#define DT_N_S_soc_S_display_controller_40016800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_display_controller_40016800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_display_controller_40016800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_display_controller_40016800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_display_controller_40016800_P_compatible_LEN 1
#define DT_N_S_soc_S_display_controller_40016800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_reg {1073833984 /* 0x40016800 */, 512 /* 0x200 */}
#define DT_N_S_soc_S_display_controller_40016800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_reg_IDX_0 1073833984
#define DT_N_S_soc_S_display_controller_40016800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_reg_IDX_1 512
#define DT_N_S_soc_S_display_controller_40016800_P_reg_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_interrupt_names {"ltdc", "ltdc_er"}
#define DT_N_S_soc_S_display_controller_40016800_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_interrupt_names_IDX_0 "ltdc"
#define DT_N_S_soc_S_display_controller_40016800_P_interrupt_names_IDX_0_STRING_UNQUOTED ltdc
#define DT_N_S_soc_S_display_controller_40016800_P_interrupt_names_IDX_0_STRING_TOKEN ltdc
#define DT_N_S_soc_S_display_controller_40016800_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN LTDC
#define DT_N_S_soc_S_display_controller_40016800_P_interrupt_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_interrupt_names_IDX_1 "ltdc_er"
#define DT_N_S_soc_S_display_controller_40016800_P_interrupt_names_IDX_1_STRING_UNQUOTED ltdc_er
#define DT_N_S_soc_S_display_controller_40016800_P_interrupt_names_IDX_1_STRING_TOKEN ltdc_er
#define DT_N_S_soc_S_display_controller_40016800_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN LTDC_ER
#define DT_N_S_soc_S_display_controller_40016800_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_display_controller_40016800, interrupt_names, 0) \
	fn(DT_N_S_soc_S_display_controller_40016800, interrupt_names, 1)
#define DT_N_S_soc_S_display_controller_40016800_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_display_controller_40016800, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_display_controller_40016800, interrupt_names, 1)
#define DT_N_S_soc_S_display_controller_40016800_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_display_controller_40016800, interrupt_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_display_controller_40016800, interrupt_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_display_controller_40016800_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_display_controller_40016800, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_display_controller_40016800, interrupt_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_display_controller_40016800_P_interrupt_names_LEN 2
#define DT_N_S_soc_S_display_controller_40016800_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_dma_coherent 0
#define DT_N_S_soc_S_display_controller_40016800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_display_controller_40016800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_wakeup_source 0
#define DT_N_S_soc_S_display_controller_40016800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_display_controller_40016800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_display_controller_40016800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/dma@40026000
 *
 * Node identifier: DT_N_S_soc_S_dma_40026000
 *
 * Binding (compatible = st,stm32-dma-v1):
 *   $ZEPHYR_BASE\dts\bindings\dma\st,stm32-dma-v1.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_dma_40026000_PATH "/soc/dma@40026000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_dma_40026000_FULL_NAME "dma@40026000"
#define DT_N_S_soc_S_dma_40026000_FULL_NAME_UNQUOTED dma@40026000
#define DT_N_S_soc_S_dma_40026000_FULL_NAME_TOKEN dma_40026000
#define DT_N_S_soc_S_dma_40026000_FULL_NAME_UPPER_TOKEN DMA_40026000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_dma_40026000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_dma_40026000_CHILD_IDX 26

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_dma_40026000_NODELABEL_NUM 1
#define DT_N_S_soc_S_dma_40026000_FOREACH_NODELABEL(fn) fn(dma1)
#define DT_N_S_soc_S_dma_40026000_FOREACH_NODELABEL_VARGS(fn, ...) fn(dma1, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40026000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_dma_40026000_CHILD_NUM 0
#define DT_N_S_soc_S_dma_40026000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_dma_40026000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_dma_40026000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_dma_40026000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_dma_40026000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_dma_40026000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_dma_40026000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_dma_40026000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_dma_40026000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_dma_40026000_HASH MZEmTTSEEbOm2DuyiRQjr9y_tKdzIKzE1ko8qyXIUwU

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_dma_40026000_ORD 65
#define DT_N_S_soc_S_dma_40026000_ORD_STR_SORTABLE 00065

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_dma_40026000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_dma_40026000_SUPPORTS_ORDS \
	66, /* /soc/i2s@40003800 */ \
	67, /* /soc/i2s@40003c00 */
#define DT_N_NODELABEL_DT_N_S_soc_S_dma_40026000_IDX_0_C_TOKEN dma1

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_dma_40026000_EXISTS 1
#define DT_N_INST_1_st_stm32_dma_v1 DT_N_S_soc_S_dma_40026000
#define DT_N_NODELABEL_dma1         DT_N_S_soc_S_dma_40026000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_dma_40026000_REG_NUM 1
#define DT_N_S_soc_S_dma_40026000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_REG_IDX_0_VAL_ADDRESS 1073897472 /* 0x40026000 */
#define DT_N_S_soc_S_dma_40026000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_dma_40026000_FOREACH_REG(fn) fn(DT_N_S_soc_S_dma_40026000, 0)
#define DT_N_S_soc_S_dma_40026000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40026000, 0)
#define DT_N_S_soc_S_dma_40026000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40026000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40026000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40026000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40026000_RANGES_NUM 0
#define DT_N_S_soc_S_dma_40026000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_dma_40026000_IRQ_NUM 8
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_0_VAL_irq 11
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_1_VAL_irq 12
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_2_VAL_irq 13
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_2_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_2_VAL_priority 0
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_2_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_2_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_3_VAL_irq 14
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_3_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_3_VAL_priority 0
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_3_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_3_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_4_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_4_VAL_irq 15
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_4_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_4_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_4_VAL_priority 0
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_4_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_4_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_5_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_5_VAL_irq 16
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_5_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_5_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_5_VAL_priority 0
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_5_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_5_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_6_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_6_VAL_irq 17
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_6_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_6_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_6_VAL_priority 0
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_6_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_6_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_7_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_7_VAL_irq 47
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_7_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_7_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_7_VAL_priority 0
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_7_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_IRQ_IDX_7_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40026000_IRQ_LEVEL 1
#define DT_N_S_soc_S_dma_40026000_COMPAT_MATCHES_st_stm32_dma_v1 1
#define DT_N_S_soc_S_dma_40026000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_dma_40026000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_COMPAT_MODEL_IDX_0 "stm32-dma-v1"
#define DT_N_S_soc_S_dma_40026000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_dma_40026000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_dma_40026000_P_reg {1073897472 /* 0x40026000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_dma_40026000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_reg_IDX_0 1073897472
#define DT_N_S_soc_S_dma_40026000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_dma_40026000_P_reg_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_interrupts {11 /* 0xb */, 0 /* 0x0 */, 12 /* 0xc */, 0 /* 0x0 */, 13 /* 0xd */, 0 /* 0x0 */, 14 /* 0xe */, 0 /* 0x0 */, 15 /* 0xf */, 0 /* 0x0 */, 16 /* 0x10 */, 0 /* 0x0 */, 17 /* 0x11 */, 0 /* 0x0 */, 47 /* 0x2f */, 0 /* 0x0 */}
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_0 11
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_2 12
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_4_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_4 13
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_5_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_5 0
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_6_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_6 14
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_7_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_7 0
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_8_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_8 15
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_9_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_9 0
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_10_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_10 16
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_11_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_11 0
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_12_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_12 17
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_13_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_13 0
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_14_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_14 47
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_15_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_interrupts_IDX_15 0
#define DT_N_S_soc_S_dma_40026000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_st_mem2mem 0
#define DT_N_S_soc_S_dma_40026000_P_st_mem2mem_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_status "disabled"
#define DT_N_S_soc_S_dma_40026000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_dma_40026000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_dma_40026000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_dma_40026000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_dma_40026000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_dma_40026000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40026000, status, 0)
#define DT_N_S_soc_S_dma_40026000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40026000, status, 0)
#define DT_N_S_soc_S_dma_40026000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40026000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40026000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40026000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40026000_P_status_LEN 1
#define DT_N_S_soc_S_dma_40026000_P_status_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_compatible {"st,stm32-dma-v1"}
#define DT_N_S_soc_S_dma_40026000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_compatible_IDX_0 "st,stm32-dma-v1"
#define DT_N_S_soc_S_dma_40026000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-dma-v1
#define DT_N_S_soc_S_dma_40026000_P_compatible_IDX_0_STRING_TOKEN st_stm32_dma_v1
#define DT_N_S_soc_S_dma_40026000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_DMA_V1
#define DT_N_S_soc_S_dma_40026000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40026000, compatible, 0)
#define DT_N_S_soc_S_dma_40026000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40026000, compatible, 0)
#define DT_N_S_soc_S_dma_40026000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40026000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40026000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40026000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40026000_P_compatible_LEN 1
#define DT_N_S_soc_S_dma_40026000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_dma_40026000_P_clocks_IDX_0_VAL_bus 48
#define DT_N_S_soc_S_dma_40026000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_clocks_IDX_0_VAL_bits 2097152
#define DT_N_S_soc_S_dma_40026000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_dma_40026000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_dma_40026000, clocks, 0, bits)
#define DT_N_S_soc_S_dma_40026000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40026000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_dma_40026000, clocks, 0, bits)
#define DT_N_S_soc_S_dma_40026000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_dma_40026000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40026000, clocks, 0)
#define DT_N_S_soc_S_dma_40026000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40026000, clocks, 0)
#define DT_N_S_soc_S_dma_40026000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40026000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40026000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40026000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40026000_P_clocks_LEN 1
#define DT_N_S_soc_S_dma_40026000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_dma_coherent 0
#define DT_N_S_soc_S_dma_40026000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_dma_40026000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_wakeup_source 0
#define DT_N_S_soc_S_dma_40026000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_dma_40026000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_dma_40026000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/i2s@40003800
 *
 * Node identifier: DT_N_S_soc_S_i2s_40003800
 *
 * Binding (compatible = st,stm32-i2s):
 *   $ZEPHYR_BASE\dts\bindings\i2s\st,stm32-i2s.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_i2s_40003800_PATH "/soc/i2s@40003800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_i2s_40003800_FULL_NAME "i2s@40003800"
#define DT_N_S_soc_S_i2s_40003800_FULL_NAME_UNQUOTED i2s@40003800
#define DT_N_S_soc_S_i2s_40003800_FULL_NAME_TOKEN i2s_40003800
#define DT_N_S_soc_S_i2s_40003800_FULL_NAME_UPPER_TOKEN I2S_40003800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_i2s_40003800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_i2s_40003800_CHILD_IDX 32

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_i2s_40003800_NODELABEL_NUM 1
#define DT_N_S_soc_S_i2s_40003800_FOREACH_NODELABEL(fn) fn(i2s2)
#define DT_N_S_soc_S_i2s_40003800_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2s2, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_i2s_40003800_CHILD_NUM 0
#define DT_N_S_soc_S_i2s_40003800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_i2s_40003800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_i2s_40003800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_i2s_40003800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2s_40003800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_i2s_40003800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_i2s_40003800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_i2s_40003800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2s_40003800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_i2s_40003800_HASH cv1l7gk621LLT8KlSAOD4ESjUxFIqs_KOzY0gVU3ofE

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_i2s_40003800_ORD 66
#define DT_N_S_soc_S_i2s_40003800_ORD_STR_SORTABLE 00066

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_i2s_40003800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	65, /* /soc/dma@40026000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_i2s_40003800_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_i2s_40003800_IDX_0_C_TOKEN i2s2

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_i2s_40003800_EXISTS 1
#define DT_N_INST_0_st_stm32_i2s DT_N_S_soc_S_i2s_40003800
#define DT_N_NODELABEL_i2s2      DT_N_S_soc_S_i2s_40003800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_i2s_40003800_REG_NUM 1
#define DT_N_S_soc_S_i2s_40003800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_REG_IDX_0_VAL_ADDRESS 1073756160 /* 0x40003800 */
#define DT_N_S_soc_S_i2s_40003800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_i2s_40003800_FOREACH_REG(fn) fn(DT_N_S_soc_S_i2s_40003800, 0)
#define DT_N_S_soc_S_i2s_40003800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003800, 0)
#define DT_N_S_soc_S_i2s_40003800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003800_RANGES_NUM 0
#define DT_N_S_soc_S_i2s_40003800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_i2s_40003800_IRQ_NUM 1
#define DT_N_S_soc_S_i2s_40003800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_IRQ_IDX_0_VAL_irq 36
#define DT_N_S_soc_S_i2s_40003800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_i2s_40003800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_i2s_40003800_IRQ_LEVEL 1
#define DT_N_S_soc_S_i2s_40003800_COMPAT_MATCHES_st_stm32_i2s 1
#define DT_N_S_soc_S_i2s_40003800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_i2s_40003800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_COMPAT_MODEL_IDX_0 "stm32-i2s"
#define DT_N_S_soc_S_i2s_40003800_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_i2s_40003800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_i2s_40003800_P_reg {1073756160 /* 0x40003800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_i2s_40003800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_reg_IDX_0 1073756160
#define DT_N_S_soc_S_i2s_40003800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_i2s_40003800_P_reg_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_interrupts {36 /* 0x24 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_i2s_40003800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_interrupts_IDX_0 36
#define DT_N_S_soc_S_i2s_40003800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_i2s_40003800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_PH DT_N_S_soc_S_dma_40026000
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_VAL_channel 4
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_VAL_slot 0
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_VAL_slot_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_VAL_channel_config 1024
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_VAL_channel_config_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_VAL_features 3
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_VAL_features_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_40003800, dmas, 0, channel) \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, 0, slot) \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, 0, channel-config) \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, 0, features)
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003800, dmas, 0, channel) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, 0, slot) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, 0, channel-config) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, 0, features)
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_NUM_CELLS 4
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_NAME "tx"
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_tx_IDX 0
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_tx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_40003800, dmas, tx, channel) \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, tx, slot) \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, tx, channel-config) \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, tx, features)
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_tx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003800, dmas, tx, channel) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, tx, slot) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, tx, channel-config) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, tx, features)
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_tx_NUM_CELLS 4
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_tx_PH DT_N_S_soc_S_dma_40026000
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_tx_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_tx_VAL_channel DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_VAL_channel
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_tx_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_tx_VAL_slot DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_VAL_slot
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_tx_VAL_slot_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_tx_VAL_channel_config DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_VAL_channel_config
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_tx_VAL_channel_config_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_tx_VAL_features DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_VAL_features
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_tx_VAL_features_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_1_PH DT_N_S_soc_S_dma_40026000
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_1_VAL_channel 3
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_1_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_1_VAL_slot 0
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_1_VAL_slot_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_1_VAL_channel_config 1024
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_1_VAL_channel_config_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_1_VAL_features 3
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_1_VAL_features_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_40003800, dmas, 1, channel) \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, 1, slot) \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, 1, channel-config) \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, 1, features)
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003800, dmas, 1, channel) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, 1, slot) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, 1, channel-config) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, 1, features)
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_1_NUM_CELLS 4
#define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_1_NAME "rx"
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_rx_IDX 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_rx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_40003800, dmas, rx, channel) \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, rx, slot) \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, rx, channel-config) \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, rx, features)
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_rx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003800, dmas, rx, channel) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, rx, slot) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, rx, channel-config) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, rx, features)
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_rx_NUM_CELLS 4
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_rx_PH DT_N_S_soc_S_dma_40026000
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_rx_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_rx_VAL_channel DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_1_VAL_channel
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_rx_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_rx_VAL_slot DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_1_VAL_slot
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_rx_VAL_slot_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_rx_VAL_channel_config DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_1_VAL_channel_config
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_rx_VAL_channel_config_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_rx_VAL_features DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_1_VAL_features
#define DT_N_S_soc_S_i2s_40003800_P_dmas_NAME_rx_VAL_features_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dmas_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003800, dmas, 0) \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, 1)
#define DT_N_S_soc_S_i2s_40003800_P_dmas_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003800, dmas, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, 1)
#define DT_N_S_soc_S_i2s_40003800_P_dmas_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003800, dmas, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003800_P_dmas_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003800, dmas, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003800, dmas, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003800_P_dmas_LEN 2
#define DT_N_S_soc_S_i2s_40003800_P_dmas_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dma_names {"tx", "rx"}
#define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_0 "tx"
#define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_0_STRING_UNQUOTED tx
#define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_0_STRING_TOKEN tx
#define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_0_STRING_UPPER_TOKEN TX
#define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_1 "rx"
#define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_1_STRING_UNQUOTED rx
#define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_1_STRING_TOKEN rx
#define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_1_STRING_UPPER_TOKEN RX
#define DT_N_S_soc_S_i2s_40003800_P_dma_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003800, dma_names, 0) \
	fn(DT_N_S_soc_S_i2s_40003800, dma_names, 1)
#define DT_N_S_soc_S_i2s_40003800_P_dma_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003800, dma_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003800, dma_names, 1)
#define DT_N_S_soc_S_i2s_40003800_P_dma_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003800, dma_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2s_40003800, dma_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003800_P_dma_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003800, dma_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003800, dma_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003800_P_dma_names_LEN 2
#define DT_N_S_soc_S_i2s_40003800_P_dma_names_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_mck_enabled 0
#define DT_N_S_soc_S_i2s_40003800_P_mck_enabled_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_ioswp 0
#define DT_N_S_soc_S_i2s_40003800_P_ioswp_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_status "disabled"
#define DT_N_S_soc_S_i2s_40003800_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_i2s_40003800_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_i2s_40003800_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_i2s_40003800_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_i2s_40003800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_i2s_40003800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003800, status, 0)
#define DT_N_S_soc_S_i2s_40003800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003800, status, 0)
#define DT_N_S_soc_S_i2s_40003800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003800_P_status_LEN 1
#define DT_N_S_soc_S_i2s_40003800_P_status_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_compatible {"st,stm32-i2s"}
#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_0 "st,stm32-i2s"
#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-i2s
#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_0_STRING_TOKEN st_stm32_i2s
#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_I2S
#define DT_N_S_soc_S_i2s_40003800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003800, compatible, 0)
#define DT_N_S_soc_S_i2s_40003800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003800, compatible, 0)
#define DT_N_S_soc_S_i2s_40003800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003800_P_compatible_LEN 1
#define DT_N_S_soc_S_i2s_40003800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_VAL_bits 16384
#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_40003800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_i2s_40003800, clocks, 0, bits)
#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003800, clocks, 0, bits)
#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_i2s_40003800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003800, clocks, 0)
#define DT_N_S_soc_S_i2s_40003800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003800, clocks, 0)
#define DT_N_S_soc_S_i2s_40003800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003800_P_clocks_LEN 1
#define DT_N_S_soc_S_i2s_40003800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_dma_coherent 0
#define DT_N_S_soc_S_i2s_40003800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_i2s_40003800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_wakeup_source 0
#define DT_N_S_soc_S_i2s_40003800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_i2s_40003800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_i2s_40003800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/i2s@40003c00
 *
 * Node identifier: DT_N_S_soc_S_i2s_40003c00
 *
 * Binding (compatible = st,stm32-i2s):
 *   $ZEPHYR_BASE\dts\bindings\i2s\st,stm32-i2s.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_i2s_40003c00_PATH "/soc/i2s@40003c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_i2s_40003c00_FULL_NAME "i2s@40003c00"
#define DT_N_S_soc_S_i2s_40003c00_FULL_NAME_UNQUOTED i2s@40003c00
#define DT_N_S_soc_S_i2s_40003c00_FULL_NAME_TOKEN i2s_40003c00
#define DT_N_S_soc_S_i2s_40003c00_FULL_NAME_UPPER_TOKEN I2S_40003C00

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_i2s_40003c00_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_i2s_40003c00_CHILD_IDX 33

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_i2s_40003c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_i2s_40003c00_FOREACH_NODELABEL(fn) fn(i2s3)
#define DT_N_S_soc_S_i2s_40003c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2s3, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_i2s_40003c00_CHILD_NUM 0
#define DT_N_S_soc_S_i2s_40003c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_i2s_40003c00_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_i2s_40003c00_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_i2s_40003c00_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2s_40003c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_i2s_40003c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_i2s_40003c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_i2s_40003c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2s_40003c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_i2s_40003c00_HASH cqu_NshQmISUpdQ_NZoLP2K_y7VkySXvopc7dRz2dUs

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_i2s_40003c00_ORD 67
#define DT_N_S_soc_S_i2s_40003c00_ORD_STR_SORTABLE 00067

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_i2s_40003c00_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	65, /* /soc/dma@40026000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_i2s_40003c00_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_i2s_40003c00_IDX_0_C_TOKEN i2s3

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_i2s_40003c00_EXISTS 1
#define DT_N_INST_1_st_stm32_i2s DT_N_S_soc_S_i2s_40003c00
#define DT_N_NODELABEL_i2s3      DT_N_S_soc_S_i2s_40003c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_i2s_40003c00_REG_NUM 1
#define DT_N_S_soc_S_i2s_40003c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_REG_IDX_0_VAL_ADDRESS 1073757184 /* 0x40003c00 */
#define DT_N_S_soc_S_i2s_40003c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_i2s_40003c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_i2s_40003c00, 0)
#define DT_N_S_soc_S_i2s_40003c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003c00, 0)
#define DT_N_S_soc_S_i2s_40003c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003c00_RANGES_NUM 0
#define DT_N_S_soc_S_i2s_40003c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_i2s_40003c00_IRQ_NUM 1
#define DT_N_S_soc_S_i2s_40003c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_IRQ_IDX_0_VAL_irq 51
#define DT_N_S_soc_S_i2s_40003c00_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_i2s_40003c00_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_i2s_40003c00_IRQ_LEVEL 1
#define DT_N_S_soc_S_i2s_40003c00_COMPAT_MATCHES_st_stm32_i2s 1
#define DT_N_S_soc_S_i2s_40003c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_i2s_40003c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_COMPAT_MODEL_IDX_0 "stm32-i2s"
#define DT_N_S_soc_S_i2s_40003c00_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_i2s_40003c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_i2s_40003c00_P_reg {1073757184 /* 0x40003c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_i2s_40003c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_reg_IDX_0 1073757184
#define DT_N_S_soc_S_i2s_40003c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_i2s_40003c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_interrupts {51 /* 0x33 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_i2s_40003c00_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_interrupts_IDX_0 51
#define DT_N_S_soc_S_i2s_40003c00_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_i2s_40003c00_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_PH DT_N_S_soc_S_dma_40026000
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_VAL_channel 5
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_VAL_slot 0
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_VAL_slot_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_VAL_channel_config 1024
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_VAL_channel_config_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_VAL_features 3
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_VAL_features_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_40003c00, dmas, 0, channel) \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, 0, slot) \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, 0, channel-config) \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, 0, features)
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003c00, dmas, 0, channel) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, 0, slot) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, 0, channel-config) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, 0, features)
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_NUM_CELLS 4
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_NAME "tx"
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_tx_IDX 0
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_tx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_40003c00, dmas, tx, channel) \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, tx, slot) \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, tx, channel-config) \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, tx, features)
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_tx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003c00, dmas, tx, channel) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, tx, slot) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, tx, channel-config) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, tx, features)
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_tx_NUM_CELLS 4
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_tx_PH DT_N_S_soc_S_dma_40026000
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_tx_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_tx_VAL_channel DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_VAL_channel
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_tx_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_tx_VAL_slot DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_VAL_slot
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_tx_VAL_slot_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_tx_VAL_channel_config DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_VAL_channel_config
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_tx_VAL_channel_config_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_tx_VAL_features DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_VAL_features
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_tx_VAL_features_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_1_PH DT_N_S_soc_S_dma_40026000
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_1_VAL_channel 0
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_1_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_1_VAL_slot 0
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_1_VAL_slot_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_1_VAL_channel_config 1024
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_1_VAL_channel_config_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_1_VAL_features 3
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_1_VAL_features_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_40003c00, dmas, 1, channel) \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, 1, slot) \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, 1, channel-config) \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, 1, features)
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003c00, dmas, 1, channel) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, 1, slot) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, 1, channel-config) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, 1, features)
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_1_NUM_CELLS 4
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_1_NAME "rx"
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_rx_IDX 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_rx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_40003c00, dmas, rx, channel) \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, rx, slot) \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, rx, channel-config) \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, rx, features)
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_rx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003c00, dmas, rx, channel) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, rx, slot) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, rx, channel-config) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, rx, features)
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_rx_NUM_CELLS 4
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_rx_PH DT_N_S_soc_S_dma_40026000
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_rx_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_rx_VAL_channel DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_1_VAL_channel
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_rx_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_rx_VAL_slot DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_1_VAL_slot
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_rx_VAL_slot_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_rx_VAL_channel_config DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_1_VAL_channel_config
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_rx_VAL_channel_config_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_rx_VAL_features DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_1_VAL_features
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_NAME_rx_VAL_features_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003c00, dmas, 0) \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, 1)
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003c00, dmas, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, 1)
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003c00, dmas, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003c00, dmas, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003c00, dmas, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_LEN 2
#define DT_N_S_soc_S_i2s_40003c00_P_dmas_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dma_names {"tx", "rx"}
#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_0 "tx"
#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_0_STRING_UNQUOTED tx
#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_0_STRING_TOKEN tx
#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_0_STRING_UPPER_TOKEN TX
#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_1 "rx"
#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_1_STRING_UNQUOTED rx
#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_1_STRING_TOKEN rx
#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_1_STRING_UPPER_TOKEN RX
#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003c00, dma_names, 0) \
	fn(DT_N_S_soc_S_i2s_40003c00, dma_names, 1)
#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003c00, dma_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003c00, dma_names, 1)
#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003c00, dma_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2s_40003c00, dma_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003c00, dma_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003c00, dma_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_LEN 2
#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_mck_enabled 0
#define DT_N_S_soc_S_i2s_40003c00_P_mck_enabled_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_ioswp 0
#define DT_N_S_soc_S_i2s_40003c00_P_ioswp_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_status "disabled"
#define DT_N_S_soc_S_i2s_40003c00_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_i2s_40003c00_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_i2s_40003c00_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_i2s_40003c00_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_i2s_40003c00_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_i2s_40003c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003c00, status, 0)
#define DT_N_S_soc_S_i2s_40003c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003c00, status, 0)
#define DT_N_S_soc_S_i2s_40003c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003c00_P_status_LEN 1
#define DT_N_S_soc_S_i2s_40003c00_P_status_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_compatible {"st,stm32-i2s"}
#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_0 "st,stm32-i2s"
#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-i2s
#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_i2s
#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_I2S
#define DT_N_S_soc_S_i2s_40003c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003c00, compatible, 0)
#define DT_N_S_soc_S_i2s_40003c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003c00, compatible, 0)
#define DT_N_S_soc_S_i2s_40003c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003c00_P_compatible_LEN 1
#define DT_N_S_soc_S_i2s_40003c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_VAL_bits 32768
#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_40003c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_i2s_40003c00, clocks, 0, bits)
#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_40003c00, clocks, 0, bits)
#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_i2s_40003c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003c00, clocks, 0)
#define DT_N_S_soc_S_i2s_40003c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003c00, clocks, 0)
#define DT_N_S_soc_S_i2s_40003c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40003c00_P_clocks_LEN 1
#define DT_N_S_soc_S_i2s_40003c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_dma_coherent 0
#define DT_N_S_soc_S_i2s_40003c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_i2s_40003c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_wakeup_source 0
#define DT_N_S_soc_S_i2s_40003c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_i2s_40003c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_i2s_40003c00_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/interrupt-controller@40013c00
 *
 * Node identifier: DT_N_S_soc_S_interrupt_controller_40013c00
 *
 * Binding (compatible = st,stm32-exti):
 *   $ZEPHYR_BASE\dts\bindings\interrupt-controller\st,stm32-exti.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_interrupt_controller_40013c00_PATH "/soc/interrupt-controller@40013c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_interrupt_controller_40013c00_FULL_NAME "interrupt-controller@40013c00"
#define DT_N_S_soc_S_interrupt_controller_40013c00_FULL_NAME_UNQUOTED interrupt-controller@40013c00
#define DT_N_S_soc_S_interrupt_controller_40013c00_FULL_NAME_TOKEN interrupt_controller_40013c00
#define DT_N_S_soc_S_interrupt_controller_40013c00_FULL_NAME_UPPER_TOKEN INTERRUPT_CONTROLLER_40013C00

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_interrupt_controller_40013c00_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_interrupt_controller_40013c00_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_interrupt_controller_40013c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_FOREACH_NODELABEL(fn) fn(exti)
#define DT_N_S_soc_S_interrupt_controller_40013c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(exti, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40013c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_interrupt_controller_40013c00_CHILD_NUM 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_interrupt_controller_40013c00_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_interrupt_controller_40013c00_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_interrupt_controller_40013c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_interrupt_controller_40013c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_interrupt_controller_40013c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_interrupt_controller_40013c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_interrupt_controller_40013c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_interrupt_controller_40013c00_HASH D1_x9QjyrJjMaczAc6IJiC3cw61e178jtvQ0qGa86ng

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_interrupt_controller_40013c00_ORD 68
#define DT_N_S_soc_S_interrupt_controller_40013c00_ORD_STR_SORTABLE 00068

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_interrupt_controller_40013c00_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_interrupt_controller_40013c00_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_interrupt_controller_40013c00_IDX_0_C_TOKEN exti

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_interrupt_controller_40013c00_EXISTS 1
#define DT_N_INST_0_st_stm32_exti DT_N_S_soc_S_interrupt_controller_40013c00
#define DT_N_NODELABEL_exti       DT_N_S_soc_S_interrupt_controller_40013c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_interrupt_controller_40013c00_REG_NUM 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_REG_IDX_0_VAL_ADDRESS 1073822720 /* 0x40013c00 */
#define DT_N_S_soc_S_interrupt_controller_40013c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_interrupt_controller_40013c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_interrupt_controller_40013c00, 0)
#define DT_N_S_soc_S_interrupt_controller_40013c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_40013c00, 0)
#define DT_N_S_soc_S_interrupt_controller_40013c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_40013c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40013c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_40013c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40013c00_RANGES_NUM 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NUM 7
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_0_VAL_irq 6
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_1_VAL_irq 7
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_2_VAL_irq 8
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_2_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_2_VAL_priority 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_2_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_2_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_3_VAL_irq 9
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_3_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_3_VAL_priority 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_3_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_3_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_4_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_4_VAL_irq 10
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_4_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_4_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_4_VAL_priority 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_4_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_4_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_5_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_5_VAL_irq 23
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_5_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_5_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_5_VAL_priority 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_5_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_5_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_6_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_6_VAL_irq 40
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_6_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_6_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_6_VAL_priority 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_6_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_6_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_LEVEL 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line0_VAL_irq DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line0_VAL_priority DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line0_CONTROLLER DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line1_VAL_irq DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_1_VAL_irq
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line1_VAL_priority DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_1_VAL_priority
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line1_CONTROLLER DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_1_CONTROLLER
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line2_VAL_irq DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_2_VAL_irq
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line2_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line2_VAL_priority DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_2_VAL_priority
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line2_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line2_CONTROLLER DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_2_CONTROLLER
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line3_VAL_irq DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_3_VAL_irq
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line3_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line3_VAL_priority DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_3_VAL_priority
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line3_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line3_CONTROLLER DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_3_CONTROLLER
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line4_VAL_irq DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_4_VAL_irq
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line4_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line4_VAL_priority DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_4_VAL_priority
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line4_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line4_CONTROLLER DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_4_CONTROLLER
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line5_9_VAL_irq DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_5_VAL_irq
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line5_9_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line5_9_VAL_priority DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_5_VAL_priority
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line5_9_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line5_9_CONTROLLER DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_5_CONTROLLER
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line10_15_VAL_irq DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_6_VAL_irq
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line10_15_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line10_15_VAL_priority DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_6_VAL_priority
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line10_15_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_NAME_line10_15_CONTROLLER DT_N_S_soc_S_interrupt_controller_40013c00_IRQ_IDX_6_CONTROLLER
#define DT_N_S_soc_S_interrupt_controller_40013c00_COMPAT_MATCHES_st_stm32_exti 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_interrupt_controller_40013c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_COMPAT_MODEL_IDX_0 "stm32-exti"
#define DT_N_S_soc_S_interrupt_controller_40013c00_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_interrupt_controller_40013c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_reg {1073822720 /* 0x40013c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_reg_IDX_0 1073822720
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts {6 /* 0x6 */, 0 /* 0x0 */, 7 /* 0x7 */, 0 /* 0x0 */, 8 /* 0x8 */, 0 /* 0x0 */, 9 /* 0x9 */, 0 /* 0x0 */, 10 /* 0xa */, 0 /* 0x0 */, 23 /* 0x17 */, 0 /* 0x0 */, 40 /* 0x28 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_0 6
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_2 7
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_4_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_4 8
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_5_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_5 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_6_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_6 9
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_7_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_7 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_8_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_8 10
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_9_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_9 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_10_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_10 23
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_11_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_11 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_12_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_12 40
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_13_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_IDX_13 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names {"line0", "line1", "line2", "line3", "line4", "line5-9", "line10-15"}
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_0 "line0"
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_0_STRING_UNQUOTED line0
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_0_STRING_TOKEN line0
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN LINE0
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_1 "line1"
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_1_STRING_UNQUOTED line1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_1_STRING_TOKEN line1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN LINE1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_2_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_2 "line2"
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_2_STRING_UNQUOTED line2
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_2_STRING_TOKEN line2
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN LINE2
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_3_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_3 "line3"
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_3_STRING_UNQUOTED line3
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_3_STRING_TOKEN line3
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_3_STRING_UPPER_TOKEN LINE3
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_4_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_4 "line4"
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_4_STRING_UNQUOTED line4
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_4_STRING_TOKEN line4
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_4_STRING_UPPER_TOKEN LINE4
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_5_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_5 "line5-9"
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_5_STRING_UNQUOTED line5-9
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_5_STRING_TOKEN line5_9
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_5_STRING_UPPER_TOKEN LINE5_9
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_6_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_6 "line10-15"
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_6_STRING_UNQUOTED line10-15
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_6_STRING_TOKEN line10_15
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_IDX_6_STRING_UPPER_TOKEN LINE10_15
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 0) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 1) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 2) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 3) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 4) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 5) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 6)
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 6)
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 6, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, interrupt_names, 6, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_LEN 7
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_num_lines 32
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_num_lines_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_num_gpio_lines 16
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_num_gpio_lines_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges {0 /* 0x0 */, 1 /* 0x1 */, 1 /* 0x1 */, 1 /* 0x1 */, 2 /* 0x2 */, 1 /* 0x1 */, 3 /* 0x3 */, 1 /* 0x1 */, 4 /* 0x4 */, 1 /* 0x1 */, 5 /* 0x5 */, 5 /* 0x5 */, 10 /* 0xa */, 6 /* 0x6 */}
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_0 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_1 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_2_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_2 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_3_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_3 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_4_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_4 2
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_5_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_5 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_6_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_6 3
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_7_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_7 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_8_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_8 4
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_9_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_9 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_10_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_10 5
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_11_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_11 5
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_12_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_12 10
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_13_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_IDX_13 6
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 0) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 1) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 2) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 3) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 4) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 5) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 6) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 7) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 8) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 9) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 10) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 11) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 12) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 13)
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 11) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 12) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 13)
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 7, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 8, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 9, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 10, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 11, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 12, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 13, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, line_ranges, 13, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_LEN 14
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_line_ranges_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_compatible {"st,stm32-exti"}
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_compatible_IDX_0 "st,stm32-exti"
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-exti
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_exti
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_EXTI
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_40013c00, compatible, 0)
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_40013c00, compatible, 0)
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_40013c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_40013c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_compatible_LEN 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_clocks_IDX_0_VAL_bus 68
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_clocks_IDX_0_VAL_bits 16384
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_interrupt_controller_40013c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, clocks, 0, bits)
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_40013c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40013c00, clocks, 0, bits)
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_40013c00, clocks, 0)
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_40013c00, clocks, 0)
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_40013c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_40013c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_clocks_LEN 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_dma_coherent 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_wakeup_source 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_controller 1
#define DT_N_S_soc_S_interrupt_controller_40013c00_P_interrupt_controller_EXISTS 1

/*
 * Devicetree node: /soc/memory@40024000
 *
 * Node identifier: DT_N_S_soc_S_memory_40024000
 *
 * Binding (compatible = zephyr,memory-region):
 *   $ZEPHYR_BASE\dts\bindings\base\zephyr,memory-region.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_memory_40024000_PATH "/soc/memory@40024000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_memory_40024000_FULL_NAME "memory@40024000"
#define DT_N_S_soc_S_memory_40024000_FULL_NAME_UNQUOTED memory@40024000
#define DT_N_S_soc_S_memory_40024000_FULL_NAME_TOKEN memory_40024000
#define DT_N_S_soc_S_memory_40024000_FULL_NAME_UPPER_TOKEN MEMORY_40024000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_40024000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_memory_40024000_CHILD_IDX 47

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_memory_40024000_NODELABEL_NUM 1
#define DT_N_S_soc_S_memory_40024000_FOREACH_NODELABEL(fn) fn(backup_sram)
#define DT_N_S_soc_S_memory_40024000_FOREACH_NODELABEL_VARGS(fn, ...) fn(backup_sram, __VA_ARGS__)
#define DT_N_S_soc_S_memory_40024000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_memory_40024000_CHILD_NUM 0
#define DT_N_S_soc_S_memory_40024000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_memory_40024000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_memory_40024000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_40024000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_40024000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_memory_40024000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_memory_40024000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_40024000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_40024000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_memory_40024000_HASH wAaXrPycrt1vnNwJNh8ek_QF4Gp_hQHLJnddP_2EzZo

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_40024000_ORD 69
#define DT_N_S_soc_S_memory_40024000_ORD_STR_SORTABLE 00069

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_40024000_REQUIRES_ORDS \
	4, /* /soc */ \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_40024000_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_memory_40024000_IDX_0_C_TOKEN backup_sram

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_40024000_EXISTS 1
#define DT_N_INST_2_zephyr_memory_region DT_N_S_soc_S_memory_40024000
#define DT_N_INST_0_st_stm32_backup_sram DT_N_S_soc_S_memory_40024000
#define DT_N_NODELABEL_backup_sram       DT_N_S_soc_S_memory_40024000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_memory_40024000_REG_NUM 1
#define DT_N_S_soc_S_memory_40024000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_REG_IDX_0_VAL_ADDRESS 1073889280 /* 0x40024000 */
#define DT_N_S_soc_S_memory_40024000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_memory_40024000_FOREACH_REG(fn) fn(DT_N_S_soc_S_memory_40024000, 0)
#define DT_N_S_soc_S_memory_40024000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_memory_40024000, 0)
#define DT_N_S_soc_S_memory_40024000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_40024000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_40024000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_40024000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_40024000_RANGES_NUM 0
#define DT_N_S_soc_S_memory_40024000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_memory_40024000_IRQ_NUM 0
#define DT_N_S_soc_S_memory_40024000_IRQ_LEVEL 0
#define DT_N_S_soc_S_memory_40024000_COMPAT_MATCHES_zephyr_memory_region 1
#define DT_N_S_soc_S_memory_40024000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_soc_S_memory_40024000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_COMPAT_MODEL_IDX_0 "memory-region"
#define DT_N_S_soc_S_memory_40024000_COMPAT_MATCHES_st_stm32_backup_sram 1
#define DT_N_S_soc_S_memory_40024000_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_memory_40024000_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_COMPAT_MODEL_IDX_1 "stm32-backup-sram"
#define DT_N_S_soc_S_memory_40024000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_memory_40024000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_memory_40024000_P_zephyr_memory_region "BACKUP_SRAM"
#define DT_N_S_soc_S_memory_40024000_P_zephyr_memory_region_STRING_UNQUOTED BACKUP_SRAM
#define DT_N_S_soc_S_memory_40024000_P_zephyr_memory_region_STRING_TOKEN BACKUP_SRAM
#define DT_N_S_soc_S_memory_40024000_P_zephyr_memory_region_STRING_UPPER_TOKEN BACKUP_SRAM
#define DT_N_S_soc_S_memory_40024000_P_zephyr_memory_region_IDX_0 "BACKUP_SRAM"
#define DT_N_S_soc_S_memory_40024000_P_zephyr_memory_region_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_40024000, zephyr_memory_region, 0)
#define DT_N_S_soc_S_memory_40024000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_40024000, zephyr_memory_region, 0)
#define DT_N_S_soc_S_memory_40024000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_40024000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_40024000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_40024000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_40024000_P_zephyr_memory_region_LEN 1
#define DT_N_S_soc_S_memory_40024000_P_zephyr_memory_region_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_status "disabled"
#define DT_N_S_soc_S_memory_40024000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_memory_40024000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_memory_40024000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_memory_40024000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_memory_40024000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_memory_40024000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_40024000, status, 0)
#define DT_N_S_soc_S_memory_40024000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_40024000, status, 0)
#define DT_N_S_soc_S_memory_40024000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_40024000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_40024000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_40024000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_40024000_P_status_LEN 1
#define DT_N_S_soc_S_memory_40024000_P_status_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_compatible {"zephyr,memory-region", "st,stm32-backup-sram"}
#define DT_N_S_soc_S_memory_40024000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_compatible_IDX_0 "zephyr,memory-region"
#define DT_N_S_soc_S_memory_40024000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,memory-region
#define DT_N_S_soc_S_memory_40024000_P_compatible_IDX_0_STRING_TOKEN zephyr_memory_region
#define DT_N_S_soc_S_memory_40024000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MEMORY_REGION
#define DT_N_S_soc_S_memory_40024000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_compatible_IDX_1 "st,stm32-backup-sram"
#define DT_N_S_soc_S_memory_40024000_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-backup-sram
#define DT_N_S_soc_S_memory_40024000_P_compatible_IDX_1_STRING_TOKEN st_stm32_backup_sram
#define DT_N_S_soc_S_memory_40024000_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_BACKUP_SRAM
#define DT_N_S_soc_S_memory_40024000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_40024000, compatible, 0) \
	fn(DT_N_S_soc_S_memory_40024000, compatible, 1)
#define DT_N_S_soc_S_memory_40024000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_40024000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_memory_40024000, compatible, 1)
#define DT_N_S_soc_S_memory_40024000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_40024000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_memory_40024000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_memory_40024000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_40024000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_memory_40024000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_memory_40024000_P_compatible_LEN 2
#define DT_N_S_soc_S_memory_40024000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_reg {1073889280 /* 0x40024000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_memory_40024000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_reg_IDX_0 1073889280
#define DT_N_S_soc_S_memory_40024000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_memory_40024000_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_memory_40024000_P_clocks_IDX_0_VAL_bus 48
#define DT_N_S_soc_S_memory_40024000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_clocks_IDX_0_VAL_bits 262144
#define DT_N_S_soc_S_memory_40024000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_memory_40024000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_memory_40024000, clocks, 0, bits)
#define DT_N_S_soc_S_memory_40024000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_memory_40024000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_memory_40024000, clocks, 0, bits)
#define DT_N_S_soc_S_memory_40024000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_memory_40024000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_40024000, clocks, 0)
#define DT_N_S_soc_S_memory_40024000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_40024000, clocks, 0)
#define DT_N_S_soc_S_memory_40024000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_40024000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_40024000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_40024000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_40024000_P_clocks_LEN 1
#define DT_N_S_soc_S_memory_40024000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_dma_coherent 0
#define DT_N_S_soc_S_memory_40024000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_memory_40024000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_wakeup_source 0
#define DT_N_S_soc_S_memory_40024000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_memory_40024000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_memory_40024000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/rng@50060800
 *
 * Node identifier: DT_N_S_soc_S_rng_50060800
 *
 * Binding (compatible = st,stm32-rng):
 *   $ZEPHYR_BASE\dts\bindings\rng\st,stm32-rng.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rng_50060800_PATH "/soc/rng@50060800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rng_50060800_FULL_NAME "rng@50060800"
#define DT_N_S_soc_S_rng_50060800_FULL_NAME_UNQUOTED rng@50060800
#define DT_N_S_soc_S_rng_50060800_FULL_NAME_TOKEN rng_50060800
#define DT_N_S_soc_S_rng_50060800_FULL_NAME_UPPER_TOKEN RNG_50060800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_rng_50060800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rng_50060800_CHILD_IDX 46

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_rng_50060800_NODELABEL_NUM 1
#define DT_N_S_soc_S_rng_50060800_FOREACH_NODELABEL(fn) fn(rng)
#define DT_N_S_soc_S_rng_50060800_FOREACH_NODELABEL_VARGS(fn, ...) fn(rng, __VA_ARGS__)
#define DT_N_S_soc_S_rng_50060800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rng_50060800_CHILD_NUM 0
#define DT_N_S_soc_S_rng_50060800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_rng_50060800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_rng_50060800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_rng_50060800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_rng_50060800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_rng_50060800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_rng_50060800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_rng_50060800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_rng_50060800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_rng_50060800_HASH 8eafQpG6YwQpjan2edsqJHU8l7DaDSiLzDM6EGAP_Uc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rng_50060800_ORD 70
#define DT_N_S_soc_S_rng_50060800_ORD_STR_SORTABLE 00070

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rng_50060800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rng_50060800_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_rng_50060800_IDX_0_C_TOKEN rng

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rng_50060800_EXISTS 1
#define DT_N_INST_0_st_stm32_rng DT_N_S_soc_S_rng_50060800
#define DT_N_NODELABEL_rng       DT_N_S_soc_S_rng_50060800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rng_50060800_REG_NUM 1
#define DT_N_S_soc_S_rng_50060800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_REG_IDX_0_VAL_ADDRESS 1342572544 /* 0x50060800 */
#define DT_N_S_soc_S_rng_50060800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_rng_50060800_FOREACH_REG(fn) fn(DT_N_S_soc_S_rng_50060800, 0)
#define DT_N_S_soc_S_rng_50060800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_rng_50060800, 0)
#define DT_N_S_soc_S_rng_50060800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_rng_50060800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rng_50060800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rng_50060800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rng_50060800_RANGES_NUM 0
#define DT_N_S_soc_S_rng_50060800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rng_50060800_IRQ_NUM 1
#define DT_N_S_soc_S_rng_50060800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_IRQ_IDX_0_VAL_irq 80
#define DT_N_S_soc_S_rng_50060800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_rng_50060800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_rng_50060800_IRQ_LEVEL 1
#define DT_N_S_soc_S_rng_50060800_COMPAT_MATCHES_st_stm32_rng 1
#define DT_N_S_soc_S_rng_50060800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_rng_50060800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_COMPAT_MODEL_IDX_0 "stm32-rng"
#define DT_N_S_soc_S_rng_50060800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rng_50060800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_rng_50060800_P_reg {1342572544 /* 0x50060800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_rng_50060800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_reg_IDX_0 1342572544
#define DT_N_S_soc_S_rng_50060800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_rng_50060800_P_reg_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_0_VAL_bus 52
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_0_VAL_bits 64
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_rng_50060800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_rng_50060800, clocks, 0, bits)
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_rng_50060800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_rng_50060800, clocks, 0, bits)
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_rng_50060800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rng_50060800, clocks, 0)
#define DT_N_S_soc_S_rng_50060800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rng_50060800, clocks, 0)
#define DT_N_S_soc_S_rng_50060800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rng_50060800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rng_50060800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rng_50060800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rng_50060800_P_clocks_LEN 1
#define DT_N_S_soc_S_rng_50060800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_status "okay"
#define DT_N_S_soc_S_rng_50060800_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_rng_50060800_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_rng_50060800_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_rng_50060800_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_rng_50060800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_rng_50060800_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rng_50060800, status, 0)
#define DT_N_S_soc_S_rng_50060800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rng_50060800, status, 0)
#define DT_N_S_soc_S_rng_50060800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rng_50060800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rng_50060800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rng_50060800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rng_50060800_P_status_LEN 1
#define DT_N_S_soc_S_rng_50060800_P_status_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_compatible {"st,stm32-rng"}
#define DT_N_S_soc_S_rng_50060800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_compatible_IDX_0 "st,stm32-rng"
#define DT_N_S_soc_S_rng_50060800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-rng
#define DT_N_S_soc_S_rng_50060800_P_compatible_IDX_0_STRING_TOKEN st_stm32_rng
#define DT_N_S_soc_S_rng_50060800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_RNG
#define DT_N_S_soc_S_rng_50060800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rng_50060800, compatible, 0)
#define DT_N_S_soc_S_rng_50060800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rng_50060800, compatible, 0)
#define DT_N_S_soc_S_rng_50060800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rng_50060800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rng_50060800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rng_50060800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rng_50060800_P_compatible_LEN 1
#define DT_N_S_soc_S_rng_50060800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_interrupts {80 /* 0x50 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_rng_50060800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_interrupts_IDX_0 80
#define DT_N_S_soc_S_rng_50060800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_rng_50060800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_dma_coherent 0
#define DT_N_S_soc_S_rng_50060800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_rng_50060800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_wakeup_source 0
#define DT_N_S_soc_S_rng_50060800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_rng_50060800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/sdmmc@40012c00
 *
 * Node identifier: DT_N_S_soc_S_sdmmc_40012c00
 *
 * Binding (compatible = st,stm32-sdmmc):
 *   $ZEPHYR_BASE\dts\bindings\mmc\st,stm32-sdmmc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_sdmmc_40012c00_PATH "/soc/sdmmc@40012c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_sdmmc_40012c00_FULL_NAME "sdmmc@40012c00"
#define DT_N_S_soc_S_sdmmc_40012c00_FULL_NAME_UNQUOTED sdmmc@40012c00
#define DT_N_S_soc_S_sdmmc_40012c00_FULL_NAME_TOKEN sdmmc_40012c00
#define DT_N_S_soc_S_sdmmc_40012c00_FULL_NAME_UPPER_TOKEN SDMMC_40012C00

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_sdmmc_40012c00_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_sdmmc_40012c00_CHILD_IDX 28

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_sdmmc_40012c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_sdmmc_40012c00_FOREACH_NODELABEL(fn) fn(sdmmc1)
#define DT_N_S_soc_S_sdmmc_40012c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(sdmmc1, __VA_ARGS__)
#define DT_N_S_soc_S_sdmmc_40012c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_sdmmc_40012c00_CHILD_NUM 0
#define DT_N_S_soc_S_sdmmc_40012c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_sdmmc_40012c00_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_sdmmc_40012c00_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_sdmmc_40012c00_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_sdmmc_40012c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_sdmmc_40012c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_sdmmc_40012c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_sdmmc_40012c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_sdmmc_40012c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_sdmmc_40012c00_HASH xfri0rTc26zpfwk6TyNA7IHMQROEEcx2XDFfjMBqbfA

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_sdmmc_40012c00_ORD 71
#define DT_N_S_soc_S_sdmmc_40012c00_ORD_STR_SORTABLE 00071

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_sdmmc_40012c00_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_sdmmc_40012c00_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_sdmmc_40012c00_IDX_0_C_TOKEN sdmmc1

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_sdmmc_40012c00_EXISTS 1
#define DT_N_INST_0_st_stm32_sdmmc DT_N_S_soc_S_sdmmc_40012c00
#define DT_N_NODELABEL_sdmmc1      DT_N_S_soc_S_sdmmc_40012c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_sdmmc_40012c00_REG_NUM 1
#define DT_N_S_soc_S_sdmmc_40012c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_REG_IDX_0_VAL_ADDRESS 1073818624 /* 0x40012c00 */
#define DT_N_S_soc_S_sdmmc_40012c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_sdmmc_40012c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_sdmmc_40012c00, 0)
#define DT_N_S_soc_S_sdmmc_40012c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_sdmmc_40012c00, 0)
#define DT_N_S_soc_S_sdmmc_40012c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_sdmmc_40012c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdmmc_40012c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdmmc_40012c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdmmc_40012c00_RANGES_NUM 0
#define DT_N_S_soc_S_sdmmc_40012c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_sdmmc_40012c00_IRQ_NUM 1
#define DT_N_S_soc_S_sdmmc_40012c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_IRQ_IDX_0_VAL_irq 49
#define DT_N_S_soc_S_sdmmc_40012c00_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_sdmmc_40012c00_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_sdmmc_40012c00_IRQ_LEVEL 1
#define DT_N_S_soc_S_sdmmc_40012c00_COMPAT_MATCHES_st_stm32_sdmmc 1
#define DT_N_S_soc_S_sdmmc_40012c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_sdmmc_40012c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_COMPAT_MODEL_IDX_0 "stm32-sdmmc"
#define DT_N_S_soc_S_sdmmc_40012c00_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_sdmmc_40012c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_IDX_0_VAL_bus 68
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_IDX_0_VAL_bits 2048
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_sdmmc_40012c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_sdmmc_40012c00, clocks, 0, bits)
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_sdmmc_40012c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_sdmmc_40012c00, clocks, 0, bits)
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_IDX_1_VAL_bus 7
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_sdmmc_40012c00, clocks, 1, bus) \
	fn(DT_N_S_soc_S_sdmmc_40012c00, clocks, 1, bits)
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_sdmmc_40012c00, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_sdmmc_40012c00, clocks, 1, bits)
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdmmc_40012c00, clocks, 0) \
	fn(DT_N_S_soc_S_sdmmc_40012c00, clocks, 1)
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdmmc_40012c00, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_sdmmc_40012c00, clocks, 1)
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdmmc_40012c00, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_sdmmc_40012c00, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdmmc_40012c00, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_sdmmc_40012c00, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_LEN 2
#define DT_N_S_soc_S_sdmmc_40012c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_reg {1073818624 /* 0x40012c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_sdmmc_40012c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_reg_IDX_0 1073818624
#define DT_N_S_soc_S_sdmmc_40012c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_sdmmc_40012c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_sdmmc_40012c00_P_resets_IDX_0_VAL_id 1163
#define DT_N_S_soc_S_sdmmc_40012c00_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_sdmmc_40012c00, resets, 0, id)
#define DT_N_S_soc_S_sdmmc_40012c00_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_sdmmc_40012c00, resets, 0, id)
#define DT_N_S_soc_S_sdmmc_40012c00_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdmmc_40012c00, resets, 0)
#define DT_N_S_soc_S_sdmmc_40012c00_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdmmc_40012c00, resets, 0)
#define DT_N_S_soc_S_sdmmc_40012c00_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdmmc_40012c00, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdmmc_40012c00_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdmmc_40012c00, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdmmc_40012c00_P_resets_LEN 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_resets_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_bus_width 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_bus_width_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_sdmmc_40012c00_P_bus_width_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_bus_width_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_bus_width_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_bus_width_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_clk_div 0
#define DT_N_S_soc_S_sdmmc_40012c00_P_clk_div_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_clk_bypass 0
#define DT_N_S_soc_S_sdmmc_40012c00_P_clk_bypass_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_idma 0
#define DT_N_S_soc_S_sdmmc_40012c00_P_idma_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_hw_flow_control 0
#define DT_N_S_soc_S_sdmmc_40012c00_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_support_1_8_v 0
#define DT_N_S_soc_S_sdmmc_40012c00_P_support_1_8_v_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_max_current_330 0
#define DT_N_S_soc_S_sdmmc_40012c00_P_max_current_330_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_max_current_300 0
#define DT_N_S_soc_S_sdmmc_40012c00_P_max_current_300_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_max_current_180 0
#define DT_N_S_soc_S_sdmmc_40012c00_P_max_current_180_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_max_bus_freq 400000
#define DT_N_S_soc_S_sdmmc_40012c00_P_max_bus_freq_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_min_bus_freq 400000
#define DT_N_S_soc_S_sdmmc_40012c00_P_min_bus_freq_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_power_delay_ms 500
#define DT_N_S_soc_S_sdmmc_40012c00_P_power_delay_ms_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_mmc_hs200_1_8v 0
#define DT_N_S_soc_S_sdmmc_40012c00_P_mmc_hs200_1_8v_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_mmc_hs400_1_8v 0
#define DT_N_S_soc_S_sdmmc_40012c00_P_mmc_hs400_1_8v_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_mmc_hs400_enhanced_strobe 0
#define DT_N_S_soc_S_sdmmc_40012c00_P_mmc_hs400_enhanced_strobe_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_status "disabled"
#define DT_N_S_soc_S_sdmmc_40012c00_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_sdmmc_40012c00_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_sdmmc_40012c00_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_sdmmc_40012c00_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_sdmmc_40012c00_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdmmc_40012c00, status, 0)
#define DT_N_S_soc_S_sdmmc_40012c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdmmc_40012c00, status, 0)
#define DT_N_S_soc_S_sdmmc_40012c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdmmc_40012c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdmmc_40012c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdmmc_40012c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdmmc_40012c00_P_status_LEN 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_status_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_compatible {"st,stm32-sdmmc"}
#define DT_N_S_soc_S_sdmmc_40012c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_compatible_IDX_0 "st,stm32-sdmmc"
#define DT_N_S_soc_S_sdmmc_40012c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-sdmmc
#define DT_N_S_soc_S_sdmmc_40012c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_sdmmc
#define DT_N_S_soc_S_sdmmc_40012c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SDMMC
#define DT_N_S_soc_S_sdmmc_40012c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdmmc_40012c00, compatible, 0)
#define DT_N_S_soc_S_sdmmc_40012c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdmmc_40012c00, compatible, 0)
#define DT_N_S_soc_S_sdmmc_40012c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdmmc_40012c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdmmc_40012c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdmmc_40012c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdmmc_40012c00_P_compatible_LEN 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_interrupts {49 /* 0x31 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_sdmmc_40012c00_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_interrupts_IDX_0 49
#define DT_N_S_soc_S_sdmmc_40012c00_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_sdmmc_40012c00_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_dma_coherent 0
#define DT_N_S_soc_S_sdmmc_40012c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_sdmmc_40012c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_wakeup_source 0
#define DT_N_S_soc_S_sdmmc_40012c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_sdmmc_40012c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_sdmmc_40012c00_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/serial@40004400
 *
 * Node identifier: DT_N_S_soc_S_serial_40004400
 *
 * Binding (compatible = st,stm32-usart):
 *   $ZEPHYR_BASE\dts\bindings\serial\st,stm32-usart.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_serial_40004400_PATH "/soc/serial@40004400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_serial_40004400_FULL_NAME "serial@40004400"
#define DT_N_S_soc_S_serial_40004400_FULL_NAME_UNQUOTED serial@40004400
#define DT_N_S_soc_S_serial_40004400_FULL_NAME_TOKEN serial_40004400
#define DT_N_S_soc_S_serial_40004400_FULL_NAME_UPPER_TOKEN SERIAL_40004400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_serial_40004400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_serial_40004400_CHILD_IDX 9

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_serial_40004400_NODELABEL_NUM 1
#define DT_N_S_soc_S_serial_40004400_FOREACH_NODELABEL(fn) fn(usart2)
#define DT_N_S_soc_S_serial_40004400_FOREACH_NODELABEL_VARGS(fn, ...) fn(usart2, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_serial_40004400_CHILD_NUM 0
#define DT_N_S_soc_S_serial_40004400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_serial_40004400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_serial_40004400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40004400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40004400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_serial_40004400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_serial_40004400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40004400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40004400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_serial_40004400_HASH w0whRjCvTBPyVty9dxjB3Bsl1nzzH1xRQTJifgUAAKQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_serial_40004400_ORD 72
#define DT_N_S_soc_S_serial_40004400_ORD_STR_SORTABLE 00072

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_serial_40004400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_serial_40004400_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_serial_40004400_IDX_0_C_TOKEN usart2

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_serial_40004400_EXISTS 1
#define DT_N_INST_3_st_stm32_usart DT_N_S_soc_S_serial_40004400
#define DT_N_INST_3_st_stm32_uart  DT_N_S_soc_S_serial_40004400
#define DT_N_NODELABEL_usart2      DT_N_S_soc_S_serial_40004400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_serial_40004400_REG_NUM 1
#define DT_N_S_soc_S_serial_40004400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_REG_IDX_0_VAL_ADDRESS 1073759232 /* 0x40004400 */
#define DT_N_S_soc_S_serial_40004400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_serial_40004400_FOREACH_REG(fn) fn(DT_N_S_soc_S_serial_40004400, 0)
#define DT_N_S_soc_S_serial_40004400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, 0)
#define DT_N_S_soc_S_serial_40004400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_RANGES_NUM 0
#define DT_N_S_soc_S_serial_40004400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_serial_40004400_IRQ_NUM 1
#define DT_N_S_soc_S_serial_40004400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_IRQ_IDX_0_VAL_irq 38
#define DT_N_S_soc_S_serial_40004400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_serial_40004400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_serial_40004400_IRQ_LEVEL 1
#define DT_N_S_soc_S_serial_40004400_COMPAT_MATCHES_st_stm32_usart 1
#define DT_N_S_soc_S_serial_40004400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40004400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_COMPAT_MODEL_IDX_0 "stm32-usart"
#define DT_N_S_soc_S_serial_40004400_COMPAT_MATCHES_st_stm32_uart 1
#define DT_N_S_soc_S_serial_40004400_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40004400_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_COMPAT_MODEL_IDX_1 "stm32-uart"
#define DT_N_S_soc_S_serial_40004400_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_serial_40004400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_serial_40004400_P_reg {1073759232 /* 0x40004400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_serial_40004400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_reg_IDX_0 1073759232
#define DT_N_S_soc_S_serial_40004400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_serial_40004400_P_reg_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_VAL_bits 131072
#define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40004400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_serial_40004400, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40004400, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_serial_40004400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, clocks, 0)
#define DT_N_S_soc_S_serial_40004400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, clocks, 0)
#define DT_N_S_soc_S_serial_40004400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_clocks_LEN 1
#define DT_N_S_soc_S_serial_40004400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_VAL_id 1041
#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40004400, resets, 0, id)
#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, resets, 0, id)
#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_serial_40004400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, resets, 0)
#define DT_N_S_soc_S_serial_40004400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, resets, 0)
#define DT_N_S_soc_S_serial_40004400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_resets_LEN 1
#define DT_N_S_soc_S_serial_40004400_P_resets_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_interrupts {38 /* 0x26 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_serial_40004400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_interrupts_IDX_0 38
#define DT_N_S_soc_S_serial_40004400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_serial_40004400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_current_speed 115200
#define DT_N_S_soc_S_serial_40004400_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_stop_bits "1"
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_STRING_UNQUOTED 1
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_STRING_TOKEN 1
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_STRING_UPPER_TOKEN 1
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_IDX_0 "1"
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, stop_bits, 0)
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, stop_bits, 0)
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_LEN 1
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_data_bits 8
#define DT_N_S_soc_S_serial_40004400_P_data_bits_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_serial_40004400_P_data_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_data_bits_IDX_0_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_data_bits_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_data_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_single_wire 0
#define DT_N_S_soc_S_serial_40004400_P_single_wire_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_tx_rx_swap 0
#define DT_N_S_soc_S_serial_40004400_P_tx_rx_swap_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_de_enable 0
#define DT_N_S_soc_S_serial_40004400_P_de_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_de_assert_time 0
#define DT_N_S_soc_S_serial_40004400_P_de_assert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_de_deassert_time 0
#define DT_N_S_soc_S_serial_40004400_P_de_deassert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_de_invert 0
#define DT_N_S_soc_S_serial_40004400_P_de_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_fifo_enable 0
#define DT_N_S_soc_S_serial_40004400_P_fifo_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_hw_flow_control 0
#define DT_N_S_soc_S_serial_40004400_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_parity "none"
#define DT_N_S_soc_S_serial_40004400_P_parity_STRING_UNQUOTED none
#define DT_N_S_soc_S_serial_40004400_P_parity_STRING_TOKEN none
#define DT_N_S_soc_S_serial_40004400_P_parity_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_serial_40004400_P_parity_IDX_0 "none"
#define DT_N_S_soc_S_serial_40004400_P_parity_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_parity_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_serial_40004400_P_parity_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_parity_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_parity_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, parity, 0)
#define DT_N_S_soc_S_serial_40004400_P_parity_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, parity, 0)
#define DT_N_S_soc_S_serial_40004400_P_parity_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_parity_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_parity_LEN 1
#define DT_N_S_soc_S_serial_40004400_P_parity_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_status "disabled"
#define DT_N_S_soc_S_serial_40004400_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_serial_40004400_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_serial_40004400_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_serial_40004400_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_serial_40004400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40004400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, status, 0)
#define DT_N_S_soc_S_serial_40004400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, status, 0)
#define DT_N_S_soc_S_serial_40004400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_status_LEN 1
#define DT_N_S_soc_S_serial_40004400_P_status_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_compatible {"st,stm32-usart", "st,stm32-uart"}
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0 "st,stm32-usart"
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-usart
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0_STRING_TOKEN st_stm32_usart
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_USART
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1 "st,stm32-uart"
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-uart
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1_STRING_TOKEN st_stm32_uart
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_UART
#define DT_N_S_soc_S_serial_40004400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, compatible, 0) \
	fn(DT_N_S_soc_S_serial_40004400, compatible, 1)
#define DT_N_S_soc_S_serial_40004400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40004400, compatible, 1)
#define DT_N_S_soc_S_serial_40004400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_serial_40004400, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40004400, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_compatible_LEN 2
#define DT_N_S_soc_S_serial_40004400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_dma_coherent 0
#define DT_N_S_soc_S_serial_40004400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_serial_40004400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_wakeup_source 0
#define DT_N_S_soc_S_serial_40004400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_serial_40004400_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_tx_invert 0
#define DT_N_S_soc_S_serial_40004400_P_tx_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_rx_invert 0
#define DT_N_S_soc_S_serial_40004400_P_rx_invert_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/usart3_rx_pd9
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_PATH "/soc/pin-controller@40020000/usart3_rx_pd9"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FULL_NAME "usart3_rx_pd9"
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FULL_NAME_UNQUOTED usart3_rx_pd9
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FULL_NAME_TOKEN usart3_rx_pd9
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FULL_NAME_UPPER_TOKEN USART3_RX_PD9

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_CHILD_IDX 30

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FOREACH_NODELABEL(fn) fn(usart3_rx_pd9)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FOREACH_NODELABEL_VARGS(fn, ...) fn(usart3_rx_pd9, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_HASH nCdR3BcwOGbOqa_s_VKvYQVRaQq56vagDOkYA0n_O6Y

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_ORD 73
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_ORD_STR_SORTABLE 00073

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_SUPPORTS_ORDS \
	75, /* /soc/serial@40004800 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_IDX_0_C_TOKEN usart3_rx_pd9

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_EXISTS 1
#define DT_N_NODELABEL_usart3_rx_pd9 DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_pinmux 1831
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/usart3_tx_pd8
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_PATH "/soc/pin-controller@40020000/usart3_tx_pd8"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FULL_NAME "usart3_tx_pd8"
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FULL_NAME_UNQUOTED usart3_tx_pd8
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FULL_NAME_TOKEN usart3_tx_pd8
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FULL_NAME_UPPER_TOKEN USART3_TX_PD8

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_CHILD_IDX 32

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FOREACH_NODELABEL(fn) fn(usart3_tx_pd8)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FOREACH_NODELABEL_VARGS(fn, ...) fn(usart3_tx_pd8, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_HASH CvU4O_56D9SAgjsMbRMYZii3NyGX7rSNN4FjfG9e7Xc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_ORD 74
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_ORD_STR_SORTABLE 00074

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_SUPPORTS_ORDS \
	75, /* /soc/serial@40004800 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_IDX_0_C_TOKEN usart3_tx_pd8

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_EXISTS 1
#define DT_N_NODELABEL_usart3_tx_pd8 DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_pinmux 1799
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_bias_pull_up 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/serial@40004800
 *
 * Node identifier: DT_N_S_soc_S_serial_40004800
 *
 * Binding (compatible = st,stm32-usart):
 *   $ZEPHYR_BASE\dts\bindings\serial\st,stm32-usart.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_serial_40004800_PATH "/soc/serial@40004800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_serial_40004800_FULL_NAME "serial@40004800"
#define DT_N_S_soc_S_serial_40004800_FULL_NAME_UNQUOTED serial@40004800
#define DT_N_S_soc_S_serial_40004800_FULL_NAME_TOKEN serial_40004800
#define DT_N_S_soc_S_serial_40004800_FULL_NAME_UPPER_TOKEN SERIAL_40004800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_serial_40004800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_serial_40004800_CHILD_IDX 34

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_serial_40004800_NODELABEL_NUM 1
#define DT_N_S_soc_S_serial_40004800_FOREACH_NODELABEL(fn) fn(usart3)
#define DT_N_S_soc_S_serial_40004800_FOREACH_NODELABEL_VARGS(fn, ...) fn(usart3, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_serial_40004800_CHILD_NUM 0
#define DT_N_S_soc_S_serial_40004800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_serial_40004800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_serial_40004800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40004800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40004800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_serial_40004800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_serial_40004800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40004800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40004800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_serial_40004800_HASH zEiuovs75QHyumn1pL5rvTd5x6H1bdnak278L4bYuj0

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_serial_40004800_ORD 75
#define DT_N_S_soc_S_serial_40004800_ORD_STR_SORTABLE 00075

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_serial_40004800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */ \
	73, /* /soc/pin-controller@40020000/usart3_rx_pd9 */ \
	74, /* /soc/pin-controller@40020000/usart3_tx_pd8 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_serial_40004800_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_serial_40004800_IDX_0_C_TOKEN usart3

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_serial_40004800_EXISTS 1
#define DT_N_INST_1_st_stm32_usart DT_N_S_soc_S_serial_40004800
#define DT_N_INST_1_st_stm32_uart  DT_N_S_soc_S_serial_40004800
#define DT_N_NODELABEL_usart3      DT_N_S_soc_S_serial_40004800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_serial_40004800_REG_NUM 1
#define DT_N_S_soc_S_serial_40004800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_REG_IDX_0_VAL_ADDRESS 1073760256 /* 0x40004800 */
#define DT_N_S_soc_S_serial_40004800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_serial_40004800_FOREACH_REG(fn) fn(DT_N_S_soc_S_serial_40004800, 0)
#define DT_N_S_soc_S_serial_40004800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, 0)
#define DT_N_S_soc_S_serial_40004800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_RANGES_NUM 0
#define DT_N_S_soc_S_serial_40004800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_serial_40004800_IRQ_NUM 1
#define DT_N_S_soc_S_serial_40004800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_IRQ_IDX_0_VAL_irq 39
#define DT_N_S_soc_S_serial_40004800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_serial_40004800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_serial_40004800_IRQ_LEVEL 1
#define DT_N_S_soc_S_serial_40004800_COMPAT_MATCHES_st_stm32_usart 1
#define DT_N_S_soc_S_serial_40004800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40004800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_COMPAT_MODEL_IDX_0 "stm32-usart"
#define DT_N_S_soc_S_serial_40004800_COMPAT_MATCHES_st_stm32_uart 1
#define DT_N_S_soc_S_serial_40004800_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40004800_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_COMPAT_MODEL_IDX_1 "stm32-uart"
#define DT_N_S_soc_S_serial_40004800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_serial_40004800_PINCTRL_NUM 1
#define DT_N_S_soc_S_serial_40004800_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_serial_40004800_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_serial_40004800_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_serial_40004800_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8
#define DT_N_S_soc_S_serial_40004800_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9

/* Generic property macros: */
#define DT_N_S_soc_S_serial_40004800_P_reg {1073760256 /* 0x40004800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_serial_40004800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_reg_IDX_0 1073760256
#define DT_N_S_soc_S_serial_40004800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_serial_40004800_P_reg_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_VAL_bits 262144
#define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40004800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_serial_40004800, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40004800, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_serial_40004800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004800, clocks, 0)
#define DT_N_S_soc_S_serial_40004800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, clocks, 0)
#define DT_N_S_soc_S_serial_40004800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_clocks_LEN 1
#define DT_N_S_soc_S_serial_40004800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_serial_40004800_P_resets_IDX_0_VAL_id 1042
#define DT_N_S_soc_S_serial_40004800_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40004800, resets, 0, id)
#define DT_N_S_soc_S_serial_40004800_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, resets, 0, id)
#define DT_N_S_soc_S_serial_40004800_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_serial_40004800_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004800, resets, 0)
#define DT_N_S_soc_S_serial_40004800_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, resets, 0)
#define DT_N_S_soc_S_serial_40004800_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_resets_LEN 1
#define DT_N_S_soc_S_serial_40004800_P_resets_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_interrupts {39 /* 0x27 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_serial_40004800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_interrupts_IDX_0 39
#define DT_N_S_soc_S_serial_40004800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_serial_40004800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_current_speed 115200
#define DT_N_S_soc_S_serial_40004800_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_stop_bits "1"
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_STRING_UNQUOTED 1
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_STRING_TOKEN 1
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_STRING_UPPER_TOKEN 1
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_IDX_0 "1"
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004800, stop_bits, 0)
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, stop_bits, 0)
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_LEN 1
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_data_bits 8
#define DT_N_S_soc_S_serial_40004800_P_data_bits_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_serial_40004800_P_data_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_data_bits_IDX_0_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_data_bits_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_data_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_single_wire 0
#define DT_N_S_soc_S_serial_40004800_P_single_wire_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_tx_rx_swap 0
#define DT_N_S_soc_S_serial_40004800_P_tx_rx_swap_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_0_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004800, pinctrl_0, 0) \
	fn(DT_N_S_soc_S_serial_40004800, pinctrl_0, 1)
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40004800, pinctrl_0, 1)
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, pinctrl_0, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_serial_40004800, pinctrl_0, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40004800, pinctrl_0, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_0_LEN 2
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004800, pinctrl_names, 0)
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, pinctrl_names, 0)
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_serial_40004800_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_de_enable 0
#define DT_N_S_soc_S_serial_40004800_P_de_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_de_assert_time 0
#define DT_N_S_soc_S_serial_40004800_P_de_assert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_de_deassert_time 0
#define DT_N_S_soc_S_serial_40004800_P_de_deassert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_de_invert 0
#define DT_N_S_soc_S_serial_40004800_P_de_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_fifo_enable 0
#define DT_N_S_soc_S_serial_40004800_P_fifo_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_hw_flow_control 0
#define DT_N_S_soc_S_serial_40004800_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_parity "none"
#define DT_N_S_soc_S_serial_40004800_P_parity_STRING_UNQUOTED none
#define DT_N_S_soc_S_serial_40004800_P_parity_STRING_TOKEN none
#define DT_N_S_soc_S_serial_40004800_P_parity_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_serial_40004800_P_parity_IDX_0 "none"
#define DT_N_S_soc_S_serial_40004800_P_parity_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_parity_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_serial_40004800_P_parity_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_parity_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_parity_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004800, parity, 0)
#define DT_N_S_soc_S_serial_40004800_P_parity_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, parity, 0)
#define DT_N_S_soc_S_serial_40004800_P_parity_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_parity_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_parity_LEN 1
#define DT_N_S_soc_S_serial_40004800_P_parity_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_status "okay"
#define DT_N_S_soc_S_serial_40004800_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_serial_40004800_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_serial_40004800_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_serial_40004800_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_serial_40004800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_serial_40004800_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004800, status, 0)
#define DT_N_S_soc_S_serial_40004800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, status, 0)
#define DT_N_S_soc_S_serial_40004800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_status_LEN 1
#define DT_N_S_soc_S_serial_40004800_P_status_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_compatible {"st,stm32-usart", "st,stm32-uart"}
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0 "st,stm32-usart"
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-usart
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0_STRING_TOKEN st_stm32_usart
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_USART
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1 "st,stm32-uart"
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-uart
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1_STRING_TOKEN st_stm32_uart
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_UART
#define DT_N_S_soc_S_serial_40004800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004800, compatible, 0) \
	fn(DT_N_S_soc_S_serial_40004800, compatible, 1)
#define DT_N_S_soc_S_serial_40004800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40004800, compatible, 1)
#define DT_N_S_soc_S_serial_40004800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_serial_40004800, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40004800, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_compatible_LEN 2
#define DT_N_S_soc_S_serial_40004800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_dma_coherent 0
#define DT_N_S_soc_S_serial_40004800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_serial_40004800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_wakeup_source 0
#define DT_N_S_soc_S_serial_40004800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_serial_40004800_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_tx_invert 0
#define DT_N_S_soc_S_serial_40004800_P_tx_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_rx_invert 0
#define DT_N_S_soc_S_serial_40004800_P_rx_invert_EXISTS 1

/*
 * Devicetree node: /soc/serial@40004c00
 *
 * Node identifier: DT_N_S_soc_S_serial_40004c00
 *
 * Binding (compatible = st,stm32-uart):
 *   $ZEPHYR_BASE\dts\bindings\serial\st,stm32-uart.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_serial_40004c00_PATH "/soc/serial@40004c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_serial_40004c00_FULL_NAME "serial@40004c00"
#define DT_N_S_soc_S_serial_40004c00_FULL_NAME_UNQUOTED serial@40004c00
#define DT_N_S_soc_S_serial_40004c00_FULL_NAME_TOKEN serial_40004c00
#define DT_N_S_soc_S_serial_40004c00_FULL_NAME_UPPER_TOKEN SERIAL_40004C00

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_serial_40004c00_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_serial_40004c00_CHILD_IDX 35

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_serial_40004c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_serial_40004c00_FOREACH_NODELABEL(fn) fn(uart4)
#define DT_N_S_soc_S_serial_40004c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart4, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_serial_40004c00_CHILD_NUM 0
#define DT_N_S_soc_S_serial_40004c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_serial_40004c00_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_serial_40004c00_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40004c00_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40004c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_serial_40004c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_serial_40004c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40004c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40004c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_serial_40004c00_HASH qw6sySCqGO4wCPwXm_EFlFNv1NqVYdGrZFXhKaRqK7U

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_serial_40004c00_ORD 76
#define DT_N_S_soc_S_serial_40004c00_ORD_STR_SORTABLE 00076

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_serial_40004c00_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_serial_40004c00_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_serial_40004c00_IDX_0_C_TOKEN uart4

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_serial_40004c00_EXISTS 1
#define DT_N_INST_4_st_stm32_uart DT_N_S_soc_S_serial_40004c00
#define DT_N_NODELABEL_uart4      DT_N_S_soc_S_serial_40004c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_serial_40004c00_REG_NUM 1
#define DT_N_S_soc_S_serial_40004c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_REG_IDX_0_VAL_ADDRESS 1073761280 /* 0x40004c00 */
#define DT_N_S_soc_S_serial_40004c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_serial_40004c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_serial_40004c00, 0)
#define DT_N_S_soc_S_serial_40004c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, 0)
#define DT_N_S_soc_S_serial_40004c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_RANGES_NUM 0
#define DT_N_S_soc_S_serial_40004c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_serial_40004c00_IRQ_NUM 1
#define DT_N_S_soc_S_serial_40004c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_IRQ_IDX_0_VAL_irq 52
#define DT_N_S_soc_S_serial_40004c00_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_serial_40004c00_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_serial_40004c00_IRQ_LEVEL 1
#define DT_N_S_soc_S_serial_40004c00_COMPAT_MATCHES_st_stm32_uart 1
#define DT_N_S_soc_S_serial_40004c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40004c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_COMPAT_MODEL_IDX_0 "stm32-uart"
#define DT_N_S_soc_S_serial_40004c00_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_serial_40004c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_serial_40004c00_P_reg {1073761280 /* 0x40004c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_serial_40004c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_reg_IDX_0 1073761280
#define DT_N_S_soc_S_serial_40004c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_serial_40004c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_VAL_bits 524288
#define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40004c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_serial_40004c00, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40004c00, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_serial_40004c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, clocks, 0)
#define DT_N_S_soc_S_serial_40004c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, clocks, 0)
#define DT_N_S_soc_S_serial_40004c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_clocks_LEN 1
#define DT_N_S_soc_S_serial_40004c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_VAL_id 1043
#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40004c00, resets, 0, id)
#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, resets, 0, id)
#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_serial_40004c00_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, resets, 0)
#define DT_N_S_soc_S_serial_40004c00_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, resets, 0)
#define DT_N_S_soc_S_serial_40004c00_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_resets_LEN 1
#define DT_N_S_soc_S_serial_40004c00_P_resets_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_interrupts {52 /* 0x34 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_serial_40004c00_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_interrupts_IDX_0 52
#define DT_N_S_soc_S_serial_40004c00_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_serial_40004c00_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_current_speed 115200
#define DT_N_S_soc_S_serial_40004c00_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits "1"
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_STRING_UNQUOTED 1
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_STRING_TOKEN 1
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_STRING_UPPER_TOKEN 1
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_IDX_0 "1"
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, stop_bits, 0)
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, stop_bits, 0)
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_LEN 1
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_data_bits 8
#define DT_N_S_soc_S_serial_40004c00_P_data_bits_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_serial_40004c00_P_data_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_data_bits_IDX_0_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_data_bits_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_data_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_single_wire 0
#define DT_N_S_soc_S_serial_40004c00_P_single_wire_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_tx_rx_swap 0
#define DT_N_S_soc_S_serial_40004c00_P_tx_rx_swap_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_de_enable 0
#define DT_N_S_soc_S_serial_40004c00_P_de_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_de_assert_time 0
#define DT_N_S_soc_S_serial_40004c00_P_de_assert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_de_deassert_time 0
#define DT_N_S_soc_S_serial_40004c00_P_de_deassert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_de_invert 0
#define DT_N_S_soc_S_serial_40004c00_P_de_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_fifo_enable 0
#define DT_N_S_soc_S_serial_40004c00_P_fifo_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_hw_flow_control 0
#define DT_N_S_soc_S_serial_40004c00_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_parity "none"
#define DT_N_S_soc_S_serial_40004c00_P_parity_STRING_UNQUOTED none
#define DT_N_S_soc_S_serial_40004c00_P_parity_STRING_TOKEN none
#define DT_N_S_soc_S_serial_40004c00_P_parity_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_serial_40004c00_P_parity_IDX_0 "none"
#define DT_N_S_soc_S_serial_40004c00_P_parity_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_parity_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_serial_40004c00_P_parity_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_parity_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_parity_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, parity, 0)
#define DT_N_S_soc_S_serial_40004c00_P_parity_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, parity, 0)
#define DT_N_S_soc_S_serial_40004c00_P_parity_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_parity_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_parity_LEN 1
#define DT_N_S_soc_S_serial_40004c00_P_parity_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_status "disabled"
#define DT_N_S_soc_S_serial_40004c00_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_serial_40004c00_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_serial_40004c00_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_serial_40004c00_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_serial_40004c00_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40004c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, status, 0)
#define DT_N_S_soc_S_serial_40004c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, status, 0)
#define DT_N_S_soc_S_serial_40004c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_status_LEN 1
#define DT_N_S_soc_S_serial_40004c00_P_status_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_compatible {"st,stm32-uart"}
#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0 "st,stm32-uart"
#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-uart
#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_uart
#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_UART
#define DT_N_S_soc_S_serial_40004c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, compatible, 0)
#define DT_N_S_soc_S_serial_40004c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, compatible, 0)
#define DT_N_S_soc_S_serial_40004c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_compatible_LEN 1
#define DT_N_S_soc_S_serial_40004c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_dma_coherent 0
#define DT_N_S_soc_S_serial_40004c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_serial_40004c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_wakeup_source 0
#define DT_N_S_soc_S_serial_40004c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_serial_40004c00_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_tx_invert 0
#define DT_N_S_soc_S_serial_40004c00_P_tx_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_rx_invert 0
#define DT_N_S_soc_S_serial_40004c00_P_rx_invert_EXISTS 1

/*
 * Devicetree node: /soc/serial@40005000
 *
 * Node identifier: DT_N_S_soc_S_serial_40005000
 *
 * Binding (compatible = st,stm32-uart):
 *   $ZEPHYR_BASE\dts\bindings\serial\st,stm32-uart.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_serial_40005000_PATH "/soc/serial@40005000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_serial_40005000_FULL_NAME "serial@40005000"
#define DT_N_S_soc_S_serial_40005000_FULL_NAME_UNQUOTED serial@40005000
#define DT_N_S_soc_S_serial_40005000_FULL_NAME_TOKEN serial_40005000
#define DT_N_S_soc_S_serial_40005000_FULL_NAME_UPPER_TOKEN SERIAL_40005000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_serial_40005000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_serial_40005000_CHILD_IDX 36

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_serial_40005000_NODELABEL_NUM 1
#define DT_N_S_soc_S_serial_40005000_FOREACH_NODELABEL(fn) fn(uart5)
#define DT_N_S_soc_S_serial_40005000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart5, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40005000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_serial_40005000_CHILD_NUM 0
#define DT_N_S_soc_S_serial_40005000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_serial_40005000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_serial_40005000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40005000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40005000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_serial_40005000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_serial_40005000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40005000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40005000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_serial_40005000_HASH zMMX5P6gmfqIczU7IzsjM4mPclQdCNjtpO0LqCzLhTI

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_serial_40005000_ORD 77
#define DT_N_S_soc_S_serial_40005000_ORD_STR_SORTABLE 00077

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_serial_40005000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_serial_40005000_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_serial_40005000_IDX_0_C_TOKEN uart5

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_serial_40005000_EXISTS 1
#define DT_N_INST_5_st_stm32_uart DT_N_S_soc_S_serial_40005000
#define DT_N_NODELABEL_uart5      DT_N_S_soc_S_serial_40005000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_serial_40005000_REG_NUM 1
#define DT_N_S_soc_S_serial_40005000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_REG_IDX_0_VAL_ADDRESS 1073762304 /* 0x40005000 */
#define DT_N_S_soc_S_serial_40005000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_serial_40005000_FOREACH_REG(fn) fn(DT_N_S_soc_S_serial_40005000, 0)
#define DT_N_S_soc_S_serial_40005000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40005000, 0)
#define DT_N_S_soc_S_serial_40005000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40005000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40005000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40005000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40005000_RANGES_NUM 0
#define DT_N_S_soc_S_serial_40005000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_serial_40005000_IRQ_NUM 1
#define DT_N_S_soc_S_serial_40005000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_IRQ_IDX_0_VAL_irq 53
#define DT_N_S_soc_S_serial_40005000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_serial_40005000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_serial_40005000_IRQ_LEVEL 1
#define DT_N_S_soc_S_serial_40005000_COMPAT_MATCHES_st_stm32_uart 1
#define DT_N_S_soc_S_serial_40005000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40005000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_COMPAT_MODEL_IDX_0 "stm32-uart"
#define DT_N_S_soc_S_serial_40005000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_serial_40005000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_serial_40005000_P_reg {1073762304 /* 0x40005000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_serial_40005000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_reg_IDX_0 1073762304
#define DT_N_S_soc_S_serial_40005000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_serial_40005000_P_reg_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_serial_40005000_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_serial_40005000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_clocks_IDX_0_VAL_bits 1048576
#define DT_N_S_soc_S_serial_40005000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40005000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_serial_40005000, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40005000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40005000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40005000, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40005000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_serial_40005000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40005000, clocks, 0)
#define DT_N_S_soc_S_serial_40005000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40005000, clocks, 0)
#define DT_N_S_soc_S_serial_40005000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40005000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40005000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40005000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40005000_P_clocks_LEN 1
#define DT_N_S_soc_S_serial_40005000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_serial_40005000_P_resets_IDX_0_VAL_id 1044
#define DT_N_S_soc_S_serial_40005000_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40005000, resets, 0, id)
#define DT_N_S_soc_S_serial_40005000_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40005000, resets, 0, id)
#define DT_N_S_soc_S_serial_40005000_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_serial_40005000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40005000, resets, 0)
#define DT_N_S_soc_S_serial_40005000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40005000, resets, 0)
#define DT_N_S_soc_S_serial_40005000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40005000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40005000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40005000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40005000_P_resets_LEN 1
#define DT_N_S_soc_S_serial_40005000_P_resets_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_interrupts {53 /* 0x35 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_serial_40005000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_interrupts_IDX_0 53
#define DT_N_S_soc_S_serial_40005000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_serial_40005000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_current_speed 115200
#define DT_N_S_soc_S_serial_40005000_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_stop_bits "1"
#define DT_N_S_soc_S_serial_40005000_P_stop_bits_STRING_UNQUOTED 1
#define DT_N_S_soc_S_serial_40005000_P_stop_bits_STRING_TOKEN 1
#define DT_N_S_soc_S_serial_40005000_P_stop_bits_STRING_UPPER_TOKEN 1
#define DT_N_S_soc_S_serial_40005000_P_stop_bits_IDX_0 "1"
#define DT_N_S_soc_S_serial_40005000_P_stop_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_stop_bits_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40005000_P_stop_bits_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_stop_bits_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_stop_bits_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40005000, stop_bits, 0)
#define DT_N_S_soc_S_serial_40005000_P_stop_bits_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40005000, stop_bits, 0)
#define DT_N_S_soc_S_serial_40005000_P_stop_bits_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40005000, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40005000_P_stop_bits_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40005000, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40005000_P_stop_bits_LEN 1
#define DT_N_S_soc_S_serial_40005000_P_stop_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_data_bits 8
#define DT_N_S_soc_S_serial_40005000_P_data_bits_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_serial_40005000_P_data_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_data_bits_IDX_0_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_data_bits_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_data_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_single_wire 0
#define DT_N_S_soc_S_serial_40005000_P_single_wire_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_tx_rx_swap 0
#define DT_N_S_soc_S_serial_40005000_P_tx_rx_swap_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_de_enable 0
#define DT_N_S_soc_S_serial_40005000_P_de_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_de_assert_time 0
#define DT_N_S_soc_S_serial_40005000_P_de_assert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_de_deassert_time 0
#define DT_N_S_soc_S_serial_40005000_P_de_deassert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_de_invert 0
#define DT_N_S_soc_S_serial_40005000_P_de_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_fifo_enable 0
#define DT_N_S_soc_S_serial_40005000_P_fifo_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_hw_flow_control 0
#define DT_N_S_soc_S_serial_40005000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_parity "none"
#define DT_N_S_soc_S_serial_40005000_P_parity_STRING_UNQUOTED none
#define DT_N_S_soc_S_serial_40005000_P_parity_STRING_TOKEN none
#define DT_N_S_soc_S_serial_40005000_P_parity_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_serial_40005000_P_parity_IDX_0 "none"
#define DT_N_S_soc_S_serial_40005000_P_parity_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_parity_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_serial_40005000_P_parity_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_parity_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_parity_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40005000, parity, 0)
#define DT_N_S_soc_S_serial_40005000_P_parity_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40005000, parity, 0)
#define DT_N_S_soc_S_serial_40005000_P_parity_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40005000, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40005000_P_parity_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40005000, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40005000_P_parity_LEN 1
#define DT_N_S_soc_S_serial_40005000_P_parity_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_status "disabled"
#define DT_N_S_soc_S_serial_40005000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_serial_40005000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_serial_40005000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_serial_40005000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_serial_40005000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40005000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40005000, status, 0)
#define DT_N_S_soc_S_serial_40005000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40005000, status, 0)
#define DT_N_S_soc_S_serial_40005000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40005000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40005000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40005000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40005000_P_status_LEN 1
#define DT_N_S_soc_S_serial_40005000_P_status_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_compatible {"st,stm32-uart"}
#define DT_N_S_soc_S_serial_40005000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_compatible_IDX_0 "st,stm32-uart"
#define DT_N_S_soc_S_serial_40005000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-uart
#define DT_N_S_soc_S_serial_40005000_P_compatible_IDX_0_STRING_TOKEN st_stm32_uart
#define DT_N_S_soc_S_serial_40005000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_UART
#define DT_N_S_soc_S_serial_40005000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40005000, compatible, 0)
#define DT_N_S_soc_S_serial_40005000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40005000, compatible, 0)
#define DT_N_S_soc_S_serial_40005000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40005000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40005000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40005000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40005000_P_compatible_LEN 1
#define DT_N_S_soc_S_serial_40005000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_dma_coherent 0
#define DT_N_S_soc_S_serial_40005000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_serial_40005000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_wakeup_source 0
#define DT_N_S_soc_S_serial_40005000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_serial_40005000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_tx_invert 0
#define DT_N_S_soc_S_serial_40005000_P_tx_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40005000_P_rx_invert 0
#define DT_N_S_soc_S_serial_40005000_P_rx_invert_EXISTS 1

/*
 * Devicetree node: /soc/serial@40007800
 *
 * Node identifier: DT_N_S_soc_S_serial_40007800
 *
 * Binding (compatible = st,stm32-uart):
 *   $ZEPHYR_BASE\dts\bindings\serial\st,stm32-uart.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_serial_40007800_PATH "/soc/serial@40007800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_serial_40007800_FULL_NAME "serial@40007800"
#define DT_N_S_soc_S_serial_40007800_FULL_NAME_UNQUOTED serial@40007800
#define DT_N_S_soc_S_serial_40007800_FULL_NAME_TOKEN serial_40007800
#define DT_N_S_soc_S_serial_40007800_FULL_NAME_UPPER_TOKEN SERIAL_40007800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_serial_40007800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_serial_40007800_CHILD_IDX 52

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_serial_40007800_NODELABEL_NUM 1
#define DT_N_S_soc_S_serial_40007800_FOREACH_NODELABEL(fn) fn(uart7)
#define DT_N_S_soc_S_serial_40007800_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart7, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_serial_40007800_CHILD_NUM 0
#define DT_N_S_soc_S_serial_40007800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_serial_40007800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_serial_40007800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40007800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40007800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_serial_40007800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_serial_40007800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40007800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40007800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_serial_40007800_HASH B1n8AhUVQ1w9M632DgTYUTge_yAZlcZs3gBpMVS0S2o

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_serial_40007800_ORD 78
#define DT_N_S_soc_S_serial_40007800_ORD_STR_SORTABLE 00078

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_serial_40007800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_serial_40007800_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_serial_40007800_IDX_0_C_TOKEN uart7

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_serial_40007800_EXISTS 1
#define DT_N_INST_6_st_stm32_uart DT_N_S_soc_S_serial_40007800
#define DT_N_NODELABEL_uart7      DT_N_S_soc_S_serial_40007800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_serial_40007800_REG_NUM 1
#define DT_N_S_soc_S_serial_40007800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_REG_IDX_0_VAL_ADDRESS 1073772544 /* 0x40007800 */
#define DT_N_S_soc_S_serial_40007800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_serial_40007800_FOREACH_REG(fn) fn(DT_N_S_soc_S_serial_40007800, 0)
#define DT_N_S_soc_S_serial_40007800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800, 0)
#define DT_N_S_soc_S_serial_40007800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007800_RANGES_NUM 0
#define DT_N_S_soc_S_serial_40007800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_serial_40007800_IRQ_NUM 1
#define DT_N_S_soc_S_serial_40007800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_IRQ_IDX_0_VAL_irq 82
#define DT_N_S_soc_S_serial_40007800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_serial_40007800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_serial_40007800_IRQ_LEVEL 1
#define DT_N_S_soc_S_serial_40007800_COMPAT_MATCHES_st_stm32_uart 1
#define DT_N_S_soc_S_serial_40007800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40007800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_COMPAT_MODEL_IDX_0 "stm32-uart"
#define DT_N_S_soc_S_serial_40007800_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_serial_40007800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_serial_40007800_P_reg {1073772544 /* 0x40007800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_serial_40007800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_reg_IDX_0 1073772544
#define DT_N_S_soc_S_serial_40007800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_serial_40007800_P_reg_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_serial_40007800_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_serial_40007800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_clocks_IDX_0_VAL_bits 1073741824
#define DT_N_S_soc_S_serial_40007800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40007800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_serial_40007800, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40007800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40007800, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40007800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_serial_40007800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800, clocks, 0)
#define DT_N_S_soc_S_serial_40007800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800, clocks, 0)
#define DT_N_S_soc_S_serial_40007800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007800_P_clocks_LEN 1
#define DT_N_S_soc_S_serial_40007800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_serial_40007800_P_resets_IDX_0_VAL_id 1054
#define DT_N_S_soc_S_serial_40007800_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40007800, resets, 0, id)
#define DT_N_S_soc_S_serial_40007800_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800, resets, 0, id)
#define DT_N_S_soc_S_serial_40007800_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_serial_40007800_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800, resets, 0)
#define DT_N_S_soc_S_serial_40007800_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800, resets, 0)
#define DT_N_S_soc_S_serial_40007800_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007800_P_resets_LEN 1
#define DT_N_S_soc_S_serial_40007800_P_resets_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_interrupts {82 /* 0x52 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_serial_40007800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_interrupts_IDX_0 82
#define DT_N_S_soc_S_serial_40007800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_serial_40007800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_current_speed 115200
#define DT_N_S_soc_S_serial_40007800_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_stop_bits "1"
#define DT_N_S_soc_S_serial_40007800_P_stop_bits_STRING_UNQUOTED 1
#define DT_N_S_soc_S_serial_40007800_P_stop_bits_STRING_TOKEN 1
#define DT_N_S_soc_S_serial_40007800_P_stop_bits_STRING_UPPER_TOKEN 1
#define DT_N_S_soc_S_serial_40007800_P_stop_bits_IDX_0 "1"
#define DT_N_S_soc_S_serial_40007800_P_stop_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_stop_bits_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40007800_P_stop_bits_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_stop_bits_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_stop_bits_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800, stop_bits, 0)
#define DT_N_S_soc_S_serial_40007800_P_stop_bits_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800, stop_bits, 0)
#define DT_N_S_soc_S_serial_40007800_P_stop_bits_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007800_P_stop_bits_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007800_P_stop_bits_LEN 1
#define DT_N_S_soc_S_serial_40007800_P_stop_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_data_bits 8
#define DT_N_S_soc_S_serial_40007800_P_data_bits_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_serial_40007800_P_data_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_data_bits_IDX_0_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_data_bits_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_data_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_single_wire 0
#define DT_N_S_soc_S_serial_40007800_P_single_wire_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_tx_rx_swap 0
#define DT_N_S_soc_S_serial_40007800_P_tx_rx_swap_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_de_enable 0
#define DT_N_S_soc_S_serial_40007800_P_de_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_de_assert_time 0
#define DT_N_S_soc_S_serial_40007800_P_de_assert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_de_deassert_time 0
#define DT_N_S_soc_S_serial_40007800_P_de_deassert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_de_invert 0
#define DT_N_S_soc_S_serial_40007800_P_de_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_fifo_enable 0
#define DT_N_S_soc_S_serial_40007800_P_fifo_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_hw_flow_control 0
#define DT_N_S_soc_S_serial_40007800_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_parity "none"
#define DT_N_S_soc_S_serial_40007800_P_parity_STRING_UNQUOTED none
#define DT_N_S_soc_S_serial_40007800_P_parity_STRING_TOKEN none
#define DT_N_S_soc_S_serial_40007800_P_parity_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_serial_40007800_P_parity_IDX_0 "none"
#define DT_N_S_soc_S_serial_40007800_P_parity_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_parity_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_serial_40007800_P_parity_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_parity_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_parity_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800, parity, 0)
#define DT_N_S_soc_S_serial_40007800_P_parity_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800, parity, 0)
#define DT_N_S_soc_S_serial_40007800_P_parity_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007800_P_parity_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007800_P_parity_LEN 1
#define DT_N_S_soc_S_serial_40007800_P_parity_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_status "disabled"
#define DT_N_S_soc_S_serial_40007800_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_serial_40007800_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_serial_40007800_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_serial_40007800_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_serial_40007800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40007800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800, status, 0)
#define DT_N_S_soc_S_serial_40007800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800, status, 0)
#define DT_N_S_soc_S_serial_40007800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007800_P_status_LEN 1
#define DT_N_S_soc_S_serial_40007800_P_status_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_compatible {"st,stm32-uart"}
#define DT_N_S_soc_S_serial_40007800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_compatible_IDX_0 "st,stm32-uart"
#define DT_N_S_soc_S_serial_40007800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-uart
#define DT_N_S_soc_S_serial_40007800_P_compatible_IDX_0_STRING_TOKEN st_stm32_uart
#define DT_N_S_soc_S_serial_40007800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_UART
#define DT_N_S_soc_S_serial_40007800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800, compatible, 0)
#define DT_N_S_soc_S_serial_40007800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800, compatible, 0)
#define DT_N_S_soc_S_serial_40007800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007800_P_compatible_LEN 1
#define DT_N_S_soc_S_serial_40007800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_dma_coherent 0
#define DT_N_S_soc_S_serial_40007800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_serial_40007800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_wakeup_source 0
#define DT_N_S_soc_S_serial_40007800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_serial_40007800_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_tx_invert 0
#define DT_N_S_soc_S_serial_40007800_P_tx_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40007800_P_rx_invert 0
#define DT_N_S_soc_S_serial_40007800_P_rx_invert_EXISTS 1

/*
 * Devicetree node: /soc/serial@40007c00
 *
 * Node identifier: DT_N_S_soc_S_serial_40007c00
 *
 * Binding (compatible = st,stm32-uart):
 *   $ZEPHYR_BASE\dts\bindings\serial\st,stm32-uart.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_serial_40007c00_PATH "/soc/serial@40007c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_serial_40007c00_FULL_NAME "serial@40007c00"
#define DT_N_S_soc_S_serial_40007c00_FULL_NAME_UNQUOTED serial@40007c00
#define DT_N_S_soc_S_serial_40007c00_FULL_NAME_TOKEN serial_40007c00
#define DT_N_S_soc_S_serial_40007c00_FULL_NAME_UPPER_TOKEN SERIAL_40007C00

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_serial_40007c00_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_serial_40007c00_CHILD_IDX 53

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_serial_40007c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_serial_40007c00_FOREACH_NODELABEL(fn) fn(uart8)
#define DT_N_S_soc_S_serial_40007c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart8, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_serial_40007c00_CHILD_NUM 0
#define DT_N_S_soc_S_serial_40007c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_serial_40007c00_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_serial_40007c00_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40007c00_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40007c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_serial_40007c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_serial_40007c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40007c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40007c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_serial_40007c00_HASH X_JkTKIJdI0eAWONgmNDDiIT_A1U0dqJMPoCmX7VfRo

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_serial_40007c00_ORD 79
#define DT_N_S_soc_S_serial_40007c00_ORD_STR_SORTABLE 00079

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_serial_40007c00_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_serial_40007c00_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_serial_40007c00_IDX_0_C_TOKEN uart8

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_serial_40007c00_EXISTS 1
#define DT_N_INST_7_st_stm32_uart DT_N_S_soc_S_serial_40007c00
#define DT_N_NODELABEL_uart8      DT_N_S_soc_S_serial_40007c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_serial_40007c00_REG_NUM 1
#define DT_N_S_soc_S_serial_40007c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_REG_IDX_0_VAL_ADDRESS 1073773568 /* 0x40007c00 */
#define DT_N_S_soc_S_serial_40007c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_serial_40007c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_serial_40007c00, 0)
#define DT_N_S_soc_S_serial_40007c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007c00, 0)
#define DT_N_S_soc_S_serial_40007c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007c00_RANGES_NUM 0
#define DT_N_S_soc_S_serial_40007c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_serial_40007c00_IRQ_NUM 1
#define DT_N_S_soc_S_serial_40007c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_IRQ_IDX_0_VAL_irq 83
#define DT_N_S_soc_S_serial_40007c00_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_serial_40007c00_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_serial_40007c00_IRQ_LEVEL 1
#define DT_N_S_soc_S_serial_40007c00_COMPAT_MATCHES_st_stm32_uart 1
#define DT_N_S_soc_S_serial_40007c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40007c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_COMPAT_MODEL_IDX_0 "stm32-uart"
#define DT_N_S_soc_S_serial_40007c00_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_serial_40007c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_serial_40007c00_P_reg {1073773568 /* 0x40007c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_serial_40007c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_reg_IDX_0 1073773568
#define DT_N_S_soc_S_serial_40007c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_serial_40007c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_serial_40007c00_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_serial_40007c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_clocks_IDX_0_VAL_bits 2147483648
#define DT_N_S_soc_S_serial_40007c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40007c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_serial_40007c00, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40007c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40007c00, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40007c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_serial_40007c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007c00, clocks, 0)
#define DT_N_S_soc_S_serial_40007c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007c00, clocks, 0)
#define DT_N_S_soc_S_serial_40007c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007c00_P_clocks_LEN 1
#define DT_N_S_soc_S_serial_40007c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_serial_40007c00_P_resets_IDX_0_VAL_id 1055
#define DT_N_S_soc_S_serial_40007c00_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40007c00, resets, 0, id)
#define DT_N_S_soc_S_serial_40007c00_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007c00, resets, 0, id)
#define DT_N_S_soc_S_serial_40007c00_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_serial_40007c00_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007c00, resets, 0)
#define DT_N_S_soc_S_serial_40007c00_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007c00, resets, 0)
#define DT_N_S_soc_S_serial_40007c00_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007c00, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007c00_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007c00, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007c00_P_resets_LEN 1
#define DT_N_S_soc_S_serial_40007c00_P_resets_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_interrupts {83 /* 0x53 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_serial_40007c00_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_interrupts_IDX_0 83
#define DT_N_S_soc_S_serial_40007c00_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_serial_40007c00_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_current_speed 115200
#define DT_N_S_soc_S_serial_40007c00_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_stop_bits "1"
#define DT_N_S_soc_S_serial_40007c00_P_stop_bits_STRING_UNQUOTED 1
#define DT_N_S_soc_S_serial_40007c00_P_stop_bits_STRING_TOKEN 1
#define DT_N_S_soc_S_serial_40007c00_P_stop_bits_STRING_UPPER_TOKEN 1
#define DT_N_S_soc_S_serial_40007c00_P_stop_bits_IDX_0 "1"
#define DT_N_S_soc_S_serial_40007c00_P_stop_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_stop_bits_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40007c00_P_stop_bits_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_stop_bits_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_stop_bits_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007c00, stop_bits, 0)
#define DT_N_S_soc_S_serial_40007c00_P_stop_bits_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007c00, stop_bits, 0)
#define DT_N_S_soc_S_serial_40007c00_P_stop_bits_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007c00, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007c00_P_stop_bits_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007c00, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007c00_P_stop_bits_LEN 1
#define DT_N_S_soc_S_serial_40007c00_P_stop_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_data_bits 8
#define DT_N_S_soc_S_serial_40007c00_P_data_bits_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_serial_40007c00_P_data_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_data_bits_IDX_0_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_data_bits_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_data_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_single_wire 0
#define DT_N_S_soc_S_serial_40007c00_P_single_wire_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_tx_rx_swap 0
#define DT_N_S_soc_S_serial_40007c00_P_tx_rx_swap_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_de_enable 0
#define DT_N_S_soc_S_serial_40007c00_P_de_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_de_assert_time 0
#define DT_N_S_soc_S_serial_40007c00_P_de_assert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_de_deassert_time 0
#define DT_N_S_soc_S_serial_40007c00_P_de_deassert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_de_invert 0
#define DT_N_S_soc_S_serial_40007c00_P_de_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_fifo_enable 0
#define DT_N_S_soc_S_serial_40007c00_P_fifo_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_hw_flow_control 0
#define DT_N_S_soc_S_serial_40007c00_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_parity "none"
#define DT_N_S_soc_S_serial_40007c00_P_parity_STRING_UNQUOTED none
#define DT_N_S_soc_S_serial_40007c00_P_parity_STRING_TOKEN none
#define DT_N_S_soc_S_serial_40007c00_P_parity_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_serial_40007c00_P_parity_IDX_0 "none"
#define DT_N_S_soc_S_serial_40007c00_P_parity_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_parity_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_serial_40007c00_P_parity_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_parity_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_parity_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007c00, parity, 0)
#define DT_N_S_soc_S_serial_40007c00_P_parity_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007c00, parity, 0)
#define DT_N_S_soc_S_serial_40007c00_P_parity_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007c00, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007c00_P_parity_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007c00, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007c00_P_parity_LEN 1
#define DT_N_S_soc_S_serial_40007c00_P_parity_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_status "disabled"
#define DT_N_S_soc_S_serial_40007c00_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_serial_40007c00_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_serial_40007c00_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_serial_40007c00_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_serial_40007c00_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40007c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007c00, status, 0)
#define DT_N_S_soc_S_serial_40007c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007c00, status, 0)
#define DT_N_S_soc_S_serial_40007c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007c00_P_status_LEN 1
#define DT_N_S_soc_S_serial_40007c00_P_status_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_compatible {"st,stm32-uart"}
#define DT_N_S_soc_S_serial_40007c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_compatible_IDX_0 "st,stm32-uart"
#define DT_N_S_soc_S_serial_40007c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-uart
#define DT_N_S_soc_S_serial_40007c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_uart
#define DT_N_S_soc_S_serial_40007c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_UART
#define DT_N_S_soc_S_serial_40007c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007c00, compatible, 0)
#define DT_N_S_soc_S_serial_40007c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007c00, compatible, 0)
#define DT_N_S_soc_S_serial_40007c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40007c00_P_compatible_LEN 1
#define DT_N_S_soc_S_serial_40007c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_dma_coherent 0
#define DT_N_S_soc_S_serial_40007c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_serial_40007c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_wakeup_source 0
#define DT_N_S_soc_S_serial_40007c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_serial_40007c00_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_tx_invert 0
#define DT_N_S_soc_S_serial_40007c00_P_tx_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40007c00_P_rx_invert 0
#define DT_N_S_soc_S_serial_40007c00_P_rx_invert_EXISTS 1

/*
 * Devicetree node: /soc/serial@40011000
 *
 * Node identifier: DT_N_S_soc_S_serial_40011000
 *
 * Binding (compatible = st,stm32-usart):
 *   $ZEPHYR_BASE\dts\bindings\serial\st,stm32-usart.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_serial_40011000_PATH "/soc/serial@40011000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_serial_40011000_FULL_NAME "serial@40011000"
#define DT_N_S_soc_S_serial_40011000_FULL_NAME_UNQUOTED serial@40011000
#define DT_N_S_soc_S_serial_40011000_FULL_NAME_TOKEN serial_40011000
#define DT_N_S_soc_S_serial_40011000_FULL_NAME_UPPER_TOKEN SERIAL_40011000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_serial_40011000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_serial_40011000_CHILD_IDX 8

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_serial_40011000_NODELABEL_NUM 1
#define DT_N_S_soc_S_serial_40011000_FOREACH_NODELABEL(fn) fn(usart1)
#define DT_N_S_soc_S_serial_40011000_FOREACH_NODELABEL_VARGS(fn, ...) fn(usart1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_serial_40011000_CHILD_NUM 0
#define DT_N_S_soc_S_serial_40011000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_serial_40011000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_serial_40011000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40011000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40011000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_serial_40011000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_serial_40011000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40011000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40011000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_serial_40011000_HASH zC6jA0Z9upGUbivXx_7kb5XvPKXVEdHortQpRPhSzt8

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_serial_40011000_ORD 80
#define DT_N_S_soc_S_serial_40011000_ORD_STR_SORTABLE 00080

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_serial_40011000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_serial_40011000_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_serial_40011000_IDX_0_C_TOKEN usart1

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_serial_40011000_EXISTS 1
#define DT_N_INST_2_st_stm32_usart DT_N_S_soc_S_serial_40011000
#define DT_N_INST_2_st_stm32_uart  DT_N_S_soc_S_serial_40011000
#define DT_N_NODELABEL_usart1      DT_N_S_soc_S_serial_40011000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_serial_40011000_REG_NUM 1
#define DT_N_S_soc_S_serial_40011000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_REG_IDX_0_VAL_ADDRESS 1073811456 /* 0x40011000 */
#define DT_N_S_soc_S_serial_40011000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_serial_40011000_FOREACH_REG(fn) fn(DT_N_S_soc_S_serial_40011000, 0)
#define DT_N_S_soc_S_serial_40011000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011000, 0)
#define DT_N_S_soc_S_serial_40011000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011000_RANGES_NUM 0
#define DT_N_S_soc_S_serial_40011000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_serial_40011000_IRQ_NUM 1
#define DT_N_S_soc_S_serial_40011000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_IRQ_IDX_0_VAL_irq 37
#define DT_N_S_soc_S_serial_40011000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_serial_40011000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_serial_40011000_IRQ_LEVEL 1
#define DT_N_S_soc_S_serial_40011000_COMPAT_MATCHES_st_stm32_usart 1
#define DT_N_S_soc_S_serial_40011000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40011000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_COMPAT_MODEL_IDX_0 "stm32-usart"
#define DT_N_S_soc_S_serial_40011000_COMPAT_MATCHES_st_stm32_uart 1
#define DT_N_S_soc_S_serial_40011000_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40011000_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_COMPAT_MODEL_IDX_1 "stm32-uart"
#define DT_N_S_soc_S_serial_40011000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_serial_40011000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_serial_40011000_P_reg {1073811456 /* 0x40011000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_serial_40011000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_reg_IDX_0 1073811456
#define DT_N_S_soc_S_serial_40011000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_serial_40011000_P_reg_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_serial_40011000_P_clocks_IDX_0_VAL_bus 68
#define DT_N_S_soc_S_serial_40011000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_clocks_IDX_0_VAL_bits 16
#define DT_N_S_soc_S_serial_40011000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40011000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_serial_40011000, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40011000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40011000, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40011000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_serial_40011000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011000, clocks, 0)
#define DT_N_S_soc_S_serial_40011000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011000, clocks, 0)
#define DT_N_S_soc_S_serial_40011000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011000_P_clocks_LEN 1
#define DT_N_S_soc_S_serial_40011000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_serial_40011000_P_resets_IDX_0_VAL_id 1156
#define DT_N_S_soc_S_serial_40011000_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40011000, resets, 0, id)
#define DT_N_S_soc_S_serial_40011000_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011000, resets, 0, id)
#define DT_N_S_soc_S_serial_40011000_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_serial_40011000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011000, resets, 0)
#define DT_N_S_soc_S_serial_40011000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011000, resets, 0)
#define DT_N_S_soc_S_serial_40011000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011000_P_resets_LEN 1
#define DT_N_S_soc_S_serial_40011000_P_resets_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_interrupts {37 /* 0x25 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_serial_40011000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_interrupts_IDX_0 37
#define DT_N_S_soc_S_serial_40011000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_serial_40011000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_current_speed 115200
#define DT_N_S_soc_S_serial_40011000_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_stop_bits "1"
#define DT_N_S_soc_S_serial_40011000_P_stop_bits_STRING_UNQUOTED 1
#define DT_N_S_soc_S_serial_40011000_P_stop_bits_STRING_TOKEN 1
#define DT_N_S_soc_S_serial_40011000_P_stop_bits_STRING_UPPER_TOKEN 1
#define DT_N_S_soc_S_serial_40011000_P_stop_bits_IDX_0 "1"
#define DT_N_S_soc_S_serial_40011000_P_stop_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_stop_bits_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40011000_P_stop_bits_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_stop_bits_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_stop_bits_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011000, stop_bits, 0)
#define DT_N_S_soc_S_serial_40011000_P_stop_bits_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011000, stop_bits, 0)
#define DT_N_S_soc_S_serial_40011000_P_stop_bits_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011000, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011000_P_stop_bits_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011000, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011000_P_stop_bits_LEN 1
#define DT_N_S_soc_S_serial_40011000_P_stop_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_data_bits 8
#define DT_N_S_soc_S_serial_40011000_P_data_bits_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_serial_40011000_P_data_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_data_bits_IDX_0_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_data_bits_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_data_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_single_wire 0
#define DT_N_S_soc_S_serial_40011000_P_single_wire_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_tx_rx_swap 0
#define DT_N_S_soc_S_serial_40011000_P_tx_rx_swap_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_de_enable 0
#define DT_N_S_soc_S_serial_40011000_P_de_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_de_assert_time 0
#define DT_N_S_soc_S_serial_40011000_P_de_assert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_de_deassert_time 0
#define DT_N_S_soc_S_serial_40011000_P_de_deassert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_de_invert 0
#define DT_N_S_soc_S_serial_40011000_P_de_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_fifo_enable 0
#define DT_N_S_soc_S_serial_40011000_P_fifo_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_hw_flow_control 0
#define DT_N_S_soc_S_serial_40011000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_parity "none"
#define DT_N_S_soc_S_serial_40011000_P_parity_STRING_UNQUOTED none
#define DT_N_S_soc_S_serial_40011000_P_parity_STRING_TOKEN none
#define DT_N_S_soc_S_serial_40011000_P_parity_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_serial_40011000_P_parity_IDX_0 "none"
#define DT_N_S_soc_S_serial_40011000_P_parity_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_parity_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_serial_40011000_P_parity_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_parity_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_parity_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011000, parity, 0)
#define DT_N_S_soc_S_serial_40011000_P_parity_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011000, parity, 0)
#define DT_N_S_soc_S_serial_40011000_P_parity_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011000, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011000_P_parity_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011000, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011000_P_parity_LEN 1
#define DT_N_S_soc_S_serial_40011000_P_parity_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_status "disabled"
#define DT_N_S_soc_S_serial_40011000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_serial_40011000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_serial_40011000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_serial_40011000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_serial_40011000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40011000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011000, status, 0)
#define DT_N_S_soc_S_serial_40011000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011000, status, 0)
#define DT_N_S_soc_S_serial_40011000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011000_P_status_LEN 1
#define DT_N_S_soc_S_serial_40011000_P_status_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_compatible {"st,stm32-usart", "st,stm32-uart"}
#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_0 "st,stm32-usart"
#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-usart
#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_0_STRING_TOKEN st_stm32_usart
#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_USART
#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_1 "st,stm32-uart"
#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-uart
#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_1_STRING_TOKEN st_stm32_uart
#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_UART
#define DT_N_S_soc_S_serial_40011000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011000, compatible, 0) \
	fn(DT_N_S_soc_S_serial_40011000, compatible, 1)
#define DT_N_S_soc_S_serial_40011000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40011000, compatible, 1)
#define DT_N_S_soc_S_serial_40011000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_serial_40011000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40011000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011000_P_compatible_LEN 2
#define DT_N_S_soc_S_serial_40011000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_dma_coherent 0
#define DT_N_S_soc_S_serial_40011000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_serial_40011000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_wakeup_source 0
#define DT_N_S_soc_S_serial_40011000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_serial_40011000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_tx_invert 0
#define DT_N_S_soc_S_serial_40011000_P_tx_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40011000_P_rx_invert 0
#define DT_N_S_soc_S_serial_40011000_P_rx_invert_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/usart6_rx_pg9
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_PATH "/soc/pin-controller@40020000/usart6_rx_pg9"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FULL_NAME "usart6_rx_pg9"
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FULL_NAME_UNQUOTED usart6_rx_pg9
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FULL_NAME_TOKEN usart6_rx_pg9
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FULL_NAME_UPPER_TOKEN USART6_RX_PG9

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_CHILD_IDX 31

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FOREACH_NODELABEL(fn) fn(usart6_rx_pg9)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FOREACH_NODELABEL_VARGS(fn, ...) fn(usart6_rx_pg9, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_HASH Zhjac_WNVYD_aVnR12OiIJt_PzKHdVlI1P2sGxn5cp8

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_ORD 81
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_ORD_STR_SORTABLE 00081

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_SUPPORTS_ORDS \
	83, /* /soc/serial@40011400 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_IDX_0_C_TOKEN usart6_rx_pg9

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_EXISTS 1
#define DT_N_NODELABEL_usart6_rx_pg9 DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_pinmux 3368
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/usart6_tx_pg14
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_PATH "/soc/pin-controller@40020000/usart6_tx_pg14"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FULL_NAME "usart6_tx_pg14"
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FULL_NAME_UNQUOTED usart6_tx_pg14
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FULL_NAME_TOKEN usart6_tx_pg14
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FULL_NAME_UPPER_TOKEN USART6_TX_PG14

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_CHILD_IDX 33

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FOREACH_NODELABEL(fn) fn(usart6_tx_pg14)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FOREACH_NODELABEL_VARGS(fn, ...) fn(usart6_tx_pg14, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_HASH ViPPLStTlMUQ_C94JVpZjJORf42lSTxNsSbMMVpf_J4

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_ORD 82
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_ORD_STR_SORTABLE 00082

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_SUPPORTS_ORDS \
	83, /* /soc/serial@40011400 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_IDX_0_C_TOKEN usart6_tx_pg14

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_EXISTS 1
#define DT_N_NODELABEL_usart6_tx_pg14 DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_pinmux 3528
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_bias_pull_up 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/serial@40011400
 *
 * Node identifier: DT_N_S_soc_S_serial_40011400
 *
 * Binding (compatible = st,stm32-usart):
 *   $ZEPHYR_BASE\dts\bindings\serial\st,stm32-usart.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_serial_40011400_PATH "/soc/serial@40011400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_serial_40011400_FULL_NAME "serial@40011400"
#define DT_N_S_soc_S_serial_40011400_FULL_NAME_UNQUOTED serial@40011400
#define DT_N_S_soc_S_serial_40011400_FULL_NAME_TOKEN serial_40011400
#define DT_N_S_soc_S_serial_40011400_FULL_NAME_UPPER_TOKEN SERIAL_40011400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_serial_40011400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_serial_40011400_CHILD_IDX 10

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_serial_40011400_NODELABEL_NUM 2
#define DT_N_S_soc_S_serial_40011400_FOREACH_NODELABEL(fn) fn(usart6) fn(arduino_serial)
#define DT_N_S_soc_S_serial_40011400_FOREACH_NODELABEL_VARGS(fn, ...) fn(usart6, __VA_ARGS__) fn(arduino_serial, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_serial_40011400_CHILD_NUM 0
#define DT_N_S_soc_S_serial_40011400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_serial_40011400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_serial_40011400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40011400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40011400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_serial_40011400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_serial_40011400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40011400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40011400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_serial_40011400_HASH EbGeH803dfT68JE63jG_Jb4zq9uTggwiK7WnQWx1toQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_serial_40011400_ORD 83
#define DT_N_S_soc_S_serial_40011400_ORD_STR_SORTABLE 00083

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_serial_40011400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */ \
	81, /* /soc/pin-controller@40020000/usart6_rx_pg9 */ \
	82, /* /soc/pin-controller@40020000/usart6_tx_pg14 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_serial_40011400_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_serial_40011400_IDX_0_C_TOKEN usart6
#define DT_N_NODELABEL_DT_N_S_soc_S_serial_40011400_IDX_1_C_TOKEN arduino_serial

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_serial_40011400_EXISTS 1
#define DT_N_INST_0_st_stm32_usart    DT_N_S_soc_S_serial_40011400
#define DT_N_INST_0_st_stm32_uart     DT_N_S_soc_S_serial_40011400
#define DT_N_NODELABEL_usart6         DT_N_S_soc_S_serial_40011400
#define DT_N_NODELABEL_arduino_serial DT_N_S_soc_S_serial_40011400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_serial_40011400_REG_NUM 1
#define DT_N_S_soc_S_serial_40011400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_REG_IDX_0_VAL_ADDRESS 1073812480 /* 0x40011400 */
#define DT_N_S_soc_S_serial_40011400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_serial_40011400_FOREACH_REG(fn) fn(DT_N_S_soc_S_serial_40011400, 0)
#define DT_N_S_soc_S_serial_40011400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011400, 0)
#define DT_N_S_soc_S_serial_40011400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_RANGES_NUM 0
#define DT_N_S_soc_S_serial_40011400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_serial_40011400_IRQ_NUM 1
#define DT_N_S_soc_S_serial_40011400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_IRQ_IDX_0_VAL_irq 71
#define DT_N_S_soc_S_serial_40011400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_serial_40011400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_serial_40011400_IRQ_LEVEL 1
#define DT_N_S_soc_S_serial_40011400_COMPAT_MATCHES_st_stm32_usart 1
#define DT_N_S_soc_S_serial_40011400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40011400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_COMPAT_MODEL_IDX_0 "stm32-usart"
#define DT_N_S_soc_S_serial_40011400_COMPAT_MATCHES_st_stm32_uart 1
#define DT_N_S_soc_S_serial_40011400_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40011400_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_COMPAT_MODEL_IDX_1 "stm32-uart"
#define DT_N_S_soc_S_serial_40011400_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_serial_40011400_PINCTRL_NUM 1
#define DT_N_S_soc_S_serial_40011400_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_serial_40011400_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_serial_40011400_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_serial_40011400_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14
#define DT_N_S_soc_S_serial_40011400_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9

/* Generic property macros: */
#define DT_N_S_soc_S_serial_40011400_P_reg {1073812480 /* 0x40011400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_serial_40011400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_reg_IDX_0 1073812480
#define DT_N_S_soc_S_serial_40011400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_serial_40011400_P_reg_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_serial_40011400_P_clocks_IDX_0_VAL_bus 68
#define DT_N_S_soc_S_serial_40011400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_clocks_IDX_0_VAL_bits 32
#define DT_N_S_soc_S_serial_40011400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40011400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_serial_40011400, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40011400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40011400, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40011400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_serial_40011400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011400, clocks, 0)
#define DT_N_S_soc_S_serial_40011400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011400, clocks, 0)
#define DT_N_S_soc_S_serial_40011400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_P_clocks_LEN 1
#define DT_N_S_soc_S_serial_40011400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_serial_40011400_P_resets_IDX_0_VAL_id 1157
#define DT_N_S_soc_S_serial_40011400_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40011400, resets, 0, id)
#define DT_N_S_soc_S_serial_40011400_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011400, resets, 0, id)
#define DT_N_S_soc_S_serial_40011400_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_serial_40011400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011400, resets, 0)
#define DT_N_S_soc_S_serial_40011400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011400, resets, 0)
#define DT_N_S_soc_S_serial_40011400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_P_resets_LEN 1
#define DT_N_S_soc_S_serial_40011400_P_resets_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_interrupts {71 /* 0x47 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_serial_40011400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_interrupts_IDX_0 71
#define DT_N_S_soc_S_serial_40011400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_serial_40011400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_current_speed 115200
#define DT_N_S_soc_S_serial_40011400_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_stop_bits "1"
#define DT_N_S_soc_S_serial_40011400_P_stop_bits_STRING_UNQUOTED 1
#define DT_N_S_soc_S_serial_40011400_P_stop_bits_STRING_TOKEN 1
#define DT_N_S_soc_S_serial_40011400_P_stop_bits_STRING_UPPER_TOKEN 1
#define DT_N_S_soc_S_serial_40011400_P_stop_bits_IDX_0 "1"
#define DT_N_S_soc_S_serial_40011400_P_stop_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_stop_bits_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40011400_P_stop_bits_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_stop_bits_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_stop_bits_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011400, stop_bits, 0)
#define DT_N_S_soc_S_serial_40011400_P_stop_bits_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011400, stop_bits, 0)
#define DT_N_S_soc_S_serial_40011400_P_stop_bits_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011400, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_P_stop_bits_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011400, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_P_stop_bits_LEN 1
#define DT_N_S_soc_S_serial_40011400_P_stop_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_data_bits 8
#define DT_N_S_soc_S_serial_40011400_P_data_bits_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_serial_40011400_P_data_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_data_bits_IDX_0_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_data_bits_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_data_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_single_wire 0
#define DT_N_S_soc_S_serial_40011400_P_single_wire_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_tx_rx_swap 0
#define DT_N_S_soc_S_serial_40011400_P_tx_rx_swap_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_0_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011400, pinctrl_0, 0) \
	fn(DT_N_S_soc_S_serial_40011400, pinctrl_0, 1)
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011400, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40011400, pinctrl_0, 1)
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011400, pinctrl_0, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_serial_40011400, pinctrl_0, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011400, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40011400, pinctrl_0, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_0_LEN 2
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011400, pinctrl_names, 0)
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011400, pinctrl_names, 0)
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011400, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011400, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_de_enable 0
#define DT_N_S_soc_S_serial_40011400_P_de_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_de_assert_time 0
#define DT_N_S_soc_S_serial_40011400_P_de_assert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_de_deassert_time 0
#define DT_N_S_soc_S_serial_40011400_P_de_deassert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_de_invert 0
#define DT_N_S_soc_S_serial_40011400_P_de_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_fifo_enable 0
#define DT_N_S_soc_S_serial_40011400_P_fifo_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_hw_flow_control 0
#define DT_N_S_soc_S_serial_40011400_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_parity "none"
#define DT_N_S_soc_S_serial_40011400_P_parity_STRING_UNQUOTED none
#define DT_N_S_soc_S_serial_40011400_P_parity_STRING_TOKEN none
#define DT_N_S_soc_S_serial_40011400_P_parity_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_serial_40011400_P_parity_IDX_0 "none"
#define DT_N_S_soc_S_serial_40011400_P_parity_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_parity_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_serial_40011400_P_parity_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_parity_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_parity_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011400, parity, 0)
#define DT_N_S_soc_S_serial_40011400_P_parity_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011400, parity, 0)
#define DT_N_S_soc_S_serial_40011400_P_parity_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011400, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_P_parity_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011400, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_P_parity_LEN 1
#define DT_N_S_soc_S_serial_40011400_P_parity_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_status "okay"
#define DT_N_S_soc_S_serial_40011400_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_serial_40011400_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_serial_40011400_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_serial_40011400_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_serial_40011400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_serial_40011400_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011400, status, 0)
#define DT_N_S_soc_S_serial_40011400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011400, status, 0)
#define DT_N_S_soc_S_serial_40011400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_P_status_LEN 1
#define DT_N_S_soc_S_serial_40011400_P_status_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_compatible {"st,stm32-usart", "st,stm32-uart"}
#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_0 "st,stm32-usart"
#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-usart
#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_0_STRING_TOKEN st_stm32_usart
#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_USART
#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_1 "st,stm32-uart"
#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-uart
#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_1_STRING_TOKEN st_stm32_uart
#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_UART
#define DT_N_S_soc_S_serial_40011400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011400, compatible, 0) \
	fn(DT_N_S_soc_S_serial_40011400, compatible, 1)
#define DT_N_S_soc_S_serial_40011400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011400, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40011400, compatible, 1)
#define DT_N_S_soc_S_serial_40011400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011400, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_serial_40011400, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011400, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40011400, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40011400_P_compatible_LEN 2
#define DT_N_S_soc_S_serial_40011400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_dma_coherent 0
#define DT_N_S_soc_S_serial_40011400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_serial_40011400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_wakeup_source 0
#define DT_N_S_soc_S_serial_40011400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_serial_40011400_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_tx_invert 0
#define DT_N_S_soc_S_serial_40011400_P_tx_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40011400_P_rx_invert 0
#define DT_N_S_soc_S_serial_40011400_P_rx_invert_EXISTS 1

/*
 * Devicetree node: /soc/spi@40003800
 *
 * Node identifier: DT_N_S_soc_S_spi_40003800
 *
 * Binding (compatible = st,stm32-spi):
 *   $ZEPHYR_BASE\dts\bindings\spi\st,stm32-spi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_spi_40003800_PATH "/soc/spi@40003800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_spi_40003800_FULL_NAME "spi@40003800"
#define DT_N_S_soc_S_spi_40003800_FULL_NAME_UNQUOTED spi@40003800
#define DT_N_S_soc_S_spi_40003800_FULL_NAME_TOKEN spi_40003800
#define DT_N_S_soc_S_spi_40003800_FULL_NAME_UPPER_TOKEN SPI_40003800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spi_40003800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_spi_40003800_CHILD_IDX 29

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_spi_40003800_NODELABEL_NUM 1
#define DT_N_S_soc_S_spi_40003800_FOREACH_NODELABEL(fn) fn(spi2)
#define DT_N_S_soc_S_spi_40003800_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi2, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_spi_40003800_CHILD_NUM 0
#define DT_N_S_soc_S_spi_40003800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_spi_40003800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_spi_40003800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40003800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40003800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_spi_40003800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_spi_40003800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40003800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40003800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_spi_40003800_HASH XKwnj_54XNd9o8CRTIG33G9j_T58zD9aWx_JOqtlec4

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spi_40003800_ORD 84
#define DT_N_S_soc_S_spi_40003800_ORD_STR_SORTABLE 00084

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spi_40003800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spi_40003800_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_spi_40003800_IDX_0_C_TOKEN spi2

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spi_40003800_EXISTS 1
#define DT_N_INST_1_st_stm32_spi DT_N_S_soc_S_spi_40003800
#define DT_N_NODELABEL_spi2      DT_N_S_soc_S_spi_40003800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_spi_40003800_REG_NUM 1
#define DT_N_S_soc_S_spi_40003800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_REG_IDX_0_VAL_ADDRESS 1073756160 /* 0x40003800 */
#define DT_N_S_soc_S_spi_40003800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_spi_40003800_FOREACH_REG(fn) fn(DT_N_S_soc_S_spi_40003800, 0)
#define DT_N_S_soc_S_spi_40003800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003800, 0)
#define DT_N_S_soc_S_spi_40003800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_RANGES_NUM 0
#define DT_N_S_soc_S_spi_40003800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_spi_40003800_IRQ_NUM 1
#define DT_N_S_soc_S_spi_40003800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_IRQ_IDX_0_VAL_irq 36
#define DT_N_S_soc_S_spi_40003800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_spi_40003800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_spi_40003800_IRQ_LEVEL 1
#define DT_N_S_soc_S_spi_40003800_COMPAT_MATCHES_st_stm32_spi 1
#define DT_N_S_soc_S_spi_40003800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_spi_40003800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_COMPAT_MODEL_IDX_0 "stm32-spi"
#define DT_N_S_soc_S_spi_40003800_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_spi_40003800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_spi_40003800_P_reg {1073756160 /* 0x40003800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_spi_40003800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_reg_IDX_0 1073756160
#define DT_N_S_soc_S_spi_40003800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_spi_40003800_P_reg_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_interrupts {36 /* 0x24 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_spi_40003800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_interrupts_IDX_0 36
#define DT_N_S_soc_S_spi_40003800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_spi_40003800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_ioswp 0
#define DT_N_S_soc_S_spi_40003800_P_ioswp_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width "limited-8-16-bit"
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_STRING_UNQUOTED limited-8-16-bit
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_STRING_TOKEN limited_8_16_bit
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_STRING_UPPER_TOKEN LIMITED_8_16_BIT
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_IDX_0 "limited-8-16-bit"
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_IDX_0_ENUM_IDX 2
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_IDX_0_ENUM_VAL_limited_8_16_bit_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_ENUM_VAL_limited_8_16_bit_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003800, st_spi_data_width, 0)
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003800, st_spi_data_width, 0)
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003800, st_spi_data_width, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003800, st_spi_data_width, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_LEN 1
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_st_soft_nss 0
#define DT_N_S_soc_S_spi_40003800_P_st_soft_nss_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_status "disabled"
#define DT_N_S_soc_S_spi_40003800_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_spi_40003800_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_spi_40003800_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_spi_40003800_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_spi_40003800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_spi_40003800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003800, status, 0)
#define DT_N_S_soc_S_spi_40003800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003800, status, 0)
#define DT_N_S_soc_S_spi_40003800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_status_LEN 1
#define DT_N_S_soc_S_spi_40003800_P_status_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_compatible {"st,stm32-spi"}
#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_0 "st,stm32-spi"
#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-spi
#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_0_STRING_TOKEN st_stm32_spi
#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SPI
#define DT_N_S_soc_S_spi_40003800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003800, compatible, 0)
#define DT_N_S_soc_S_spi_40003800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003800, compatible, 0)
#define DT_N_S_soc_S_spi_40003800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_compatible_LEN 1
#define DT_N_S_soc_S_spi_40003800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_VAL_bits 16384
#define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_spi_40003800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_spi_40003800, clocks, 0, bits)
#define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003800, clocks, 0, bits)
#define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_spi_40003800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003800, clocks, 0)
#define DT_N_S_soc_S_spi_40003800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003800, clocks, 0)
#define DT_N_S_soc_S_spi_40003800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_clocks_LEN 1
#define DT_N_S_soc_S_spi_40003800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_dma_coherent 0
#define DT_N_S_soc_S_spi_40003800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_spi_40003800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_wakeup_source 0
#define DT_N_S_soc_S_spi_40003800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_spi_40003800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/spi@40003c00
 *
 * Node identifier: DT_N_S_soc_S_spi_40003c00
 *
 * Binding (compatible = st,stm32-spi):
 *   $ZEPHYR_BASE\dts\bindings\spi\st,stm32-spi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_spi_40003c00_PATH "/soc/spi@40003c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_spi_40003c00_FULL_NAME "spi@40003c00"
#define DT_N_S_soc_S_spi_40003c00_FULL_NAME_UNQUOTED spi@40003c00
#define DT_N_S_soc_S_spi_40003c00_FULL_NAME_TOKEN spi_40003c00
#define DT_N_S_soc_S_spi_40003c00_FULL_NAME_UPPER_TOKEN SPI_40003C00

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spi_40003c00_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_spi_40003c00_CHILD_IDX 30

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_spi_40003c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_spi_40003c00_FOREACH_NODELABEL(fn) fn(spi3)
#define DT_N_S_soc_S_spi_40003c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi3, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_spi_40003c00_CHILD_NUM 0
#define DT_N_S_soc_S_spi_40003c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_spi_40003c00_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_spi_40003c00_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40003c00_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40003c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_spi_40003c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_spi_40003c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40003c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40003c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_spi_40003c00_HASH 2ZRlHGHWIr4tSgRVkDzDHSiC22m9C4PVNAuFo8LU_0A

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spi_40003c00_ORD 85
#define DT_N_S_soc_S_spi_40003c00_ORD_STR_SORTABLE 00085

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spi_40003c00_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spi_40003c00_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_spi_40003c00_IDX_0_C_TOKEN spi3

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spi_40003c00_EXISTS 1
#define DT_N_INST_2_st_stm32_spi DT_N_S_soc_S_spi_40003c00
#define DT_N_NODELABEL_spi3      DT_N_S_soc_S_spi_40003c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_spi_40003c00_REG_NUM 1
#define DT_N_S_soc_S_spi_40003c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_REG_IDX_0_VAL_ADDRESS 1073757184 /* 0x40003c00 */
#define DT_N_S_soc_S_spi_40003c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_spi_40003c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_spi_40003c00, 0)
#define DT_N_S_soc_S_spi_40003c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003c00, 0)
#define DT_N_S_soc_S_spi_40003c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_RANGES_NUM 0
#define DT_N_S_soc_S_spi_40003c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_spi_40003c00_IRQ_NUM 1
#define DT_N_S_soc_S_spi_40003c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_IRQ_IDX_0_VAL_irq 51
#define DT_N_S_soc_S_spi_40003c00_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_spi_40003c00_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_spi_40003c00_IRQ_LEVEL 1
#define DT_N_S_soc_S_spi_40003c00_COMPAT_MATCHES_st_stm32_spi 1
#define DT_N_S_soc_S_spi_40003c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_spi_40003c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_COMPAT_MODEL_IDX_0 "stm32-spi"
#define DT_N_S_soc_S_spi_40003c00_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_spi_40003c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_spi_40003c00_P_reg {1073757184 /* 0x40003c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_spi_40003c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_reg_IDX_0 1073757184
#define DT_N_S_soc_S_spi_40003c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_spi_40003c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_interrupts {51 /* 0x33 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_spi_40003c00_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_interrupts_IDX_0 51
#define DT_N_S_soc_S_spi_40003c00_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_spi_40003c00_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_ioswp 0
#define DT_N_S_soc_S_spi_40003c00_P_ioswp_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width "limited-8-16-bit"
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_STRING_UNQUOTED limited-8-16-bit
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_STRING_TOKEN limited_8_16_bit
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_STRING_UPPER_TOKEN LIMITED_8_16_BIT
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_IDX_0 "limited-8-16-bit"
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_IDX_0_ENUM_IDX 2
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_IDX_0_ENUM_VAL_limited_8_16_bit_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_ENUM_VAL_limited_8_16_bit_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003c00, st_spi_data_width, 0)
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003c00, st_spi_data_width, 0)
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003c00, st_spi_data_width, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003c00, st_spi_data_width, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_LEN 1
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_st_soft_nss 0
#define DT_N_S_soc_S_spi_40003c00_P_st_soft_nss_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_status "disabled"
#define DT_N_S_soc_S_spi_40003c00_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_spi_40003c00_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_spi_40003c00_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_spi_40003c00_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_spi_40003c00_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_spi_40003c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003c00, status, 0)
#define DT_N_S_soc_S_spi_40003c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003c00, status, 0)
#define DT_N_S_soc_S_spi_40003c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_status_LEN 1
#define DT_N_S_soc_S_spi_40003c00_P_status_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_compatible {"st,stm32-spi"}
#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_0 "st,stm32-spi"
#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-spi
#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_spi
#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SPI
#define DT_N_S_soc_S_spi_40003c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003c00, compatible, 0)
#define DT_N_S_soc_S_spi_40003c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003c00, compatible, 0)
#define DT_N_S_soc_S_spi_40003c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_compatible_LEN 1
#define DT_N_S_soc_S_spi_40003c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_VAL_bits 32768
#define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_spi_40003c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_spi_40003c00, clocks, 0, bits)
#define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003c00, clocks, 0, bits)
#define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_spi_40003c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003c00, clocks, 0)
#define DT_N_S_soc_S_spi_40003c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003c00, clocks, 0)
#define DT_N_S_soc_S_spi_40003c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_clocks_LEN 1
#define DT_N_S_soc_S_spi_40003c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_dma_coherent 0
#define DT_N_S_soc_S_spi_40003c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_spi_40003c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_wakeup_source 0
#define DT_N_S_soc_S_spi_40003c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_spi_40003c00_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/gpio@40020c00
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00
 *
 * Binding (compatible = st,stm32-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\st,stm32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_PATH "/soc/pin-controller@40020000/gpio@40020c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FULL_NAME "gpio@40020c00"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FULL_NAME_UNQUOTED gpio@40020c00
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FULL_NAME_TOKEN gpio_40020c00
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FULL_NAME_UPPER_TOKEN GPIO_40020C00

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FOREACH_NODELABEL(fn) fn(gpiod)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpiod, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_HASH urI3sHVSvnrVLWAQ786vvDI0ksvmq5lFBck_I7VFAZs

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_ORD 86
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_ORD_STR_SORTABLE 00086

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_REQUIRES_ORDS \
	9, /* /soc/rcc@40023800 */ \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_SUPPORTS_ORDS \
	90, /* /soc/spi@40013000 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_IDX_0_C_TOKEN gpiod

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_EXISTS 1
#define DT_N_INST_3_st_stm32_gpio DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00
#define DT_N_NODELABEL_gpiod      DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_REG_IDX_0_VAL_ADDRESS 1073875968 /* 0x40020c00 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_COMPAT_MATCHES_st_stm32_gpio 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_COMPAT_MODEL_IDX_0 "stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_reg {1073875968 /* 0x40020c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_reg_IDX_0 1073875968
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_clocks_IDX_0_VAL_bus 48
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_clocks_IDX_0_VAL_bits 8
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_clocks_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_ngpios 16
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_gpio_controller 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_compatible {"st,stm32-gpio"}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_compatible_IDX_0 "st,stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/spi1_miso_pa6
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_PATH "/soc/pin-controller@40020000/spi1_miso_pa6"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FULL_NAME "spi1_miso_pa6"
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FULL_NAME_UNQUOTED spi1_miso_pa6
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FULL_NAME_TOKEN spi1_miso_pa6
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FULL_NAME_UPPER_TOKEN SPI1_MISO_PA6

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_CHILD_IDX 26

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FOREACH_NODELABEL(fn) fn(spi1_miso_pa6)
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi1_miso_pa6, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_HASH NeaQEWLkV_bwIO15oTrkPiUb8dd7BSvDbzexST8pN_U

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_ORD 87
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_ORD_STR_SORTABLE 00087

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_SUPPORTS_ORDS \
	90, /* /soc/spi@40013000 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_IDX_0_C_TOKEN spi1_miso_pa6

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_EXISTS 1
#define DT_N_NODELABEL_spi1_miso_pa6 DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_pinmux 197
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_bias_pull_down 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/spi1_mosi_pa7
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_PATH "/soc/pin-controller@40020000/spi1_mosi_pa7"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FULL_NAME "spi1_mosi_pa7"
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FULL_NAME_UNQUOTED spi1_mosi_pa7
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FULL_NAME_TOKEN spi1_mosi_pa7
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FULL_NAME_UPPER_TOKEN SPI1_MOSI_PA7

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_CHILD_IDX 27

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FOREACH_NODELABEL(fn) fn(spi1_mosi_pa7)
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi1_mosi_pa7, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_HASH R6CBsusBpaW6dLQcd5LfWhbrwkvSo5DIsMX8ENgGoZ4

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_ORD 88
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_ORD_STR_SORTABLE 00088

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_SUPPORTS_ORDS \
	90, /* /soc/spi@40013000 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_IDX_0_C_TOKEN spi1_mosi_pa7

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_EXISTS 1
#define DT_N_NODELABEL_spi1_mosi_pa7 DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_pinmux 229
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_bias_pull_down 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/spi1_sck_pa5
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_PATH "/soc/pin-controller@40020000/spi1_sck_pa5"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FULL_NAME "spi1_sck_pa5"
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FULL_NAME_UNQUOTED spi1_sck_pa5
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FULL_NAME_TOKEN spi1_sck_pa5
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FULL_NAME_UPPER_TOKEN SPI1_SCK_PA5

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_CHILD_IDX 28

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FOREACH_NODELABEL(fn) fn(spi1_sck_pa5)
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi1_sck_pa5, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_HASH sl289rrRXiwrgQdQsYWfVMlgIy3DiBOTvVjmJ4_3IVE

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_ORD 89
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_ORD_STR_SORTABLE 00089

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_SUPPORTS_ORDS \
	90, /* /soc/spi@40013000 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_IDX_0_C_TOKEN spi1_sck_pa5

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_EXISTS 1
#define DT_N_NODELABEL_spi1_sck_pa5 DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_pinmux 165
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_bias_pull_down 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/spi@40013000
 *
 * Node identifier: DT_N_S_soc_S_spi_40013000
 *
 * Binding (compatible = st,stm32-spi):
 *   $ZEPHYR_BASE\dts\bindings\spi\st,stm32-spi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_spi_40013000_PATH "/soc/spi@40013000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_spi_40013000_FULL_NAME "spi@40013000"
#define DT_N_S_soc_S_spi_40013000_FULL_NAME_UNQUOTED spi@40013000
#define DT_N_S_soc_S_spi_40013000_FULL_NAME_TOKEN spi_40013000
#define DT_N_S_soc_S_spi_40013000_FULL_NAME_UPPER_TOKEN SPI_40013000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spi_40013000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_spi_40013000_CHILD_IDX 14

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_spi_40013000_NODELABEL_NUM 2
#define DT_N_S_soc_S_spi_40013000_FOREACH_NODELABEL(fn) fn(spi1) fn(arduino_spi)
#define DT_N_S_soc_S_spi_40013000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi1, __VA_ARGS__) fn(arduino_spi, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_spi_40013000_CHILD_NUM 0
#define DT_N_S_soc_S_spi_40013000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_spi_40013000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_spi_40013000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40013000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40013000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_spi_40013000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_spi_40013000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40013000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40013000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_spi_40013000_HASH q04f3jPcynKDa_9eKR_V34RQn5SAL2iX4yHIC7XGkLs

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spi_40013000_ORD 90
#define DT_N_S_soc_S_spi_40013000_ORD_STR_SORTABLE 00090

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spi_40013000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	86, /* /soc/pin-controller@40020000/gpio@40020c00 */ \
	87, /* /soc/pin-controller@40020000/spi1_miso_pa6 */ \
	88, /* /soc/pin-controller@40020000/spi1_mosi_pa7 */ \
	89, /* /soc/pin-controller@40020000/spi1_sck_pa5 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spi_40013000_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_spi_40013000_IDX_0_C_TOKEN spi1
#define DT_N_NODELABEL_DT_N_S_soc_S_spi_40013000_IDX_1_C_TOKEN arduino_spi

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spi_40013000_EXISTS 1
#define DT_N_INST_0_st_stm32_spi   DT_N_S_soc_S_spi_40013000
#define DT_N_NODELABEL_spi1        DT_N_S_soc_S_spi_40013000
#define DT_N_NODELABEL_arduino_spi DT_N_S_soc_S_spi_40013000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_spi_40013000_REG_NUM 1
#define DT_N_S_soc_S_spi_40013000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_REG_IDX_0_VAL_ADDRESS 1073819648 /* 0x40013000 */
#define DT_N_S_soc_S_spi_40013000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_spi_40013000_FOREACH_REG(fn) fn(DT_N_S_soc_S_spi_40013000, 0)
#define DT_N_S_soc_S_spi_40013000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, 0)
#define DT_N_S_soc_S_spi_40013000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_RANGES_NUM 0
#define DT_N_S_soc_S_spi_40013000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_spi_40013000_IRQ_NUM 1
#define DT_N_S_soc_S_spi_40013000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_IRQ_IDX_0_VAL_irq 35
#define DT_N_S_soc_S_spi_40013000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_spi_40013000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_spi_40013000_IRQ_LEVEL 1
#define DT_N_S_soc_S_spi_40013000_COMPAT_MATCHES_st_stm32_spi 1
#define DT_N_S_soc_S_spi_40013000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_spi_40013000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_COMPAT_MODEL_IDX_0 "stm32-spi"
#define DT_N_S_soc_S_spi_40013000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_spi_40013000_PINCTRL_NUM 1
#define DT_N_S_soc_S_spi_40013000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_spi_40013000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_spi_40013000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_spi_40013000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5
#define DT_N_S_soc_S_spi_40013000_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6
#define DT_N_S_soc_S_spi_40013000_PINCTRL_NAME_default_IDX_2_PH DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7

/* Generic property macros: */
#define DT_N_S_soc_S_spi_40013000_P_reg {1073819648 /* 0x40013000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_spi_40013000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_reg_IDX_0 1073819648
#define DT_N_S_soc_S_spi_40013000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_spi_40013000_P_reg_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_interrupts {35 /* 0x23 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_spi_40013000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_interrupts_IDX_0 35
#define DT_N_S_soc_S_spi_40013000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_spi_40013000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_2 DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_2_PH DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_2_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 0) \
	fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 1) \
	fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 2)
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 2)
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 2, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 2, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_LEN 3
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, pinctrl_names, 0)
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, pinctrl_names, 0)
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_ioswp 0
#define DT_N_S_soc_S_spi_40013000_P_ioswp_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width "limited-8-16-bit"
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_STRING_UNQUOTED limited-8-16-bit
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_STRING_TOKEN limited_8_16_bit
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_STRING_UPPER_TOKEN LIMITED_8_16_BIT
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_IDX_0 "limited-8-16-bit"
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_IDX_0_ENUM_IDX 2
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_IDX_0_ENUM_VAL_limited_8_16_bit_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_ENUM_VAL_limited_8_16_bit_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, st_spi_data_width, 0)
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, st_spi_data_width, 0)
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, st_spi_data_width, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, st_spi_data_width, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_LEN 1
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_st_soft_nss 0
#define DT_N_S_soc_S_spi_40013000_P_st_soft_nss_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_IDX_0_VAL_pin 14
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_IDX_0_VAL_flags 17
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_spi_40013000, cs_gpios, 0, pin) \
	fn(DT_N_S_soc_S_spi_40013000, cs_gpios, 0, flags)
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, cs_gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40013000, cs_gpios, 0, flags)
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, cs_gpios, 0)
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, cs_gpios, 0)
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, cs_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, cs_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_LEN 1
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_status "okay"
#define DT_N_S_soc_S_spi_40013000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_spi_40013000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_spi_40013000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_spi_40013000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_spi_40013000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_spi_40013000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, status, 0)
#define DT_N_S_soc_S_spi_40013000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, status, 0)
#define DT_N_S_soc_S_spi_40013000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_status_LEN 1
#define DT_N_S_soc_S_spi_40013000_P_status_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_compatible {"st,stm32-spi"}
#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_0 "st,stm32-spi"
#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-spi
#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_0_STRING_TOKEN st_stm32_spi
#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SPI
#define DT_N_S_soc_S_spi_40013000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, compatible, 0)
#define DT_N_S_soc_S_spi_40013000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, compatible, 0)
#define DT_N_S_soc_S_spi_40013000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_compatible_LEN 1
#define DT_N_S_soc_S_spi_40013000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_VAL_bus 68
#define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_VAL_bits 4096
#define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_spi_40013000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_spi_40013000, clocks, 0, bits)
#define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40013000, clocks, 0, bits)
#define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_spi_40013000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, clocks, 0)
#define DT_N_S_soc_S_spi_40013000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, clocks, 0)
#define DT_N_S_soc_S_spi_40013000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_clocks_LEN 1
#define DT_N_S_soc_S_spi_40013000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_dma_coherent 0
#define DT_N_S_soc_S_spi_40013000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_spi_40013000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_wakeup_source 0
#define DT_N_S_soc_S_spi_40013000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_spi_40013000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/spi@40013400
 *
 * Node identifier: DT_N_S_soc_S_spi_40013400
 *
 * Binding (compatible = st,stm32-spi):
 *   $ZEPHYR_BASE\dts\bindings\spi\st,stm32-spi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_spi_40013400_PATH "/soc/spi@40013400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_spi_40013400_FULL_NAME "spi@40013400"
#define DT_N_S_soc_S_spi_40013400_FULL_NAME_UNQUOTED spi@40013400
#define DT_N_S_soc_S_spi_40013400_FULL_NAME_TOKEN spi_40013400
#define DT_N_S_soc_S_spi_40013400_FULL_NAME_UPPER_TOKEN SPI_40013400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spi_40013400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_spi_40013400_CHILD_IDX 31

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_spi_40013400_NODELABEL_NUM 1
#define DT_N_S_soc_S_spi_40013400_FOREACH_NODELABEL(fn) fn(spi4)
#define DT_N_S_soc_S_spi_40013400_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi4, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_spi_40013400_CHILD_NUM 0
#define DT_N_S_soc_S_spi_40013400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_spi_40013400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_spi_40013400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40013400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40013400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_spi_40013400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_spi_40013400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40013400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40013400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_spi_40013400_HASH _gq_GFzBL2BriiF_xUBpw3VzRXUfex3S_XMm3qRcPgU

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spi_40013400_ORD 91
#define DT_N_S_soc_S_spi_40013400_ORD_STR_SORTABLE 00091

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spi_40013400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spi_40013400_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_spi_40013400_IDX_0_C_TOKEN spi4

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spi_40013400_EXISTS 1
#define DT_N_INST_3_st_stm32_spi DT_N_S_soc_S_spi_40013400
#define DT_N_NODELABEL_spi4      DT_N_S_soc_S_spi_40013400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_spi_40013400_REG_NUM 1
#define DT_N_S_soc_S_spi_40013400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_REG_IDX_0_VAL_ADDRESS 1073820672 /* 0x40013400 */
#define DT_N_S_soc_S_spi_40013400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_spi_40013400_FOREACH_REG(fn) fn(DT_N_S_soc_S_spi_40013400, 0)
#define DT_N_S_soc_S_spi_40013400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013400, 0)
#define DT_N_S_soc_S_spi_40013400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013400_RANGES_NUM 0
#define DT_N_S_soc_S_spi_40013400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_spi_40013400_IRQ_NUM 1
#define DT_N_S_soc_S_spi_40013400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_IRQ_IDX_0_VAL_irq 84
#define DT_N_S_soc_S_spi_40013400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_spi_40013400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_spi_40013400_IRQ_LEVEL 1
#define DT_N_S_soc_S_spi_40013400_COMPAT_MATCHES_st_stm32_spi 1
#define DT_N_S_soc_S_spi_40013400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_spi_40013400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_COMPAT_MODEL_IDX_0 "stm32-spi"
#define DT_N_S_soc_S_spi_40013400_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_spi_40013400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_spi_40013400_P_reg {1073820672 /* 0x40013400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_spi_40013400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_reg_IDX_0 1073820672
#define DT_N_S_soc_S_spi_40013400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_spi_40013400_P_reg_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_interrupts {84 /* 0x54 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_spi_40013400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_interrupts_IDX_0 84
#define DT_N_S_soc_S_spi_40013400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_spi_40013400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_ioswp 0
#define DT_N_S_soc_S_spi_40013400_P_ioswp_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_st_spi_data_width "limited-8-16-bit"
#define DT_N_S_soc_S_spi_40013400_P_st_spi_data_width_STRING_UNQUOTED limited-8-16-bit
#define DT_N_S_soc_S_spi_40013400_P_st_spi_data_width_STRING_TOKEN limited_8_16_bit
#define DT_N_S_soc_S_spi_40013400_P_st_spi_data_width_STRING_UPPER_TOKEN LIMITED_8_16_BIT
#define DT_N_S_soc_S_spi_40013400_P_st_spi_data_width_IDX_0 "limited-8-16-bit"
#define DT_N_S_soc_S_spi_40013400_P_st_spi_data_width_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_st_spi_data_width_IDX_0_ENUM_IDX 2
#define DT_N_S_soc_S_spi_40013400_P_st_spi_data_width_IDX_0_ENUM_VAL_limited_8_16_bit_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_st_spi_data_width_ENUM_VAL_limited_8_16_bit_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_st_spi_data_width_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013400, st_spi_data_width, 0)
#define DT_N_S_soc_S_spi_40013400_P_st_spi_data_width_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013400, st_spi_data_width, 0)
#define DT_N_S_soc_S_spi_40013400_P_st_spi_data_width_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013400, st_spi_data_width, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013400_P_st_spi_data_width_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013400, st_spi_data_width, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013400_P_st_spi_data_width_LEN 1
#define DT_N_S_soc_S_spi_40013400_P_st_spi_data_width_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_st_soft_nss 0
#define DT_N_S_soc_S_spi_40013400_P_st_soft_nss_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_status "disabled"
#define DT_N_S_soc_S_spi_40013400_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_spi_40013400_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_spi_40013400_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_spi_40013400_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_spi_40013400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_spi_40013400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013400, status, 0)
#define DT_N_S_soc_S_spi_40013400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013400, status, 0)
#define DT_N_S_soc_S_spi_40013400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013400_P_status_LEN 1
#define DT_N_S_soc_S_spi_40013400_P_status_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_compatible {"st,stm32-spi"}
#define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_0 "st,stm32-spi"
#define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-spi
#define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_0_STRING_TOKEN st_stm32_spi
#define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SPI
#define DT_N_S_soc_S_spi_40013400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013400, compatible, 0)
#define DT_N_S_soc_S_spi_40013400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013400, compatible, 0)
#define DT_N_S_soc_S_spi_40013400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013400_P_compatible_LEN 1
#define DT_N_S_soc_S_spi_40013400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_spi_40013400_P_clocks_IDX_0_VAL_bus 68
#define DT_N_S_soc_S_spi_40013400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_clocks_IDX_0_VAL_bits 8192
#define DT_N_S_soc_S_spi_40013400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_spi_40013400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_spi_40013400, clocks, 0, bits)
#define DT_N_S_soc_S_spi_40013400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40013400, clocks, 0, bits)
#define DT_N_S_soc_S_spi_40013400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_spi_40013400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013400, clocks, 0)
#define DT_N_S_soc_S_spi_40013400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013400, clocks, 0)
#define DT_N_S_soc_S_spi_40013400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013400_P_clocks_LEN 1
#define DT_N_S_soc_S_spi_40013400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_dma_coherent 0
#define DT_N_S_soc_S_spi_40013400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_spi_40013400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_wakeup_source 0
#define DT_N_S_soc_S_spi_40013400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_spi_40013400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_spi_40013400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/spi@40015000
 *
 * Node identifier: DT_N_S_soc_S_spi_40015000
 *
 * Binding (compatible = st,stm32-spi):
 *   $ZEPHYR_BASE\dts\bindings\spi\st,stm32-spi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_spi_40015000_PATH "/soc/spi@40015000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_spi_40015000_FULL_NAME "spi@40015000"
#define DT_N_S_soc_S_spi_40015000_FULL_NAME_UNQUOTED spi@40015000
#define DT_N_S_soc_S_spi_40015000_FULL_NAME_TOKEN spi_40015000
#define DT_N_S_soc_S_spi_40015000_FULL_NAME_UPPER_TOKEN SPI_40015000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spi_40015000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_spi_40015000_CHILD_IDX 54

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_spi_40015000_NODELABEL_NUM 1
#define DT_N_S_soc_S_spi_40015000_FOREACH_NODELABEL(fn) fn(spi5)
#define DT_N_S_soc_S_spi_40015000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi5, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_spi_40015000_CHILD_NUM 0
#define DT_N_S_soc_S_spi_40015000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_spi_40015000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_spi_40015000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40015000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40015000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_spi_40015000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_spi_40015000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40015000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40015000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_spi_40015000_HASH _7uoLr5262nubu_Aw_eizLfScuJO0NCTRjc4zDKDojg

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spi_40015000_ORD 92
#define DT_N_S_soc_S_spi_40015000_ORD_STR_SORTABLE 00092

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spi_40015000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spi_40015000_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_spi_40015000_IDX_0_C_TOKEN spi5

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spi_40015000_EXISTS 1
#define DT_N_INST_4_st_stm32_spi DT_N_S_soc_S_spi_40015000
#define DT_N_NODELABEL_spi5      DT_N_S_soc_S_spi_40015000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_spi_40015000_REG_NUM 1
#define DT_N_S_soc_S_spi_40015000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_REG_IDX_0_VAL_ADDRESS 1073827840 /* 0x40015000 */
#define DT_N_S_soc_S_spi_40015000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_spi_40015000_FOREACH_REG(fn) fn(DT_N_S_soc_S_spi_40015000, 0)
#define DT_N_S_soc_S_spi_40015000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40015000, 0)
#define DT_N_S_soc_S_spi_40015000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40015000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40015000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015000_RANGES_NUM 0
#define DT_N_S_soc_S_spi_40015000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_spi_40015000_IRQ_NUM 1
#define DT_N_S_soc_S_spi_40015000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_IRQ_IDX_0_VAL_irq 85
#define DT_N_S_soc_S_spi_40015000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_spi_40015000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_spi_40015000_IRQ_LEVEL 1
#define DT_N_S_soc_S_spi_40015000_COMPAT_MATCHES_st_stm32_spi 1
#define DT_N_S_soc_S_spi_40015000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_spi_40015000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_COMPAT_MODEL_IDX_0 "stm32-spi"
#define DT_N_S_soc_S_spi_40015000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_spi_40015000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_spi_40015000_P_reg {1073827840 /* 0x40015000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_spi_40015000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_reg_IDX_0 1073827840
#define DT_N_S_soc_S_spi_40015000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_spi_40015000_P_reg_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_interrupts {85 /* 0x55 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_spi_40015000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_interrupts_IDX_0 85
#define DT_N_S_soc_S_spi_40015000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_spi_40015000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_ioswp 0
#define DT_N_S_soc_S_spi_40015000_P_ioswp_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_st_spi_data_width "limited-8-16-bit"
#define DT_N_S_soc_S_spi_40015000_P_st_spi_data_width_STRING_UNQUOTED limited-8-16-bit
#define DT_N_S_soc_S_spi_40015000_P_st_spi_data_width_STRING_TOKEN limited_8_16_bit
#define DT_N_S_soc_S_spi_40015000_P_st_spi_data_width_STRING_UPPER_TOKEN LIMITED_8_16_BIT
#define DT_N_S_soc_S_spi_40015000_P_st_spi_data_width_IDX_0 "limited-8-16-bit"
#define DT_N_S_soc_S_spi_40015000_P_st_spi_data_width_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_st_spi_data_width_IDX_0_ENUM_IDX 2
#define DT_N_S_soc_S_spi_40015000_P_st_spi_data_width_IDX_0_ENUM_VAL_limited_8_16_bit_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_st_spi_data_width_ENUM_VAL_limited_8_16_bit_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_st_spi_data_width_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40015000, st_spi_data_width, 0)
#define DT_N_S_soc_S_spi_40015000_P_st_spi_data_width_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40015000, st_spi_data_width, 0)
#define DT_N_S_soc_S_spi_40015000_P_st_spi_data_width_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40015000, st_spi_data_width, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015000_P_st_spi_data_width_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40015000, st_spi_data_width, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015000_P_st_spi_data_width_LEN 1
#define DT_N_S_soc_S_spi_40015000_P_st_spi_data_width_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_st_soft_nss 0
#define DT_N_S_soc_S_spi_40015000_P_st_soft_nss_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_status "disabled"
#define DT_N_S_soc_S_spi_40015000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_spi_40015000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_spi_40015000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_spi_40015000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_spi_40015000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_spi_40015000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40015000, status, 0)
#define DT_N_S_soc_S_spi_40015000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40015000, status, 0)
#define DT_N_S_soc_S_spi_40015000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40015000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40015000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015000_P_status_LEN 1
#define DT_N_S_soc_S_spi_40015000_P_status_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_compatible {"st,stm32-spi"}
#define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_0 "st,stm32-spi"
#define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-spi
#define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_0_STRING_TOKEN st_stm32_spi
#define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SPI
#define DT_N_S_soc_S_spi_40015000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40015000, compatible, 0)
#define DT_N_S_soc_S_spi_40015000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40015000, compatible, 0)
#define DT_N_S_soc_S_spi_40015000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40015000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40015000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015000_P_compatible_LEN 1
#define DT_N_S_soc_S_spi_40015000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_spi_40015000_P_clocks_IDX_0_VAL_bus 68
#define DT_N_S_soc_S_spi_40015000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_clocks_IDX_0_VAL_bits 1048576
#define DT_N_S_soc_S_spi_40015000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_spi_40015000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_spi_40015000, clocks, 0, bits)
#define DT_N_S_soc_S_spi_40015000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40015000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40015000, clocks, 0, bits)
#define DT_N_S_soc_S_spi_40015000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_spi_40015000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40015000, clocks, 0)
#define DT_N_S_soc_S_spi_40015000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40015000, clocks, 0)
#define DT_N_S_soc_S_spi_40015000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40015000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40015000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015000_P_clocks_LEN 1
#define DT_N_S_soc_S_spi_40015000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_dma_coherent 0
#define DT_N_S_soc_S_spi_40015000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_spi_40015000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_wakeup_source 0
#define DT_N_S_soc_S_spi_40015000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_spi_40015000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_spi_40015000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/spi@40015400
 *
 * Node identifier: DT_N_S_soc_S_spi_40015400
 *
 * Binding (compatible = st,stm32-spi):
 *   $ZEPHYR_BASE\dts\bindings\spi\st,stm32-spi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_spi_40015400_PATH "/soc/spi@40015400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_spi_40015400_FULL_NAME "spi@40015400"
#define DT_N_S_soc_S_spi_40015400_FULL_NAME_UNQUOTED spi@40015400
#define DT_N_S_soc_S_spi_40015400_FULL_NAME_TOKEN spi_40015400
#define DT_N_S_soc_S_spi_40015400_FULL_NAME_UPPER_TOKEN SPI_40015400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spi_40015400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_spi_40015400_CHILD_IDX 55

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_spi_40015400_NODELABEL_NUM 1
#define DT_N_S_soc_S_spi_40015400_FOREACH_NODELABEL(fn) fn(spi6)
#define DT_N_S_soc_S_spi_40015400_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi6, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_spi_40015400_CHILD_NUM 0
#define DT_N_S_soc_S_spi_40015400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_spi_40015400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_spi_40015400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40015400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40015400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_spi_40015400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_spi_40015400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40015400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40015400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_spi_40015400_HASH cVI5s6vMSeiCQtOXk7_V2Bvna_PAv3b5vNtt21_UsRU

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spi_40015400_ORD 93
#define DT_N_S_soc_S_spi_40015400_ORD_STR_SORTABLE 00093

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spi_40015400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spi_40015400_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_spi_40015400_IDX_0_C_TOKEN spi6

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spi_40015400_EXISTS 1
#define DT_N_INST_5_st_stm32_spi DT_N_S_soc_S_spi_40015400
#define DT_N_NODELABEL_spi6      DT_N_S_soc_S_spi_40015400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_spi_40015400_REG_NUM 1
#define DT_N_S_soc_S_spi_40015400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_REG_IDX_0_VAL_ADDRESS 1073828864 /* 0x40015400 */
#define DT_N_S_soc_S_spi_40015400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_spi_40015400_FOREACH_REG(fn) fn(DT_N_S_soc_S_spi_40015400, 0)
#define DT_N_S_soc_S_spi_40015400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40015400, 0)
#define DT_N_S_soc_S_spi_40015400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40015400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40015400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015400_RANGES_NUM 0
#define DT_N_S_soc_S_spi_40015400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_spi_40015400_IRQ_NUM 1
#define DT_N_S_soc_S_spi_40015400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_IRQ_IDX_0_VAL_irq 86
#define DT_N_S_soc_S_spi_40015400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_spi_40015400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_spi_40015400_IRQ_LEVEL 1
#define DT_N_S_soc_S_spi_40015400_COMPAT_MATCHES_st_stm32_spi 1
#define DT_N_S_soc_S_spi_40015400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_spi_40015400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_COMPAT_MODEL_IDX_0 "stm32-spi"
#define DT_N_S_soc_S_spi_40015400_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_spi_40015400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_spi_40015400_P_reg {1073828864 /* 0x40015400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_spi_40015400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_reg_IDX_0 1073828864
#define DT_N_S_soc_S_spi_40015400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_spi_40015400_P_reg_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_interrupts {86 /* 0x56 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_spi_40015400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_interrupts_IDX_0 86
#define DT_N_S_soc_S_spi_40015400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_spi_40015400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_ioswp 0
#define DT_N_S_soc_S_spi_40015400_P_ioswp_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_st_spi_data_width "limited-8-16-bit"
#define DT_N_S_soc_S_spi_40015400_P_st_spi_data_width_STRING_UNQUOTED limited-8-16-bit
#define DT_N_S_soc_S_spi_40015400_P_st_spi_data_width_STRING_TOKEN limited_8_16_bit
#define DT_N_S_soc_S_spi_40015400_P_st_spi_data_width_STRING_UPPER_TOKEN LIMITED_8_16_BIT
#define DT_N_S_soc_S_spi_40015400_P_st_spi_data_width_IDX_0 "limited-8-16-bit"
#define DT_N_S_soc_S_spi_40015400_P_st_spi_data_width_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_st_spi_data_width_IDX_0_ENUM_IDX 2
#define DT_N_S_soc_S_spi_40015400_P_st_spi_data_width_IDX_0_ENUM_VAL_limited_8_16_bit_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_st_spi_data_width_ENUM_VAL_limited_8_16_bit_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_st_spi_data_width_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40015400, st_spi_data_width, 0)
#define DT_N_S_soc_S_spi_40015400_P_st_spi_data_width_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40015400, st_spi_data_width, 0)
#define DT_N_S_soc_S_spi_40015400_P_st_spi_data_width_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40015400, st_spi_data_width, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015400_P_st_spi_data_width_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40015400, st_spi_data_width, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015400_P_st_spi_data_width_LEN 1
#define DT_N_S_soc_S_spi_40015400_P_st_spi_data_width_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_st_soft_nss 0
#define DT_N_S_soc_S_spi_40015400_P_st_soft_nss_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_status "disabled"
#define DT_N_S_soc_S_spi_40015400_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_spi_40015400_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_spi_40015400_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_spi_40015400_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_spi_40015400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_spi_40015400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40015400, status, 0)
#define DT_N_S_soc_S_spi_40015400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40015400, status, 0)
#define DT_N_S_soc_S_spi_40015400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40015400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40015400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015400_P_status_LEN 1
#define DT_N_S_soc_S_spi_40015400_P_status_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_compatible {"st,stm32-spi"}
#define DT_N_S_soc_S_spi_40015400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_compatible_IDX_0 "st,stm32-spi"
#define DT_N_S_soc_S_spi_40015400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-spi
#define DT_N_S_soc_S_spi_40015400_P_compatible_IDX_0_STRING_TOKEN st_stm32_spi
#define DT_N_S_soc_S_spi_40015400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SPI
#define DT_N_S_soc_S_spi_40015400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40015400, compatible, 0)
#define DT_N_S_soc_S_spi_40015400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40015400, compatible, 0)
#define DT_N_S_soc_S_spi_40015400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40015400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40015400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015400_P_compatible_LEN 1
#define DT_N_S_soc_S_spi_40015400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_spi_40015400_P_clocks_IDX_0_VAL_bus 68
#define DT_N_S_soc_S_spi_40015400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_clocks_IDX_0_VAL_bits 2097152
#define DT_N_S_soc_S_spi_40015400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_spi_40015400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_spi_40015400, clocks, 0, bits)
#define DT_N_S_soc_S_spi_40015400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40015400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40015400, clocks, 0, bits)
#define DT_N_S_soc_S_spi_40015400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_spi_40015400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40015400, clocks, 0)
#define DT_N_S_soc_S_spi_40015400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40015400, clocks, 0)
#define DT_N_S_soc_S_spi_40015400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40015400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40015400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40015400_P_clocks_LEN 1
#define DT_N_S_soc_S_spi_40015400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_dma_coherent 0
#define DT_N_S_soc_S_spi_40015400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_spi_40015400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_wakeup_source 0
#define DT_N_S_soc_S_spi_40015400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_spi_40015400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_spi_40015400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timer@e000e010
 *
 * Node identifier: DT_N_S_soc_S_timer_e000e010
 *
 * Binding (compatible = arm,armv7m-systick):
 *   $ZEPHYR_BASE\dts\bindings\timer\arm,armv7m-systick.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timer_e000e010_PATH "/soc/timer@e000e010"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timer_e000e010_FULL_NAME "timer@e000e010"
#define DT_N_S_soc_S_timer_e000e010_FULL_NAME_UNQUOTED timer@e000e010
#define DT_N_S_soc_S_timer_e000e010_FULL_NAME_TOKEN timer_e000e010
#define DT_N_S_soc_S_timer_e000e010_FULL_NAME_UPPER_TOKEN TIMER_E000E010

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timer_e000e010_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timer_e000e010_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timer_e000e010_NODELABEL_NUM 1
#define DT_N_S_soc_S_timer_e000e010_FOREACH_NODELABEL(fn) fn(systick)
#define DT_N_S_soc_S_timer_e000e010_FOREACH_NODELABEL_VARGS(fn, ...) fn(systick, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timer_e000e010_CHILD_NUM 0
#define DT_N_S_soc_S_timer_e000e010_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timer_e000e010_HASH aZrzPLAIRgEwRZJIvTCzJONA6gPgc4QlhkiU5oWGArA

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timer_e000e010_ORD 94
#define DT_N_S_soc_S_timer_e000e010_ORD_STR_SORTABLE 00094

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timer_e000e010_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timer_e000e010_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_timer_e000e010_IDX_0_C_TOKEN systick

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timer_e000e010_EXISTS 1
#define DT_N_INST_0_arm_armv7m_systick DT_N_S_soc_S_timer_e000e010
#define DT_N_NODELABEL_systick         DT_N_S_soc_S_timer_e000e010

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timer_e000e010_REG_NUM 1
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_ADDRESS 3758153744 /* 0xe000e010 */
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_SIZE 16 /* 0x10 */
#define DT_N_S_soc_S_timer_e000e010_FOREACH_REG(fn) fn(DT_N_S_soc_S_timer_e000e010, 0)
#define DT_N_S_soc_S_timer_e000e010_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, 0)
#define DT_N_S_soc_S_timer_e000e010_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_RANGES_NUM 0
#define DT_N_S_soc_S_timer_e000e010_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timer_e000e010_IRQ_NUM 0
#define DT_N_S_soc_S_timer_e000e010_IRQ_LEVEL 0
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MATCHES_arm_armv7m_systick 1
#define DT_N_S_soc_S_timer_e000e010_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MODEL_IDX_0 "armv7m-systick"
#define DT_N_S_soc_S_timer_e000e010_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timer_e000e010_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timer_e000e010_P_reg {3758153744 /* 0xe000e010 */, 16 /* 0x10 */}
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0 3758153744
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1 16
#define DT_N_S_soc_S_timer_e000e010_P_reg_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_external_clock_source 0
#define DT_N_S_soc_S_timer_e000e010_P_external_clock_source_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible {"arm,armv7m-systick"}
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0 "arm,armv7m-systick"
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_UNQUOTED arm,armv7m-systick
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_TOKEN arm_armv7m_systick
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV7M_SYSTICK
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_LEN 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_dma_coherent 0
#define DT_N_S_soc_S_timer_e000e010_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timer_e000e010_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_wakeup_source 0
#define DT_N_S_soc_S_timer_e000e010_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timer_e000e010_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /otghs_fs_phy
 *
 * Node identifier: DT_N_S_otghs_fs_phy
 *
 * Binding (compatible = usb-nop-xceiv):
 *   $ZEPHYR_BASE\dts\bindings\phy\usb-nop-xceiv.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_otghs_fs_phy_PATH "/otghs_fs_phy"

/* Node's name with unit-address: */
#define DT_N_S_otghs_fs_phy_FULL_NAME "otghs_fs_phy"
#define DT_N_S_otghs_fs_phy_FULL_NAME_UNQUOTED otghs_fs_phy
#define DT_N_S_otghs_fs_phy_FULL_NAME_TOKEN otghs_fs_phy
#define DT_N_S_otghs_fs_phy_FULL_NAME_UPPER_TOKEN OTGHS_FS_PHY

/* Node parent (/) identifier: */
#define DT_N_S_otghs_fs_phy_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_otghs_fs_phy_CHILD_IDX 15

/* Helpers for dealing with node labels: */
#define DT_N_S_otghs_fs_phy_NODELABEL_NUM 1
#define DT_N_S_otghs_fs_phy_FOREACH_NODELABEL(fn) fn(otghs_fs_phy)
#define DT_N_S_otghs_fs_phy_FOREACH_NODELABEL_VARGS(fn, ...) fn(otghs_fs_phy, __VA_ARGS__)
#define DT_N_S_otghs_fs_phy_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_otghs_fs_phy_CHILD_NUM 0
#define DT_N_S_otghs_fs_phy_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_otghs_fs_phy_FOREACH_CHILD(fn) 
#define DT_N_S_otghs_fs_phy_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_otghs_fs_phy_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_otghs_fs_phy_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_otghs_fs_phy_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_otghs_fs_phy_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_otghs_fs_phy_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_otghs_fs_phy_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_otghs_fs_phy_HASH o2OMyBwvyxbYltqcvcFLzPkg8jqQm_Azar3MBmQRx1E

/* Node's dependency ordinal: */
#define DT_N_S_otghs_fs_phy_ORD 95
#define DT_N_S_otghs_fs_phy_ORD_STR_SORTABLE 00095

/* Ordinals for what this node depends on directly: */
#define DT_N_S_otghs_fs_phy_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_otghs_fs_phy_SUPPORTS_ORDS \
	96, /* /soc/usb@40040000 */
#define DT_N_NODELABEL_DT_N_S_otghs_fs_phy_IDX_0_C_TOKEN otghs_fs_phy

/* Existence and alternate IDs: */
#define DT_N_S_otghs_fs_phy_EXISTS 1
#define DT_N_INST_1_usb_nop_xceiv   DT_N_S_otghs_fs_phy
#define DT_N_NODELABEL_otghs_fs_phy DT_N_S_otghs_fs_phy

/* Macros for properties that are special in the specification: */
#define DT_N_S_otghs_fs_phy_REG_NUM 0
#define DT_N_S_otghs_fs_phy_FOREACH_REG(fn) 
#define DT_N_S_otghs_fs_phy_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_otghs_fs_phy_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_otghs_fs_phy_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_otghs_fs_phy_RANGES_NUM 0
#define DT_N_S_otghs_fs_phy_FOREACH_RANGE(fn) 
#define DT_N_S_otghs_fs_phy_IRQ_NUM 0
#define DT_N_S_otghs_fs_phy_IRQ_LEVEL 0
#define DT_N_S_otghs_fs_phy_COMPAT_MATCHES_usb_nop_xceiv 1
#define DT_N_S_otghs_fs_phy_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_otghs_fs_phy_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_otghs_fs_phy_P_compatible {"usb-nop-xceiv"}
#define DT_N_S_otghs_fs_phy_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_otghs_fs_phy_P_compatible_IDX_0 "usb-nop-xceiv"
#define DT_N_S_otghs_fs_phy_P_compatible_IDX_0_STRING_UNQUOTED usb-nop-xceiv
#define DT_N_S_otghs_fs_phy_P_compatible_IDX_0_STRING_TOKEN usb_nop_xceiv
#define DT_N_S_otghs_fs_phy_P_compatible_IDX_0_STRING_UPPER_TOKEN USB_NOP_XCEIV
#define DT_N_S_otghs_fs_phy_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_otghs_fs_phy, compatible, 0)
#define DT_N_S_otghs_fs_phy_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_otghs_fs_phy, compatible, 0)
#define DT_N_S_otghs_fs_phy_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_otghs_fs_phy, compatible, 0, __VA_ARGS__)
#define DT_N_S_otghs_fs_phy_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_otghs_fs_phy, compatible, 0, __VA_ARGS__)
#define DT_N_S_otghs_fs_phy_P_compatible_LEN 1
#define DT_N_S_otghs_fs_phy_P_compatible_EXISTS 1
#define DT_N_S_otghs_fs_phy_P_dma_coherent 0
#define DT_N_S_otghs_fs_phy_P_dma_coherent_EXISTS 1
#define DT_N_S_otghs_fs_phy_P_zephyr_deferred_init 0
#define DT_N_S_otghs_fs_phy_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_otghs_fs_phy_P_wakeup_source 0
#define DT_N_S_otghs_fs_phy_P_wakeup_source_EXISTS 1
#define DT_N_S_otghs_fs_phy_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_otghs_fs_phy_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/usb@40040000
 *
 * Node identifier: DT_N_S_soc_S_usb_40040000
 *
 * Binding (compatible = st,stm32-otghs):
 *   $ZEPHYR_BASE\dts\bindings\usb\st,stm32-otghs.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_usb_40040000_PATH "/soc/usb@40040000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_usb_40040000_FULL_NAME "usb@40040000"
#define DT_N_S_soc_S_usb_40040000_FULL_NAME_UNQUOTED usb@40040000
#define DT_N_S_soc_S_usb_40040000_FULL_NAME_TOKEN usb_40040000
#define DT_N_S_soc_S_usb_40040000_FULL_NAME_UPPER_TOKEN USB_40040000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_usb_40040000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_usb_40040000_CHILD_IDX 43

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_usb_40040000_NODELABEL_NUM 1
#define DT_N_S_soc_S_usb_40040000_FOREACH_NODELABEL(fn) fn(usbotg_hs)
#define DT_N_S_soc_S_usb_40040000_FOREACH_NODELABEL_VARGS(fn, ...) fn(usbotg_hs, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40040000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_usb_40040000_CHILD_NUM 0
#define DT_N_S_soc_S_usb_40040000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_usb_40040000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_usb_40040000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_usb_40040000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_usb_40040000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_usb_40040000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_usb_40040000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_usb_40040000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_usb_40040000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_usb_40040000_HASH hQX5a6h4YrwYkjEZ67iF2XLzK046iAbBlHG3GB49DxM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_usb_40040000_ORD 96
#define DT_N_S_soc_S_usb_40040000_ORD_STR_SORTABLE 00096

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_usb_40040000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	95, /* /otghs_fs_phy */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_usb_40040000_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_usb_40040000_IDX_0_C_TOKEN usbotg_hs

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_usb_40040000_EXISTS 1
#define DT_N_INST_0_st_stm32_otghs DT_N_S_soc_S_usb_40040000
#define DT_N_NODELABEL_usbotg_hs   DT_N_S_soc_S_usb_40040000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_usb_40040000_REG_NUM 1
#define DT_N_S_soc_S_usb_40040000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_REG_IDX_0_VAL_ADDRESS 1074003968 /* 0x40040000 */
#define DT_N_S_soc_S_usb_40040000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
#define DT_N_S_soc_S_usb_40040000_FOREACH_REG(fn) fn(DT_N_S_soc_S_usb_40040000, 0)
#define DT_N_S_soc_S_usb_40040000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40040000, 0)
#define DT_N_S_soc_S_usb_40040000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40040000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40040000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40040000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40040000_RANGES_NUM 0
#define DT_N_S_soc_S_usb_40040000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_usb_40040000_IRQ_NUM 3
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_0_VAL_irq 77
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_1_VAL_irq 74
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_2_VAL_irq 75
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_2_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_2_VAL_priority 0
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_2_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_IRQ_IDX_2_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_usb_40040000_IRQ_LEVEL 1
#define DT_N_S_soc_S_usb_40040000_IRQ_NAME_otghs_VAL_irq DT_N_S_soc_S_usb_40040000_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_usb_40040000_IRQ_NAME_otghs_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_IRQ_NAME_otghs_VAL_priority DT_N_S_soc_S_usb_40040000_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_usb_40040000_IRQ_NAME_otghs_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_IRQ_NAME_otghs_CONTROLLER DT_N_S_soc_S_usb_40040000_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_usb_40040000_IRQ_NAME_ep1_out_VAL_irq DT_N_S_soc_S_usb_40040000_IRQ_IDX_1_VAL_irq
#define DT_N_S_soc_S_usb_40040000_IRQ_NAME_ep1_out_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_IRQ_NAME_ep1_out_VAL_priority DT_N_S_soc_S_usb_40040000_IRQ_IDX_1_VAL_priority
#define DT_N_S_soc_S_usb_40040000_IRQ_NAME_ep1_out_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_IRQ_NAME_ep1_out_CONTROLLER DT_N_S_soc_S_usb_40040000_IRQ_IDX_1_CONTROLLER
#define DT_N_S_soc_S_usb_40040000_IRQ_NAME_ep1_in_VAL_irq DT_N_S_soc_S_usb_40040000_IRQ_IDX_2_VAL_irq
#define DT_N_S_soc_S_usb_40040000_IRQ_NAME_ep1_in_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_IRQ_NAME_ep1_in_VAL_priority DT_N_S_soc_S_usb_40040000_IRQ_IDX_2_VAL_priority
#define DT_N_S_soc_S_usb_40040000_IRQ_NAME_ep1_in_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_IRQ_NAME_ep1_in_CONTROLLER DT_N_S_soc_S_usb_40040000_IRQ_IDX_2_CONTROLLER
#define DT_N_S_soc_S_usb_40040000_COMPAT_MATCHES_st_stm32_otghs 1
#define DT_N_S_soc_S_usb_40040000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_usb_40040000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_COMPAT_MODEL_IDX_0 "stm32-otghs"
#define DT_N_S_soc_S_usb_40040000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_usb_40040000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_usb_40040000_P_reg {1074003968 /* 0x40040000 */, 262144 /* 0x40000 */}
#define DT_N_S_soc_S_usb_40040000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_reg_IDX_0 1074003968
#define DT_N_S_soc_S_usb_40040000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_reg_IDX_1 262144
#define DT_N_S_soc_S_usb_40040000_P_reg_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_interrupts {77 /* 0x4d */, 0 /* 0x0 */, 74 /* 0x4a */, 0 /* 0x0 */, 75 /* 0x4b */, 0 /* 0x0 */}
#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_0 77
#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_2 74
#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_4_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_4 75
#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_5_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_5 0
#define DT_N_S_soc_S_usb_40040000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_ram_size 4096
#define DT_N_S_soc_S_usb_40040000_P_ram_size_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_phys DT_N_S_otghs_fs_phy
#define DT_N_S_soc_S_usb_40040000_P_phys_IDX_0 DT_N_S_otghs_fs_phy
#define DT_N_S_soc_S_usb_40040000_P_phys_IDX_0_PH DT_N_S_otghs_fs_phy
#define DT_N_S_soc_S_usb_40040000_P_phys_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_phys_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40040000, phys, 0)
#define DT_N_S_soc_S_usb_40040000_P_phys_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40040000, phys, 0)
#define DT_N_S_soc_S_usb_40040000_P_phys_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40040000, phys, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40040000_P_phys_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40040000, phys, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40040000_P_phys_LEN 1
#define DT_N_S_soc_S_usb_40040000_P_phys_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_0_VAL_bus 48
#define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_0_VAL_bits 536870912
#define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_usb_40040000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_usb_40040000, clocks, 0, bits)
#define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40040000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_40040000, clocks, 0, bits)
#define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_1_VAL_bus 7
#define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_usb_40040000, clocks, 1, bus) \
	fn(DT_N_S_soc_S_usb_40040000, clocks, 1, bits)
#define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40040000, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_40040000, clocks, 1, bits)
#define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_usb_40040000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40040000, clocks, 0) \
	fn(DT_N_S_soc_S_usb_40040000, clocks, 1)
#define DT_N_S_soc_S_usb_40040000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40040000, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_40040000, clocks, 1)
#define DT_N_S_soc_S_usb_40040000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40040000, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_usb_40040000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40040000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40040000, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_40040000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40040000_P_clocks_LEN 2
#define DT_N_S_soc_S_usb_40040000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_num_bidir_endpoints 6
#define DT_N_S_soc_S_usb_40040000_P_num_bidir_endpoints_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_maximum_speed "full-speed"
#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_STRING_UNQUOTED full-speed
#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_STRING_TOKEN full_speed
#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_STRING_UPPER_TOKEN FULL_SPEED
#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_IDX_0 "full-speed"
#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_IDX_0_ENUM_VAL_full_speed_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_ENUM_VAL_full_speed_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40040000, maximum_speed, 0)
#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40040000, maximum_speed, 0)
#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40040000, maximum_speed, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40040000, maximum_speed, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_LEN 1
#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_status "disabled"
#define DT_N_S_soc_S_usb_40040000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_usb_40040000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_usb_40040000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_usb_40040000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_usb_40040000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_usb_40040000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40040000, status, 0)
#define DT_N_S_soc_S_usb_40040000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40040000, status, 0)
#define DT_N_S_soc_S_usb_40040000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40040000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40040000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40040000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40040000_P_status_LEN 1
#define DT_N_S_soc_S_usb_40040000_P_status_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_compatible {"st,stm32-otghs"}
#define DT_N_S_soc_S_usb_40040000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_compatible_IDX_0 "st,stm32-otghs"
#define DT_N_S_soc_S_usb_40040000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-otghs
#define DT_N_S_soc_S_usb_40040000_P_compatible_IDX_0_STRING_TOKEN st_stm32_otghs
#define DT_N_S_soc_S_usb_40040000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_OTGHS
#define DT_N_S_soc_S_usb_40040000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40040000, compatible, 0)
#define DT_N_S_soc_S_usb_40040000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40040000, compatible, 0)
#define DT_N_S_soc_S_usb_40040000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40040000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40040000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40040000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40040000_P_compatible_LEN 1
#define DT_N_S_soc_S_usb_40040000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names {"otghs", "ep1_out", "ep1_in"}
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_0 "otghs"
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_0_STRING_UNQUOTED otghs
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_0_STRING_TOKEN otghs
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN OTGHS
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_1 "ep1_out"
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_1_STRING_UNQUOTED ep1_out
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_1_STRING_TOKEN ep1_out
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN EP1_OUT
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_2_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_2 "ep1_in"
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_2_STRING_UNQUOTED ep1_in
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_2_STRING_TOKEN ep1_in
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN EP1_IN
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 0) \
	fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 1) \
	fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 2)
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 2)
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 2, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 2, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_LEN 3
#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_dma_coherent 0
#define DT_N_S_soc_S_usb_40040000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_usb_40040000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_wakeup_source 0
#define DT_N_S_soc_S_usb_40040000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_usb_40040000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_usb_40040000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /otgfs_phy
 *
 * Node identifier: DT_N_S_otgfs_phy
 *
 * Binding (compatible = usb-nop-xceiv):
 *   $ZEPHYR_BASE\dts\bindings\phy\usb-nop-xceiv.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_otgfs_phy_PATH "/otgfs_phy"

/* Node's name with unit-address: */
#define DT_N_S_otgfs_phy_FULL_NAME "otgfs_phy"
#define DT_N_S_otgfs_phy_FULL_NAME_UNQUOTED otgfs_phy
#define DT_N_S_otgfs_phy_FULL_NAME_TOKEN otgfs_phy
#define DT_N_S_otgfs_phy_FULL_NAME_UPPER_TOKEN OTGFS_PHY

/* Node parent (/) identifier: */
#define DT_N_S_otgfs_phy_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_otgfs_phy_CHILD_IDX 11

/* Helpers for dealing with node labels: */
#define DT_N_S_otgfs_phy_NODELABEL_NUM 1
#define DT_N_S_otgfs_phy_FOREACH_NODELABEL(fn) fn(otgfs_phy)
#define DT_N_S_otgfs_phy_FOREACH_NODELABEL_VARGS(fn, ...) fn(otgfs_phy, __VA_ARGS__)
#define DT_N_S_otgfs_phy_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_otgfs_phy_CHILD_NUM 0
#define DT_N_S_otgfs_phy_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_otgfs_phy_FOREACH_CHILD(fn) 
#define DT_N_S_otgfs_phy_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_otgfs_phy_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_otgfs_phy_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_otgfs_phy_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_otgfs_phy_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_otgfs_phy_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_otgfs_phy_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_otgfs_phy_HASH BjqGekc6eLiy_ZsqywPmRRzbKM6f0m4PZsLpNK3ktvU

/* Node's dependency ordinal: */
#define DT_N_S_otgfs_phy_ORD 97
#define DT_N_S_otgfs_phy_ORD_STR_SORTABLE 00097

/* Ordinals for what this node depends on directly: */
#define DT_N_S_otgfs_phy_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_otgfs_phy_SUPPORTS_ORDS \
	100, /* /soc/usb@50000000 */
#define DT_N_NODELABEL_DT_N_S_otgfs_phy_IDX_0_C_TOKEN otgfs_phy

/* Existence and alternate IDs: */
#define DT_N_S_otgfs_phy_EXISTS 1
#define DT_N_INST_0_usb_nop_xceiv DT_N_S_otgfs_phy
#define DT_N_NODELABEL_otgfs_phy  DT_N_S_otgfs_phy

/* Macros for properties that are special in the specification: */
#define DT_N_S_otgfs_phy_REG_NUM 0
#define DT_N_S_otgfs_phy_FOREACH_REG(fn) 
#define DT_N_S_otgfs_phy_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_otgfs_phy_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_otgfs_phy_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_otgfs_phy_RANGES_NUM 0
#define DT_N_S_otgfs_phy_FOREACH_RANGE(fn) 
#define DT_N_S_otgfs_phy_IRQ_NUM 0
#define DT_N_S_otgfs_phy_IRQ_LEVEL 0
#define DT_N_S_otgfs_phy_COMPAT_MATCHES_usb_nop_xceiv 1
#define DT_N_S_otgfs_phy_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_otgfs_phy_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_otgfs_phy_P_compatible {"usb-nop-xceiv"}
#define DT_N_S_otgfs_phy_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_otgfs_phy_P_compatible_IDX_0 "usb-nop-xceiv"
#define DT_N_S_otgfs_phy_P_compatible_IDX_0_STRING_UNQUOTED usb-nop-xceiv
#define DT_N_S_otgfs_phy_P_compatible_IDX_0_STRING_TOKEN usb_nop_xceiv
#define DT_N_S_otgfs_phy_P_compatible_IDX_0_STRING_UPPER_TOKEN USB_NOP_XCEIV
#define DT_N_S_otgfs_phy_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_otgfs_phy, compatible, 0)
#define DT_N_S_otgfs_phy_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_otgfs_phy, compatible, 0)
#define DT_N_S_otgfs_phy_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_otgfs_phy, compatible, 0, __VA_ARGS__)
#define DT_N_S_otgfs_phy_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_otgfs_phy, compatible, 0, __VA_ARGS__)
#define DT_N_S_otgfs_phy_P_compatible_LEN 1
#define DT_N_S_otgfs_phy_P_compatible_EXISTS 1
#define DT_N_S_otgfs_phy_P_dma_coherent 0
#define DT_N_S_otgfs_phy_P_dma_coherent_EXISTS 1
#define DT_N_S_otgfs_phy_P_zephyr_deferred_init 0
#define DT_N_S_otgfs_phy_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_otgfs_phy_P_wakeup_source 0
#define DT_N_S_otgfs_phy_P_wakeup_source_EXISTS 1
#define DT_N_S_otgfs_phy_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_otgfs_phy_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/usb_otg_fs_dm_pa11
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_PATH "/soc/pin-controller@40020000/usb_otg_fs_dm_pa11"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FULL_NAME "usb_otg_fs_dm_pa11"
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FULL_NAME_UNQUOTED usb_otg_fs_dm_pa11
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FULL_NAME_TOKEN usb_otg_fs_dm_pa11
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FULL_NAME_UPPER_TOKEN USB_OTG_FS_DM_PA11

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_CHILD_IDX 34

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FOREACH_NODELABEL(fn) fn(usb_otg_fs_dm_pa11)
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FOREACH_NODELABEL_VARGS(fn, ...) fn(usb_otg_fs_dm_pa11, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_HASH G4_YCm1jYlq0IjmE_bs3XY4Oul6K_J80Laao8Z0XAx4

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_ORD 98
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_ORD_STR_SORTABLE 00098

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_SUPPORTS_ORDS \
	100, /* /soc/usb@50000000 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_IDX_0_C_TOKEN usb_otg_fs_dm_pa11

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_EXISTS 1
#define DT_N_NODELABEL_usb_otg_fs_dm_pa11 DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_pinmux 362
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/usb_otg_fs_dp_pa12
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_PATH "/soc/pin-controller@40020000/usb_otg_fs_dp_pa12"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FULL_NAME "usb_otg_fs_dp_pa12"
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FULL_NAME_UNQUOTED usb_otg_fs_dp_pa12
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FULL_NAME_TOKEN usb_otg_fs_dp_pa12
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FULL_NAME_UPPER_TOKEN USB_OTG_FS_DP_PA12

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_CHILD_IDX 35

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FOREACH_NODELABEL(fn) fn(usb_otg_fs_dp_pa12)
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FOREACH_NODELABEL_VARGS(fn, ...) fn(usb_otg_fs_dp_pa12, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_HASH q2Nj2MtikV10QYkfa_RKcsiLGMLCcUgeSr6B1T_kDcM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_ORD 99
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_ORD_STR_SORTABLE 00099

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_SUPPORTS_ORDS \
	100, /* /soc/usb@50000000 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_IDX_0_C_TOKEN usb_otg_fs_dp_pa12

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_EXISTS 1
#define DT_N_NODELABEL_usb_otg_fs_dp_pa12 DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_pinmux 394
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/usb@50000000
 *
 * Node identifier: DT_N_S_soc_S_usb_50000000
 *
 * Binding (compatible = st,stm32-otgfs):
 *   $ZEPHYR_BASE\dts\bindings\usb\st,stm32-otgfs.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_usb_50000000_PATH "/soc/usb@50000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_usb_50000000_FULL_NAME "usb@50000000"
#define DT_N_S_soc_S_usb_50000000_FULL_NAME_UNQUOTED usb@50000000
#define DT_N_S_soc_S_usb_50000000_FULL_NAME_TOKEN usb_50000000
#define DT_N_S_soc_S_usb_50000000_FULL_NAME_UPPER_TOKEN USB_50000000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_usb_50000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_usb_50000000_CHILD_IDX 15

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_usb_50000000_NODELABEL_NUM 2
#define DT_N_S_soc_S_usb_50000000_FOREACH_NODELABEL(fn) fn(usbotg_fs) fn(zephyr_udc0)
#define DT_N_S_soc_S_usb_50000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(usbotg_fs, __VA_ARGS__) fn(zephyr_udc0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_usb_50000000_CHILD_NUM 0
#define DT_N_S_soc_S_usb_50000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_usb_50000000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_usb_50000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_usb_50000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_usb_50000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_usb_50000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_usb_50000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_usb_50000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_usb_50000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_usb_50000000_HASH 0xTou4PF1b__DltQ4r_PjAATOxQ7IbaClpZX57mZ8ek

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_usb_50000000_ORD 100
#define DT_N_S_soc_S_usb_50000000_ORD_STR_SORTABLE 00100

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_usb_50000000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	97, /* /otgfs_phy */ \
	98, /* /soc/pin-controller@40020000/usb_otg_fs_dm_pa11 */ \
	99, /* /soc/pin-controller@40020000/usb_otg_fs_dp_pa12 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_usb_50000000_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_usb_50000000_IDX_0_C_TOKEN usbotg_fs
#define DT_N_NODELABEL_DT_N_S_soc_S_usb_50000000_IDX_1_C_TOKEN zephyr_udc0

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_usb_50000000_EXISTS 1
#define DT_N_INST_0_st_stm32_otgfs DT_N_S_soc_S_usb_50000000
#define DT_N_NODELABEL_usbotg_fs   DT_N_S_soc_S_usb_50000000
#define DT_N_NODELABEL_zephyr_udc0 DT_N_S_soc_S_usb_50000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_usb_50000000_REG_NUM 1
#define DT_N_S_soc_S_usb_50000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_REG_IDX_0_VAL_ADDRESS 1342177280 /* 0x50000000 */
#define DT_N_S_soc_S_usb_50000000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
#define DT_N_S_soc_S_usb_50000000_FOREACH_REG(fn) fn(DT_N_S_soc_S_usb_50000000, 0)
#define DT_N_S_soc_S_usb_50000000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_usb_50000000, 0)
#define DT_N_S_soc_S_usb_50000000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_50000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_50000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_RANGES_NUM 0
#define DT_N_S_soc_S_usb_50000000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_usb_50000000_IRQ_NUM 1
#define DT_N_S_soc_S_usb_50000000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_IRQ_IDX_0_VAL_irq 67
#define DT_N_S_soc_S_usb_50000000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_usb_50000000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_usb_50000000_IRQ_LEVEL 1
#define DT_N_S_soc_S_usb_50000000_IRQ_NAME_otgfs_VAL_irq DT_N_S_soc_S_usb_50000000_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_usb_50000000_IRQ_NAME_otgfs_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_IRQ_NAME_otgfs_VAL_priority DT_N_S_soc_S_usb_50000000_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_usb_50000000_IRQ_NAME_otgfs_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_IRQ_NAME_otgfs_CONTROLLER DT_N_S_soc_S_usb_50000000_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_usb_50000000_COMPAT_MATCHES_st_stm32_otgfs 1
#define DT_N_S_soc_S_usb_50000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_usb_50000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_COMPAT_MODEL_IDX_0 "stm32-otgfs"
#define DT_N_S_soc_S_usb_50000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_usb_50000000_PINCTRL_NUM 1
#define DT_N_S_soc_S_usb_50000000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_usb_50000000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_usb_50000000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_usb_50000000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11
#define DT_N_S_soc_S_usb_50000000_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12

/* Generic property macros: */
#define DT_N_S_soc_S_usb_50000000_P_reg {1342177280 /* 0x50000000 */, 262144 /* 0x40000 */}
#define DT_N_S_soc_S_usb_50000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_reg_IDX_0 1342177280
#define DT_N_S_soc_S_usb_50000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_reg_IDX_1 262144
#define DT_N_S_soc_S_usb_50000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_interrupts {67 /* 0x43 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_usb_50000000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_interrupts_IDX_0 67
#define DT_N_S_soc_S_usb_50000000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_usb_50000000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_0_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_50000000, pinctrl_0, 0) \
	fn(DT_N_S_soc_S_usb_50000000, pinctrl_0, 1)
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_50000000, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_50000000, pinctrl_0, 1)
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_50000000, pinctrl_0, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_usb_50000000, pinctrl_0, 1, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_50000000, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_50000000, pinctrl_0, 1, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_0_LEN 2
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_50000000, pinctrl_names, 0)
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_50000000, pinctrl_names, 0)
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_50000000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_50000000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_usb_50000000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_ram_size 1280
#define DT_N_S_soc_S_usb_50000000_P_ram_size_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_phys DT_N_S_otgfs_phy
#define DT_N_S_soc_S_usb_50000000_P_phys_IDX_0 DT_N_S_otgfs_phy
#define DT_N_S_soc_S_usb_50000000_P_phys_IDX_0_PH DT_N_S_otgfs_phy
#define DT_N_S_soc_S_usb_50000000_P_phys_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_phys_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_50000000, phys, 0)
#define DT_N_S_soc_S_usb_50000000_P_phys_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_50000000, phys, 0)
#define DT_N_S_soc_S_usb_50000000_P_phys_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_50000000, phys, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_P_phys_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_50000000, phys, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_P_phys_LEN 1
#define DT_N_S_soc_S_usb_50000000_P_phys_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_usb_50000000_P_clocks_IDX_0_VAL_bus 52
#define DT_N_S_soc_S_usb_50000000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_clocks_IDX_0_VAL_bits 128
#define DT_N_S_soc_S_usb_50000000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_usb_50000000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_usb_50000000, clocks, 0, bits)
#define DT_N_S_soc_S_usb_50000000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_usb_50000000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_50000000, clocks, 0, bits)
#define DT_N_S_soc_S_usb_50000000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_usb_50000000_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_usb_50000000_P_clocks_IDX_1_VAL_bus 7
#define DT_N_S_soc_S_usb_50000000_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_usb_50000000_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_usb_50000000, clocks, 1, bus) \
	fn(DT_N_S_soc_S_usb_50000000, clocks, 1, bits)
#define DT_N_S_soc_S_usb_50000000_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_usb_50000000, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_50000000, clocks, 1, bits)
#define DT_N_S_soc_S_usb_50000000_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_usb_50000000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_50000000, clocks, 0) \
	fn(DT_N_S_soc_S_usb_50000000, clocks, 1)
#define DT_N_S_soc_S_usb_50000000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_50000000, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_50000000, clocks, 1)
#define DT_N_S_soc_S_usb_50000000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_50000000, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_usb_50000000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_50000000, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_50000000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_P_clocks_LEN 2
#define DT_N_S_soc_S_usb_50000000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_num_bidir_endpoints 4
#define DT_N_S_soc_S_usb_50000000_P_num_bidir_endpoints_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_maximum_speed "full-speed"
#define DT_N_S_soc_S_usb_50000000_P_maximum_speed_STRING_UNQUOTED full-speed
#define DT_N_S_soc_S_usb_50000000_P_maximum_speed_STRING_TOKEN full_speed
#define DT_N_S_soc_S_usb_50000000_P_maximum_speed_STRING_UPPER_TOKEN FULL_SPEED
#define DT_N_S_soc_S_usb_50000000_P_maximum_speed_IDX_0 "full-speed"
#define DT_N_S_soc_S_usb_50000000_P_maximum_speed_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_maximum_speed_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_usb_50000000_P_maximum_speed_IDX_0_ENUM_VAL_full_speed_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_maximum_speed_ENUM_VAL_full_speed_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_maximum_speed_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_50000000, maximum_speed, 0)
#define DT_N_S_soc_S_usb_50000000_P_maximum_speed_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_50000000, maximum_speed, 0)
#define DT_N_S_soc_S_usb_50000000_P_maximum_speed_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_50000000, maximum_speed, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_P_maximum_speed_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_50000000, maximum_speed, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_P_maximum_speed_LEN 1
#define DT_N_S_soc_S_usb_50000000_P_maximum_speed_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_status "okay"
#define DT_N_S_soc_S_usb_50000000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_usb_50000000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_usb_50000000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_usb_50000000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_usb_50000000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_usb_50000000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_50000000, status, 0)
#define DT_N_S_soc_S_usb_50000000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_50000000, status, 0)
#define DT_N_S_soc_S_usb_50000000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_50000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_50000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_P_status_LEN 1
#define DT_N_S_soc_S_usb_50000000_P_status_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_compatible {"st,stm32-otgfs"}
#define DT_N_S_soc_S_usb_50000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_compatible_IDX_0 "st,stm32-otgfs"
#define DT_N_S_soc_S_usb_50000000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-otgfs
#define DT_N_S_soc_S_usb_50000000_P_compatible_IDX_0_STRING_TOKEN st_stm32_otgfs
#define DT_N_S_soc_S_usb_50000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_OTGFS
#define DT_N_S_soc_S_usb_50000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_50000000, compatible, 0)
#define DT_N_S_soc_S_usb_50000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_50000000, compatible, 0)
#define DT_N_S_soc_S_usb_50000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_50000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_50000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_P_compatible_LEN 1
#define DT_N_S_soc_S_usb_50000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_interrupt_names {"otgfs"}
#define DT_N_S_soc_S_usb_50000000_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_interrupt_names_IDX_0 "otgfs"
#define DT_N_S_soc_S_usb_50000000_P_interrupt_names_IDX_0_STRING_UNQUOTED otgfs
#define DT_N_S_soc_S_usb_50000000_P_interrupt_names_IDX_0_STRING_TOKEN otgfs
#define DT_N_S_soc_S_usb_50000000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN OTGFS
#define DT_N_S_soc_S_usb_50000000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_50000000, interrupt_names, 0)
#define DT_N_S_soc_S_usb_50000000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_50000000, interrupt_names, 0)
#define DT_N_S_soc_S_usb_50000000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_50000000, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_50000000, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_50000000_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_usb_50000000_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_dma_coherent 0
#define DT_N_S_soc_S_usb_50000000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_usb_50000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_wakeup_source 0
#define DT_N_S_soc_S_usb_50000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_usb_50000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_usb_50000000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/watchdog@40002c00
 *
 * Node identifier: DT_N_S_soc_S_watchdog_40002c00
 *
 * Binding (compatible = st,stm32-window-watchdog):
 *   $ZEPHYR_BASE\dts\bindings\watchdog\st,stm32-window-watchdog.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_watchdog_40002c00_PATH "/soc/watchdog@40002c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_watchdog_40002c00_FULL_NAME "watchdog@40002c00"
#define DT_N_S_soc_S_watchdog_40002c00_FULL_NAME_UNQUOTED watchdog@40002c00
#define DT_N_S_soc_S_watchdog_40002c00_FULL_NAME_TOKEN watchdog_40002c00
#define DT_N_S_soc_S_watchdog_40002c00_FULL_NAME_UPPER_TOKEN WATCHDOG_40002C00

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_watchdog_40002c00_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_watchdog_40002c00_CHILD_IDX 7

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_watchdog_40002c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_NODELABEL(fn) fn(wwdg)
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(wwdg, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_watchdog_40002c00_CHILD_NUM 0
#define DT_N_S_soc_S_watchdog_40002c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_watchdog_40002c00_HASH NKEpaR6mtDKOWUZ_R2tC3uFejChIy267XTRT9LC__CA

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_watchdog_40002c00_ORD 101
#define DT_N_S_soc_S_watchdog_40002c00_ORD_STR_SORTABLE 00101

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_watchdog_40002c00_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_watchdog_40002c00_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_watchdog_40002c00_IDX_0_C_TOKEN wwdg

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_watchdog_40002c00_EXISTS 1
#define DT_N_INST_0_st_stm32_window_watchdog DT_N_S_soc_S_watchdog_40002c00
#define DT_N_NODELABEL_wwdg                  DT_N_S_soc_S_watchdog_40002c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_watchdog_40002c00_REG_NUM 1
#define DT_N_S_soc_S_watchdog_40002c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_REG_IDX_0_VAL_ADDRESS 1073753088 /* 0x40002c00 */
#define DT_N_S_soc_S_watchdog_40002c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_watchdog_40002c00, 0)
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_40002c00, 0)
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_40002c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_40002c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40002c00_RANGES_NUM 0
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_watchdog_40002c00_IRQ_NUM 1
#define DT_N_S_soc_S_watchdog_40002c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_IRQ_IDX_0_VAL_irq 0
#define DT_N_S_soc_S_watchdog_40002c00_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_watchdog_40002c00_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_watchdog_40002c00_IRQ_LEVEL 1
#define DT_N_S_soc_S_watchdog_40002c00_COMPAT_MATCHES_st_stm32_window_watchdog 1
#define DT_N_S_soc_S_watchdog_40002c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_watchdog_40002c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_COMPAT_MODEL_IDX_0 "stm32-window-watchdog"
#define DT_N_S_soc_S_watchdog_40002c00_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_watchdog_40002c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_watchdog_40002c00_P_reg {1073753088 /* 0x40002c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_watchdog_40002c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_reg_IDX_0 1073753088
#define DT_N_S_soc_S_watchdog_40002c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_watchdog_40002c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_IDX_0_VAL_bits 2048
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_watchdog_40002c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_watchdog_40002c00, clocks, 0, bits)
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_40002c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_watchdog_40002c00, clocks, 0, bits)
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_40002c00, clocks, 0)
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_40002c00, clocks, 0)
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_40002c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_40002c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_LEN 1
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_status "disabled"
#define DT_N_S_soc_S_watchdog_40002c00_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_watchdog_40002c00_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_watchdog_40002c00_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_watchdog_40002c00_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_watchdog_40002c00_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_watchdog_40002c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_40002c00, status, 0)
#define DT_N_S_soc_S_watchdog_40002c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_40002c00, status, 0)
#define DT_N_S_soc_S_watchdog_40002c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_40002c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40002c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_40002c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40002c00_P_status_LEN 1
#define DT_N_S_soc_S_watchdog_40002c00_P_status_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible {"st,stm32-window-watchdog"}
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_IDX_0 "st,stm32-window-watchdog"
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-window-watchdog
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_window_watchdog
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_WINDOW_WATCHDOG
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_40002c00, compatible, 0)
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_40002c00, compatible, 0)
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_40002c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_40002c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_LEN 1
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_interrupts {0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_watchdog_40002c00_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_interrupts_IDX_0 0
#define DT_N_S_soc_S_watchdog_40002c00_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_watchdog_40002c00_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_dma_coherent 0
#define DT_N_S_soc_S_watchdog_40002c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_watchdog_40002c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_wakeup_source 0
#define DT_N_S_soc_S_watchdog_40002c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_watchdog_40002c00_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/watchdog@40003000
 *
 * Node identifier: DT_N_S_soc_S_watchdog_40003000
 *
 * Binding (compatible = st,stm32-watchdog):
 *   $ZEPHYR_BASE\dts\bindings\watchdog\st,stm32-watchdog.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_watchdog_40003000_PATH "/soc/watchdog@40003000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_watchdog_40003000_FULL_NAME "watchdog@40003000"
#define DT_N_S_soc_S_watchdog_40003000_FULL_NAME_UNQUOTED watchdog@40003000
#define DT_N_S_soc_S_watchdog_40003000_FULL_NAME_TOKEN watchdog_40003000
#define DT_N_S_soc_S_watchdog_40003000_FULL_NAME_UPPER_TOKEN WATCHDOG_40003000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_watchdog_40003000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_watchdog_40003000_CHILD_IDX 6

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_watchdog_40003000_NODELABEL_NUM 1
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_NODELABEL(fn) fn(iwdg)
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_NODELABEL_VARGS(fn, ...) fn(iwdg, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_watchdog_40003000_CHILD_NUM 0
#define DT_N_S_soc_S_watchdog_40003000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_watchdog_40003000_HASH ZgrqJ_c2LlWOgbyPiYriITNa7e_ieqQvmB0duI6_QGU

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_watchdog_40003000_ORD 102
#define DT_N_S_soc_S_watchdog_40003000_ORD_STR_SORTABLE 00102

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_watchdog_40003000_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_watchdog_40003000_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_watchdog_40003000_IDX_0_C_TOKEN iwdg

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_watchdog_40003000_EXISTS 1
#define DT_N_ALIAS_watchdog0          DT_N_S_soc_S_watchdog_40003000
#define DT_N_INST_0_st_stm32_watchdog DT_N_S_soc_S_watchdog_40003000
#define DT_N_NODELABEL_iwdg           DT_N_S_soc_S_watchdog_40003000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_watchdog_40003000_REG_NUM 1
#define DT_N_S_soc_S_watchdog_40003000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_REG_IDX_0_VAL_ADDRESS 1073754112 /* 0x40003000 */
#define DT_N_S_soc_S_watchdog_40003000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_REG(fn) fn(DT_N_S_soc_S_watchdog_40003000, 0)
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_40003000, 0)
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_40003000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_40003000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40003000_RANGES_NUM 0
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_watchdog_40003000_IRQ_NUM 0
#define DT_N_S_soc_S_watchdog_40003000_IRQ_LEVEL 0
#define DT_N_S_soc_S_watchdog_40003000_COMPAT_MATCHES_st_stm32_watchdog 1
#define DT_N_S_soc_S_watchdog_40003000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_watchdog_40003000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_COMPAT_MODEL_IDX_0 "stm32-watchdog"
#define DT_N_S_soc_S_watchdog_40003000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_watchdog_40003000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_watchdog_40003000_P_reg {1073754112 /* 0x40003000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_watchdog_40003000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_reg_IDX_0 1073754112
#define DT_N_S_soc_S_watchdog_40003000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_watchdog_40003000_P_reg_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_status "okay"
#define DT_N_S_soc_S_watchdog_40003000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_watchdog_40003000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_watchdog_40003000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_watchdog_40003000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_watchdog_40003000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_watchdog_40003000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_40003000, status, 0)
#define DT_N_S_soc_S_watchdog_40003000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_40003000, status, 0)
#define DT_N_S_soc_S_watchdog_40003000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_40003000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40003000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_40003000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40003000_P_status_LEN 1
#define DT_N_S_soc_S_watchdog_40003000_P_status_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_compatible {"st,stm32-watchdog"}
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_IDX_0 "st,stm32-watchdog"
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-watchdog
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_IDX_0_STRING_TOKEN st_stm32_watchdog
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_WATCHDOG
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_40003000, compatible, 0)
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_40003000, compatible, 0)
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_40003000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_40003000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_LEN 1
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_dma_coherent 0
#define DT_N_S_soc_S_watchdog_40003000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_watchdog_40003000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_wakeup_source 0
#define DT_N_S_soc_S_watchdog_40003000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_watchdog_40003000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/eth_crs_dv_pa7
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_PATH "/soc/pin-controller@40020000/eth_crs_dv_pa7"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FULL_NAME "eth_crs_dv_pa7"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FULL_NAME_UNQUOTED eth_crs_dv_pa7
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FULL_NAME_TOKEN eth_crs_dv_pa7
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FULL_NAME_UPPER_TOKEN ETH_CRS_DV_PA7

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_CHILD_IDX 15

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FOREACH_NODELABEL(fn) fn(eth_crs_dv_pa7)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FOREACH_NODELABEL_VARGS(fn, ...) fn(eth_crs_dv_pa7, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_HASH Si1vPiJ7z_MfT1M1MjtWB3zVV5PHM1LIHLc348xT8dE

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_ORD 103
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_ORD_STR_SORTABLE 00103

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_SUPPORTS_ORDS \
	110, /* /soc/ethernet@40028000 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_IDX_0_C_TOKEN eth_crs_dv_pa7

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_EXISTS 1
#define DT_N_NODELABEL_eth_crs_dv_pa7 DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_pinmux 235
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/eth_ref_clk_pa1
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_PATH "/soc/pin-controller@40020000/eth_ref_clk_pa1"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FULL_NAME "eth_ref_clk_pa1"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FULL_NAME_UNQUOTED eth_ref_clk_pa1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FULL_NAME_TOKEN eth_ref_clk_pa1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FULL_NAME_UPPER_TOKEN ETH_REF_CLK_PA1

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_CHILD_IDX 13

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FOREACH_NODELABEL(fn) fn(eth_ref_clk_pa1)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FOREACH_NODELABEL_VARGS(fn, ...) fn(eth_ref_clk_pa1, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_HASH 78RrZXN2e2zPle0uayaYT3RgPuUyTxrWCKwm5V1gdTU

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_ORD 104
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_ORD_STR_SORTABLE 00104

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_SUPPORTS_ORDS \
	110, /* /soc/ethernet@40028000 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_IDX_0_C_TOKEN eth_ref_clk_pa1

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_EXISTS 1
#define DT_N_NODELABEL_eth_ref_clk_pa1 DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_pinmux 43
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/eth_rxd0_pc4
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_PATH "/soc/pin-controller@40020000/eth_rxd0_pc4"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FULL_NAME "eth_rxd0_pc4"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FULL_NAME_UNQUOTED eth_rxd0_pc4
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FULL_NAME_TOKEN eth_rxd0_pc4
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FULL_NAME_UPPER_TOKEN ETH_RXD0_PC4

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_CHILD_IDX 18

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FOREACH_NODELABEL(fn) fn(eth_rxd0_pc4)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FOREACH_NODELABEL_VARGS(fn, ...) fn(eth_rxd0_pc4, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_HASH bPPjKBTw3YoCbcQq2SqMOQyT0t5wxjyWPfp7Mk0GXU4

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_ORD 105
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_ORD_STR_SORTABLE 00105

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_SUPPORTS_ORDS \
	110, /* /soc/ethernet@40028000 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_IDX_0_C_TOKEN eth_rxd0_pc4

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_EXISTS 1
#define DT_N_NODELABEL_eth_rxd0_pc4 DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_pinmux 1163
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/eth_rxd1_pc5
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_PATH "/soc/pin-controller@40020000/eth_rxd1_pc5"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FULL_NAME "eth_rxd1_pc5"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FULL_NAME_UNQUOTED eth_rxd1_pc5
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FULL_NAME_TOKEN eth_rxd1_pc5
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FULL_NAME_UPPER_TOKEN ETH_RXD1_PC5

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_CHILD_IDX 19

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FOREACH_NODELABEL(fn) fn(eth_rxd1_pc5)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FOREACH_NODELABEL_VARGS(fn, ...) fn(eth_rxd1_pc5, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_HASH hRn2ZsMYXoevAOchTyN1RPNLaxWRsX9uXb3FM007Xe8

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_ORD 106
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_ORD_STR_SORTABLE 00106

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_SUPPORTS_ORDS \
	110, /* /soc/ethernet@40028000 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_IDX_0_C_TOKEN eth_rxd1_pc5

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_EXISTS 1
#define DT_N_NODELABEL_eth_rxd1_pc5 DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_pinmux 1195
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/eth_tx_en_pg11
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_PATH "/soc/pin-controller@40020000/eth_tx_en_pg11"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FULL_NAME "eth_tx_en_pg11"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FULL_NAME_UNQUOTED eth_tx_en_pg11
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FULL_NAME_TOKEN eth_tx_en_pg11
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FULL_NAME_UPPER_TOKEN ETH_TX_EN_PG11

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_CHILD_IDX 20

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FOREACH_NODELABEL(fn) fn(eth_tx_en_pg11)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FOREACH_NODELABEL_VARGS(fn, ...) fn(eth_tx_en_pg11, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_HASH e_OKYZMRIRMJfI_RCJbVRMnP186N6XE0ZPg5B3HkWSw

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_ORD 107
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_ORD_STR_SORTABLE 00107

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_SUPPORTS_ORDS \
	110, /* /soc/ethernet@40028000 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_IDX_0_C_TOKEN eth_tx_en_pg11

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_EXISTS 1
#define DT_N_NODELABEL_eth_tx_en_pg11 DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_pinmux 3435
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/eth_txd0_pg13
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_PATH "/soc/pin-controller@40020000/eth_txd0_pg13"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FULL_NAME "eth_txd0_pg13"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FULL_NAME_UNQUOTED eth_txd0_pg13
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FULL_NAME_TOKEN eth_txd0_pg13
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FULL_NAME_UPPER_TOKEN ETH_TXD0_PG13

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_CHILD_IDX 21

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FOREACH_NODELABEL(fn) fn(eth_txd0_pg13)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FOREACH_NODELABEL_VARGS(fn, ...) fn(eth_txd0_pg13, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_HASH A1vW9Z1jwsJHBXXb9Z_SlboqpBGUraCDzJ5sFBwbjec

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_ORD 108
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_ORD_STR_SORTABLE 00108

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_SUPPORTS_ORDS \
	110, /* /soc/ethernet@40028000 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_IDX_0_C_TOKEN eth_txd0_pg13

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_EXISTS 1
#define DT_N_NODELABEL_eth_txd0_pg13 DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_pinmux 3499
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/eth_txd1_pb13
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_PATH "/soc/pin-controller@40020000/eth_txd1_pb13"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FULL_NAME "eth_txd1_pb13"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FULL_NAME_UNQUOTED eth_txd1_pb13
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FULL_NAME_TOKEN eth_txd1_pb13
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FULL_NAME_UPPER_TOKEN ETH_TXD1_PB13

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_CHILD_IDX 16

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FOREACH_NODELABEL(fn) fn(eth_txd1_pb13)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FOREACH_NODELABEL_VARGS(fn, ...) fn(eth_txd1_pb13, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_HASH QGwVsqklmkyTbvT72ZeJD5AksgmJaGbIgoj7Rey6fHM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_ORD 109
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_ORD_STR_SORTABLE 00109

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_SUPPORTS_ORDS \
	110, /* /soc/ethernet@40028000 */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_IDX_0_C_TOKEN eth_txd1_pb13

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_EXISTS 1
#define DT_N_NODELABEL_eth_txd1_pb13 DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_pinmux 939
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/ethernet@40028000
 *
 * Node identifier: DT_N_S_soc_S_ethernet_40028000
 *
 * Binding (compatible = st,stm32-ethernet):
 *   $ZEPHYR_BASE\dts\bindings\ethernet\st,stm32-ethernet.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_ethernet_40028000_PATH "/soc/ethernet@40028000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_ethernet_40028000_FULL_NAME "ethernet@40028000"
#define DT_N_S_soc_S_ethernet_40028000_FULL_NAME_UNQUOTED ethernet@40028000
#define DT_N_S_soc_S_ethernet_40028000_FULL_NAME_TOKEN ethernet_40028000
#define DT_N_S_soc_S_ethernet_40028000_FULL_NAME_UPPER_TOKEN ETHERNET_40028000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_ethernet_40028000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_ethernet_40028000_CHILD_IDX 51

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_ethernet_40028000_NODELABEL_NUM 1
#define DT_N_S_soc_S_ethernet_40028000_FOREACH_NODELABEL(fn) fn(mac)
#define DT_N_S_soc_S_ethernet_40028000_FOREACH_NODELABEL_VARGS(fn, ...) fn(mac, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_ethernet_40028000_CHILD_NUM 1
#define DT_N_S_soc_S_ethernet_40028000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_ethernet_40028000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio)
#define DT_N_S_soc_S_ethernet_40028000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio)
#define DT_N_S_soc_S_ethernet_40028000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio)
#define DT_N_S_soc_S_ethernet_40028000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio)
#define DT_N_S_soc_S_ethernet_40028000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_ethernet_40028000_HASH NBHLaJx7ay1JQmiZCtQoklPEGDXvh9V0u5wy5wSK0dE

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_ethernet_40028000_ORD 110
#define DT_N_S_soc_S_ethernet_40028000_ORD_STR_SORTABLE 00110

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_ethernet_40028000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	103, /* /soc/pin-controller@40020000/eth_crs_dv_pa7 */ \
	104, /* /soc/pin-controller@40020000/eth_ref_clk_pa1 */ \
	105, /* /soc/pin-controller@40020000/eth_rxd0_pc4 */ \
	106, /* /soc/pin-controller@40020000/eth_rxd1_pc5 */ \
	107, /* /soc/pin-controller@40020000/eth_tx_en_pg11 */ \
	108, /* /soc/pin-controller@40020000/eth_txd0_pg13 */ \
	109, /* /soc/pin-controller@40020000/eth_txd1_pb13 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_ethernet_40028000_SUPPORTS_ORDS \
	113, /* /soc/ethernet@40028000/mdio */
#define DT_N_NODELABEL_DT_N_S_soc_S_ethernet_40028000_IDX_0_C_TOKEN mac

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_ethernet_40028000_EXISTS 1
#define DT_N_INST_0_st_stm32_ethernet DT_N_S_soc_S_ethernet_40028000
#define DT_N_NODELABEL_mac            DT_N_S_soc_S_ethernet_40028000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_ethernet_40028000_REG_NUM 1
#define DT_N_S_soc_S_ethernet_40028000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_REG_IDX_0_VAL_ADDRESS 1073905664 /* 0x40028000 */
#define DT_N_S_soc_S_ethernet_40028000_REG_IDX_0_VAL_SIZE 32768 /* 0x8000 */
#define DT_N_S_soc_S_ethernet_40028000_FOREACH_REG(fn) fn(DT_N_S_soc_S_ethernet_40028000, 0)
#define DT_N_S_soc_S_ethernet_40028000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, 0)
#define DT_N_S_soc_S_ethernet_40028000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_RANGES_NUM 0
#define DT_N_S_soc_S_ethernet_40028000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_ethernet_40028000_IRQ_NUM 1
#define DT_N_S_soc_S_ethernet_40028000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_IRQ_IDX_0_VAL_irq 61
#define DT_N_S_soc_S_ethernet_40028000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_ethernet_40028000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_ethernet_40028000_IRQ_LEVEL 1
#define DT_N_S_soc_S_ethernet_40028000_COMPAT_MATCHES_st_stm32_ethernet 1
#define DT_N_S_soc_S_ethernet_40028000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_ethernet_40028000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_COMPAT_MODEL_IDX_0 "stm32-ethernet"
#define DT_N_S_soc_S_ethernet_40028000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_ethernet_40028000_PINCTRL_NUM 1
#define DT_N_S_soc_S_ethernet_40028000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_ethernet_40028000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_ethernet_40028000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_ethernet_40028000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4
#define DT_N_S_soc_S_ethernet_40028000_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5
#define DT_N_S_soc_S_ethernet_40028000_PINCTRL_NAME_default_IDX_2_PH DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1
#define DT_N_S_soc_S_ethernet_40028000_PINCTRL_NAME_default_IDX_3_PH DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7
#define DT_N_S_soc_S_ethernet_40028000_PINCTRL_NAME_default_IDX_4_PH DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11
#define DT_N_S_soc_S_ethernet_40028000_PINCTRL_NAME_default_IDX_5_PH DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13
#define DT_N_S_soc_S_ethernet_40028000_PINCTRL_NAME_default_IDX_6_PH DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13

/* Generic property macros: */
#define DT_N_S_soc_S_ethernet_40028000_P_reg {1073905664 /* 0x40028000 */, 32768 /* 0x8000 */}
#define DT_N_S_soc_S_ethernet_40028000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_reg_IDX_0 1073905664
#define DT_N_S_soc_S_ethernet_40028000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_reg_IDX_1 32768
#define DT_N_S_soc_S_ethernet_40028000_P_reg_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_0_VAL_bus 48
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_0_VAL_bits 33554432
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_ethernet_40028000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 0, bits)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 0, bits)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_0_NAME "stm-eth"
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_stm_eth_IDX 0
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_stm_eth_FOREACH_CELL(fn) fn(DT_N_S_soc_S_ethernet_40028000, clocks, stm_eth, bus) \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, stm_eth, bits)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_stm_eth_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, clocks, stm_eth, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, stm_eth, bits)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_stm_eth_NUM_CELLS 2
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_stm_eth_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_stm_eth_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_stm_eth_VAL_bus DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_0_VAL_bus
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_stm_eth_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_stm_eth_VAL_bits DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_0_VAL_bits
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_stm_eth_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_1_VAL_bus 48
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_1_VAL_bits 67108864
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_ethernet_40028000, clocks, 1, bus) \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 1, bits)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 1, bits)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_1_NAME "mac-clk-tx"
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_tx_IDX 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_tx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_ethernet_40028000, clocks, mac_clk_tx, bus) \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, mac_clk_tx, bits)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_tx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, clocks, mac_clk_tx, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, mac_clk_tx, bits)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_tx_NUM_CELLS 2
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_tx_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_tx_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_tx_VAL_bus DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_1_VAL_bus
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_tx_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_tx_VAL_bits DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_1_VAL_bits
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_tx_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_2_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_2_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_2_VAL_bus 48
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_2_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_2_VAL_bits 134217728
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_2_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_2_FOREACH_CELL(fn) fn(DT_N_S_soc_S_ethernet_40028000, clocks, 2, bus) \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 2, bits)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_2_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, clocks, 2, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 2, bits)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_2_NUM_CELLS 2
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_2_NAME "mac-clk-rx"
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_rx_IDX 2
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_rx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_ethernet_40028000, clocks, mac_clk_rx, bus) \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, mac_clk_rx, bits)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_rx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, clocks, mac_clk_rx, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, mac_clk_rx, bits)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_rx_NUM_CELLS 2
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_rx_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_rx_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_rx_VAL_bus DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_2_VAL_bus
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_rx_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_rx_VAL_bits DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_2_VAL_bits
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_rx_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_3_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_3_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_3_VAL_bus 48
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_3_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_3_VAL_bits 268435456
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_3_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_3_FOREACH_CELL(fn) fn(DT_N_S_soc_S_ethernet_40028000, clocks, 3, bus) \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 3, bits)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_3_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, clocks, 3, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 3, bits)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_3_NUM_CELLS 2
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_3_NAME "mac-clk-ptp"
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_ptp_IDX 3
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_ptp_FOREACH_CELL(fn) fn(DT_N_S_soc_S_ethernet_40028000, clocks, mac_clk_ptp, bus) \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, mac_clk_ptp, bits)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_ptp_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, clocks, mac_clk_ptp, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, mac_clk_ptp, bits)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_ptp_NUM_CELLS 2
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_ptp_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_ptp_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_ptp_VAL_bus DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_3_VAL_bus
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_ptp_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_ptp_VAL_bits DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_3_VAL_bits
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_NAME_mac_clk_ptp_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000, clocks, 0) \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 1) \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 2) \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 3)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 3)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 3, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clocks, 3, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_LEN 4
#define DT_N_S_soc_S_ethernet_40028000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names {"stm-eth", "mac-clk-tx", "mac-clk-rx", "mac-clk-ptp"}
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_0 "stm-eth"
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_0_STRING_UNQUOTED stm-eth
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_0_STRING_TOKEN stm_eth
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_0_STRING_UPPER_TOKEN STM_ETH
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_1 "mac-clk-tx"
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_1_STRING_UNQUOTED mac-clk-tx
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_1_STRING_TOKEN mac_clk_tx
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_1_STRING_UPPER_TOKEN MAC_CLK_TX
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_2_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_2 "mac-clk-rx"
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_2_STRING_UNQUOTED mac-clk-rx
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_2_STRING_TOKEN mac_clk_rx
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_2_STRING_UPPER_TOKEN MAC_CLK_RX
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_3_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_3 "mac-clk-ptp"
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_3_STRING_UNQUOTED mac-clk-ptp
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_3_STRING_TOKEN mac_clk_ptp
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_3_STRING_UPPER_TOKEN MAC_CLK_PTP
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 0) \
	fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 1) \
	fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 2) \
	fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 3)
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 3)
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 3, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 3, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_LEN 4
#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_interrupts {61 /* 0x3d */, 0 /* 0x0 */}
#define DT_N_S_soc_S_ethernet_40028000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_interrupts_IDX_0 61
#define DT_N_S_soc_S_ethernet_40028000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_ethernet_40028000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_2 DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_2_PH DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_2_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_3 DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_3_PH DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_3_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_4 DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_4_PH DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_4_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_5 DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_5_PH DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_5_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_6 DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_6_PH DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_IDX_6_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 0) \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 1) \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 2) \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 3) \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 4) \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 5) \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 6)
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 6)
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 6, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_0, 6, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_LEN 7
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_names, 0)
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_names, 0)
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_ethernet_40028000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_phy_connection_type "rmii"
#define DT_N_S_soc_S_ethernet_40028000_P_phy_connection_type_STRING_UNQUOTED rmii
#define DT_N_S_soc_S_ethernet_40028000_P_phy_connection_type_STRING_TOKEN rmii
#define DT_N_S_soc_S_ethernet_40028000_P_phy_connection_type_STRING_UPPER_TOKEN RMII
#define DT_N_S_soc_S_ethernet_40028000_P_phy_connection_type_IDX_0 "rmii"
#define DT_N_S_soc_S_ethernet_40028000_P_phy_connection_type_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_phy_connection_type_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_ethernet_40028000_P_phy_connection_type_IDX_0_ENUM_VAL_rmii_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_phy_connection_type_ENUM_VAL_rmii_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_phy_connection_type_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000, phy_connection_type, 0)
#define DT_N_S_soc_S_ethernet_40028000_P_phy_connection_type_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, phy_connection_type, 0)
#define DT_N_S_soc_S_ethernet_40028000_P_phy_connection_type_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000, phy_connection_type, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_P_phy_connection_type_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000, phy_connection_type, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_P_phy_connection_type_LEN 1
#define DT_N_S_soc_S_ethernet_40028000_P_phy_connection_type_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_phy_handle DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0
#define DT_N_S_soc_S_ethernet_40028000_P_phy_handle_IDX_0 DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0
#define DT_N_S_soc_S_ethernet_40028000_P_phy_handle_IDX_0_PH DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0
#define DT_N_S_soc_S_ethernet_40028000_P_phy_handle_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_phy_handle_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000, phy_handle, 0)
#define DT_N_S_soc_S_ethernet_40028000_P_phy_handle_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, phy_handle, 0)
#define DT_N_S_soc_S_ethernet_40028000_P_phy_handle_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000, phy_handle, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_P_phy_handle_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000, phy_handle, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_P_phy_handle_LEN 1
#define DT_N_S_soc_S_ethernet_40028000_P_phy_handle_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_zephyr_random_mac_address 0
#define DT_N_S_soc_S_ethernet_40028000_P_zephyr_random_mac_address_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_status "okay"
#define DT_N_S_soc_S_ethernet_40028000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_ethernet_40028000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_ethernet_40028000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_ethernet_40028000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_ethernet_40028000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_ethernet_40028000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000, status, 0)
#define DT_N_S_soc_S_ethernet_40028000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, status, 0)
#define DT_N_S_soc_S_ethernet_40028000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_P_status_LEN 1
#define DT_N_S_soc_S_ethernet_40028000_P_status_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_compatible {"st,stm32-ethernet"}
#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_0 "st,stm32-ethernet"
#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-ethernet
#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_0_STRING_TOKEN st_stm32_ethernet
#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_ETHERNET
#define DT_N_S_soc_S_ethernet_40028000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000, compatible, 0)
#define DT_N_S_soc_S_ethernet_40028000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, compatible, 0)
#define DT_N_S_soc_S_ethernet_40028000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_P_compatible_LEN 1
#define DT_N_S_soc_S_ethernet_40028000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_dma_coherent 0
#define DT_N_S_soc_S_ethernet_40028000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_ethernet_40028000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_wakeup_source 0
#define DT_N_S_soc_S_ethernet_40028000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_ethernet_40028000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/eth_mdc_pc1
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_PATH "/soc/pin-controller@40020000/eth_mdc_pc1"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FULL_NAME "eth_mdc_pc1"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FULL_NAME_UNQUOTED eth_mdc_pc1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FULL_NAME_TOKEN eth_mdc_pc1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FULL_NAME_UPPER_TOKEN ETH_MDC_PC1

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_CHILD_IDX 17

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FOREACH_NODELABEL(fn) fn(eth_mdc_pc1)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FOREACH_NODELABEL_VARGS(fn, ...) fn(eth_mdc_pc1, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_HASH i9Yusk2MYt6mQkagPSytTdxD6sn4S3UBlgXYT5dvdUc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_ORD 111
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_ORD_STR_SORTABLE 00111

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_SUPPORTS_ORDS \
	113, /* /soc/ethernet@40028000/mdio */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_IDX_0_C_TOKEN eth_mdc_pc1

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_EXISTS 1
#define DT_N_NODELABEL_eth_mdc_pc1 DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_pinmux 1067
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/eth_mdio_pa2
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_PATH "/soc/pin-controller@40020000/eth_mdio_pa2"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FULL_NAME "eth_mdio_pa2"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FULL_NAME_UNQUOTED eth_mdio_pa2
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FULL_NAME_TOKEN eth_mdio_pa2
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FULL_NAME_UPPER_TOKEN ETH_MDIO_PA2

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_CHILD_IDX 14

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FOREACH_NODELABEL(fn) fn(eth_mdio_pa2)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FOREACH_NODELABEL_VARGS(fn, ...) fn(eth_mdio_pa2, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_HASH CT2YhUXA8FJVBIsRGtNu4dM3Tb7JNZl5vimIgkBDt5A

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_ORD 112
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_ORD_STR_SORTABLE 00112

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_SUPPORTS_ORDS \
	113, /* /soc/ethernet@40028000/mdio */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_IDX_0_C_TOKEN eth_mdio_pa2

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_EXISTS 1
#define DT_N_NODELABEL_eth_mdio_pa2 DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_pinmux 75
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/ethernet@40028000/mdio
 *
 * Node identifier: DT_N_S_soc_S_ethernet_40028000_S_mdio
 *
 * Binding (compatible = st,stm32-mdio):
 *   $ZEPHYR_BASE\dts\bindings\ethernet\mdio\st,stm32-mdio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_PATH "/soc/ethernet@40028000/mdio"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FULL_NAME "mdio"
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FULL_NAME_UNQUOTED mdio
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FULL_NAME_TOKEN mdio
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FULL_NAME_UPPER_TOKEN MDIO

/* Node parent (/soc/ethernet@40028000) identifier: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_PARENT DT_N_S_soc_S_ethernet_40028000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_NODELABEL_NUM 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FOREACH_NODELABEL(fn) fn(mdio)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FOREACH_NODELABEL_VARGS(fn, ...) fn(mdio, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_ethernet_40028000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_CHILD_NUM 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_CHILD_UNIT_ADDR_INT_0 DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_HASH 0taHKBrwQoii9rVChKS5oAHGd2QEKtUmsV_gJwnM__M

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_ORD 113
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_ORD_STR_SORTABLE 00113

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_REQUIRES_ORDS \
	110, /* /soc/ethernet@40028000 */ \
	111, /* /soc/pin-controller@40020000/eth_mdc_pc1 */ \
	112, /* /soc/pin-controller@40020000/eth_mdio_pa2 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_SUPPORTS_ORDS \
	114, /* /soc/ethernet@40028000/mdio/ethernet-phy@0 */
#define DT_N_NODELABEL_DT_N_S_soc_S_ethernet_40028000_S_mdio_IDX_0_C_TOKEN mdio

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_EXISTS 1
#define DT_N_INST_0_st_stm32_mdio   DT_N_S_soc_S_ethernet_40028000_S_mdio
#define DT_N_INST_0_snps_dwmac_mdio DT_N_S_soc_S_ethernet_40028000_S_mdio
#define DT_N_NODELABEL_mdio         DT_N_S_soc_S_ethernet_40028000_S_mdio

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_REG_NUM 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FOREACH_REG(fn) 
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_RANGES_NUM 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_IRQ_NUM 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_IRQ_LEVEL 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_COMPAT_MATCHES_st_stm32_mdio 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_COMPAT_MODEL_IDX_0 "stm32-mdio"
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_COMPAT_MATCHES_snps_dwmac_mdio 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_COMPAT_VENDOR_IDX_1 "Synopsys, Inc."
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_COMPAT_MODEL_IDX_1 "dwmac-mdio"
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_PINCTRL_NUM 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1

/* Generic property macros: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_0_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, pinctrl_0, 0) \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, pinctrl_0, 1)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, pinctrl_0, 1)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, pinctrl_0, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, pinctrl_0, 1, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, pinctrl_0, 1, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_0_LEN 2
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, pinctrl_names, 0)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, pinctrl_names, 0)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_suppress_preamble 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_suppress_preamble_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_clock_frequency 2500000
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status "okay"
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, status, 0)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, status, 0)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_LEN 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible {"st,stm32-mdio", "snps,dwmac-mdio"}
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_IDX_0 "st,stm32-mdio"
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-mdio
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_IDX_0_STRING_TOKEN st_stm32_mdio
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_MDIO
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_IDX_1 "snps,dwmac-mdio"
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_IDX_1_STRING_UNQUOTED snps,dwmac-mdio
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_IDX_1_STRING_TOKEN snps_dwmac_mdio
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_IDX_1_STRING_UPPER_TOKEN SNPS_DWMAC_MDIO
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, compatible, 0) \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, compatible, 1)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, compatible, 1)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_LEN 2
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_dma_coherent 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_wakeup_source 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/ethernet@40028000/mdio/ethernet-phy@0
 *
 * Node identifier: DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0
 *
 * Binding (compatible = ethernet-phy):
 *   $ZEPHYR_BASE\dts\bindings\ethernet\phy\ethernet-phy.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_PATH "/soc/ethernet@40028000/mdio/ethernet-phy@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FULL_NAME "ethernet-phy@0"
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FULL_NAME_UNQUOTED ethernet-phy@0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FULL_NAME_TOKEN ethernet_phy_0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FULL_NAME_UPPER_TOKEN ETHERNET_PHY_0

/* Node parent (/soc/ethernet@40028000/mdio) identifier: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_PARENT DT_N_S_soc_S_ethernet_40028000_S_mdio

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FOREACH_NODELABEL(fn) fn(eth_phy)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(eth_phy, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio) fn(DT_N_S_soc_S_ethernet_40028000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_CHILD_NUM 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_HASH 5Hzt_4TkJtuRZNyUToQKcQuH82OwS_KjUpEwdt95biY

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_ORD 114
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_ORD_STR_SORTABLE 00114

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_REQUIRES_ORDS \
	113, /* /soc/ethernet@40028000/mdio */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_IDX_0_C_TOKEN eth_phy

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_EXISTS 1
#define DT_N_INST_0_ethernet_phy DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0
#define DT_N_NODELABEL_eth_phy   DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0

/* Bus info (controller: '/soc/ethernet@40028000/mdio', type: '['mdio']') */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_BUS_mdio 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_BUS DT_N_S_soc_S_ethernet_40028000_S_mdio

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_REG_NUM 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FOREACH_REG(fn) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, 0)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, 0)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_RANGES_NUM 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_IRQ_NUM 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_COMPAT_MATCHES_ethernet_phy 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_no_reset 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_no_reset_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds {"10BASE Half-Duplex", "10BASE Full-Duplex", "100BASE Half-Duplex", "100BASE Full-Duplex", "1000BASE Half-Duplex", "1000BASE Full-Duplex"}
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_1_ENUM_IDX 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_2_ENUM_IDX 2
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_3_ENUM_IDX 3
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_4_ENUM_IDX 4
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_5_ENUM_IDX 5
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_0_ENUM_VAL_10base_half_duplex_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_ENUM_VAL_10base_half_duplex_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_1_ENUM_VAL_10base_full_duplex_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_ENUM_VAL_10base_full_duplex_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_2_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_2_ENUM_VAL_100base_half_duplex_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_ENUM_VAL_100base_half_duplex_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_3_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_3_ENUM_VAL_100base_full_duplex_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_ENUM_VAL_100base_full_duplex_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_4_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_4_ENUM_VAL_1000base_half_duplex_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_ENUM_VAL_1000base_half_duplex_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_5_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_5_ENUM_VAL_1000base_full_duplex_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_ENUM_VAL_1000base_full_duplex_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_0 "10BASE Half-Duplex"
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_0_STRING_UNQUOTED 10BASE Half-Duplex
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_0_STRING_TOKEN 10BASE_Half_Duplex
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_0_STRING_UPPER_TOKEN 10BASE_HALF_DUPLEX
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_1 "10BASE Full-Duplex"
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_1_STRING_UNQUOTED 10BASE Full-Duplex
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_1_STRING_TOKEN 10BASE_Full_Duplex
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_1_STRING_UPPER_TOKEN 10BASE_FULL_DUPLEX
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_2 "100BASE Half-Duplex"
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_2_STRING_UNQUOTED 100BASE Half-Duplex
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_2_STRING_TOKEN 100BASE_Half_Duplex
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_2_STRING_UPPER_TOKEN 100BASE_HALF_DUPLEX
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_3 "100BASE Full-Duplex"
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_3_STRING_UNQUOTED 100BASE Full-Duplex
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_3_STRING_TOKEN 100BASE_Full_Duplex
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_3_STRING_UPPER_TOKEN 100BASE_FULL_DUPLEX
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_4 "1000BASE Half-Duplex"
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_4_STRING_UNQUOTED 1000BASE Half-Duplex
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_4_STRING_TOKEN 1000BASE_Half_Duplex
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_4_STRING_UPPER_TOKEN 1000BASE_HALF_DUPLEX
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_5 "1000BASE Full-Duplex"
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_5_STRING_UNQUOTED 1000BASE Full-Duplex
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_5_STRING_TOKEN 1000BASE_Full_Duplex
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_IDX_5_STRING_UPPER_TOKEN 1000BASE_FULL_DUPLEX
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 0) \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 1) \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 2) \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 3) \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 4) \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 5)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 5)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 5, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, default_speeds, 5, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_LEN 6
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_default_speeds_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_reg {0 /* 0x0 */}
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_reg_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_compatible {"ethernet-phy"}
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_compatible_IDX_0 "ethernet-phy"
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_compatible_IDX_0_STRING_UNQUOTED ethernet-phy
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_compatible_IDX_0_STRING_TOKEN ethernet_phy
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_compatible_IDX_0_STRING_UPPER_TOKEN ETHERNET_PHY
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, compatible, 0)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, compatible, 0)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_compatible_LEN 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_dma_coherent 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_wakeup_source 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40023c00/flash@1fff7800
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800
 *
 * Binding (compatible = st,stm32-nvm-otp):
 *   $ZEPHYR_BASE\dts\bindings\otp\st,stm32-nvm-otp.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_PATH "/soc/flash-controller@40023c00/flash@1fff7800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FULL_NAME "flash@1fff7800"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FULL_NAME_UNQUOTED flash@1fff7800
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FULL_NAME_TOKEN flash_1fff7800
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FULL_NAME_UPPER_TOKEN FLASH_1FFF7800

/* Node parent (/soc/flash-controller@40023c00) identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_PARENT DT_N_S_soc_S_flash_controller_40023c00

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FOREACH_NODELABEL(fn) fn(st_nvm_user_otp)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FOREACH_NODELABEL_VARGS(fn, ...) fn(st_nvm_user_otp, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40023c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_HASH 4D5g4kKKhG8yitko50YuVfgL1e8U_q4R33bgsUZPCIw

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_ORD 115
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_ORD_STR_SORTABLE 00115

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_REQUIRES_ORDS \
	13, /* /soc/flash-controller@40023c00 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_IDX_0_C_TOKEN st_nvm_user_otp

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_EXISTS 1
#define DT_N_INST_1_st_stm32_nvm_otp   DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800
#define DT_N_NODELABEL_st_nvm_user_otp DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_REG_IDX_0_VAL_ADDRESS 536836096 /* 0x1fff7800 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_REG_IDX_0_VAL_SIZE 512 /* 0x200 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_COMPAT_MATCHES_st_stm32_nvm_otp 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_COMPAT_MODEL_IDX_0 "stm32-nvm-otp"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_reg {536836096 /* 0x1fff7800 */, 512 /* 0x200 */}
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_reg_IDX_0 536836096
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_reg_IDX_1 512
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_status "disabled"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800, status, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800, status, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_status_LEN 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_status_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_compatible {"st,stm32-nvm-otp"}
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_compatible_IDX_0 "st,stm32-nvm-otp"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-nvm-otp
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_compatible_IDX_0_STRING_TOKEN st_stm32_nvm_otp
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_NVM_OTP
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_compatible_LEN 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_dma_coherent 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40023c00/flash@8000000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000
 *
 * Binding (compatible = st,stm32f4-nv-flash):
 *   $ZEPHYR_BASE\dts\bindings\mtd\st,stm32f4-nv-flash.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_PATH "/soc/flash-controller@40023c00/flash@8000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FULL_NAME "flash@8000000"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FULL_NAME_UNQUOTED flash@8000000
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FULL_NAME_TOKEN flash_8000000
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FULL_NAME_UPPER_TOKEN FLASH_8000000

/* Node parent (/soc/flash-controller@40023c00) identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_PARENT DT_N_S_soc_S_flash_controller_40023c00

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FOREACH_NODELABEL(fn) fn(flash0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(flash0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40023c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_CHILD_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_HASH Hqu_ltbL9zidk6fJl_aN6Fwh6_B2dpM53Mz0vM0WeQM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_ORD 116
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_ORD_STR_SORTABLE 00116

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_REQUIRES_ORDS \
	13, /* /soc/flash-controller@40023c00 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_SUPPORTS_ORDS \
	117, /* /soc/flash-controller@40023c00/flash@8000000/partitions */
#define DT_N_NODELABEL_DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_IDX_0_C_TOKEN flash0

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_EXISTS 1
#define DT_N_INST_0_st_stm32f4_nv_flash DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000
#define DT_N_INST_0_st_stm32_nv_flash   DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000
#define DT_N_INST_0_soc_nv_flash        DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000
#define DT_N_NODELABEL_flash0           DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_REG_IDX_0_VAL_ADDRESS 134217728 /* 0x8000000 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_REG_IDX_0_VAL_SIZE 2097152 /* 0x200000 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_RANGES_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_RANGES_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_RANGES_IDX_0_VAL_CHILD_BUS_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_RANGES_IDX_0_VAL_PARENT_BUS_ADDRESS 134217728 /* 0x8000000 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_RANGES_IDX_0_VAL_LENGTH 2097152 /* 0x200000 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_FOREACH_RANGE(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_COMPAT_MATCHES_st_stm32f4_nv_flash 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_COMPAT_MODEL_IDX_0 "stm32f4-nv-flash"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_COMPAT_MATCHES_st_stm32_nv_flash 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_COMPAT_MODEL_IDX_1 "stm32-nv-flash"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_COMPAT_MATCHES_soc_nv_flash 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_write_block_size 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_write_block_size_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_write_block_size_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_write_block_size_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_write_block_size_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_write_block_size_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_max_erase_time 4000
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_max_erase_time_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible {"st,stm32f4-nv-flash", "st,stm32-nv-flash", "soc-nv-flash"}
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_IDX_0 "st,stm32f4-nv-flash"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32f4-nv-flash
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_IDX_0_STRING_TOKEN st_stm32f4_nv_flash
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32F4_NV_FLASH
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_IDX_1 "st,stm32-nv-flash"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-nv-flash
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_IDX_1_STRING_TOKEN st_stm32_nv_flash
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_NV_FLASH
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_IDX_2_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_IDX_2 "soc-nv-flash"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_IDX_2_STRING_UNQUOTED soc-nv-flash
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_IDX_2_STRING_TOKEN soc_nv_flash
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_IDX_2_STRING_UPPER_TOKEN SOC_NV_FLASH
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, compatible, 0) \
	fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, compatible, 1) \
	fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, compatible, 2)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, compatible, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, compatible, 2)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, compatible, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, compatible, 2, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, compatible, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, compatible, 2, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_LEN 3
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_reg {134217728 /* 0x8000000 */, 2097152 /* 0x200000 */}
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_reg_IDX_0 134217728
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_reg_IDX_1 2097152
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_dma_coherent 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40023c00/flash@8000000/partitions
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_PATH "/soc/flash-controller@40023c00/flash@8000000/partitions"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FULL_NAME "partitions"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FULL_NAME_UNQUOTED partitions
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FULL_NAME_TOKEN partitions
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FULL_NAME_UPPER_TOKEN PARTITIONS

/* Node parent (/soc/flash-controller@40023c00/flash@8000000) identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_PARENT DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_NODELABEL_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_40023c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_CHILD_NUM 4
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_CHILD_NUM_STATUS_OKAY 4
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_CHILD_UNIT_ADDR_INT_134217728 DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_CHILD_UNIT_ADDR_INT_134348800 DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_CHILD_UNIT_ADDR_INT_134610944 DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_CHILD_UNIT_ADDR_INT_134873088 DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_HASH nFV_qhzTb10erZBcGnuv7B_xf_qlB_YCwkEezeJCRxQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_ORD 117
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_ORD_STR_SORTABLE 00117

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_REQUIRES_ORDS \
	116, /* /soc/flash-controller@40023c00/flash@8000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_SUPPORTS_ORDS \
	118, /* /soc/flash-controller@40023c00/flash@8000000/partitions/partition@0 */ \
	119, /* /soc/flash-controller@40023c00/flash@8000000/partitions/partition@20000 */ \
	120, /* /soc/flash-controller@40023c00/flash@8000000/partitions/partition@60000 */ \
	121, /* /soc/flash-controller@40023c00/flash@8000000/partitions/partition@a0000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_REG_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FOREACH_REG(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_P_ranges_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40023c00/flash@8000000/partitions/partition@0
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0
 *
 * Binding (compatible = zephyr,mapped-partition):
 *   $ZEPHYR_BASE\dts\bindings\mtd\zephyr,mapped-partition.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_PATH "/soc/flash-controller@40023c00/flash@8000000/partitions/partition@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FULL_NAME "partition@0"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FULL_NAME_UNQUOTED partition@0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FULL_NAME_TOKEN partition_0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FULL_NAME_UPPER_TOKEN PARTITION_0

/* Node parent (/soc/flash-controller@40023c00/flash@8000000/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_PARENT DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FOREACH_NODELABEL(fn) fn(boot_partition)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(boot_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_40023c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_HASH T_kBX_kOOrT7fnSBWp9xGQHeSHcu2rd3wJReiS52apc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_ORD 118
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_ORD_STR_SORTABLE 00118

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_REQUIRES_ORDS \
	117, /* /soc/flash-controller@40023c00/flash@8000000/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_IDX_0_C_TOKEN boot_partition

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_EXISTS 1
#define DT_N_INST_0_zephyr_mapped_partition DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0
#define DT_N_NODELABEL_boot_partition       DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 134217728 /* 0x8000000 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 32768 /* 0x8000 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_COMPAT_MATCHES_zephyr_mapped_partition 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_COMPAT_MODEL_IDX_0 "mapped-partition"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_PARTITION_ID 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_label "mcuboot"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_label_STRING_UNQUOTED mcuboot
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_label_STRING_TOKEN mcuboot
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_label_STRING_UPPER_TOKEN MCUBOOT
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_label_IDX_0 "mcuboot"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, label, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, label, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_read_only 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_reg {0 /* 0x0 */, 32768 /* 0x8000 */}
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_1 32768
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_compatible {"zephyr,mapped-partition"}
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_compatible_IDX_0 "zephyr,mapped-partition"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_compatible_IDX_0_STRING_UNQUOTED zephyr,mapped-partition
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_compatible_IDX_0_STRING_TOKEN zephyr_mapped_partition
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MAPPED_PARTITION
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_compatible_LEN 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_dma_coherent 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40023c00/flash@8000000/partitions/partition@20000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000
 *
 * Binding (compatible = zephyr,mapped-partition):
 *   $ZEPHYR_BASE\dts\bindings\mtd\zephyr,mapped-partition.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_PATH "/soc/flash-controller@40023c00/flash@8000000/partitions/partition@20000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FULL_NAME "partition@20000"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FULL_NAME_UNQUOTED partition@20000
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FULL_NAME_TOKEN partition_20000
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FULL_NAME_UPPER_TOKEN PARTITION_20000

/* Node parent (/soc/flash-controller@40023c00/flash@8000000/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_PARENT DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FOREACH_NODELABEL(fn) fn(slot0_partition)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot0_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_40023c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_HASH xv5IRu6xjj5bOpYpgvH3ChDsDf8fWWVveZ4aRvl3ZVU

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_ORD 119
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_ORD_STR_SORTABLE 00119

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_REQUIRES_ORDS \
	117, /* /soc/flash-controller@40023c00/flash@8000000/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_IDX_0_C_TOKEN slot0_partition

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_EXISTS 1
#define DT_N_INST_1_zephyr_mapped_partition DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000
#define DT_N_NODELABEL_slot0_partition      DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_REG_IDX_0_VAL_ADDRESS 134348800 /* 0x8020000 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_COMPAT_MATCHES_zephyr_mapped_partition 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_COMPAT_MODEL_IDX_0 "mapped-partition"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_PARTITION_ID 1

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_label "image-0"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_label_STRING_UNQUOTED image-0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_label_STRING_TOKEN image_0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_label_STRING_UPPER_TOKEN IMAGE_0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_label_IDX_0 "image-0"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, label, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, label, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_read_only 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_reg {131072 /* 0x20000 */, 262144 /* 0x40000 */}
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_reg_IDX_0 131072
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_reg_IDX_1 262144
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_compatible {"zephyr,mapped-partition"}
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_compatible_IDX_0 "zephyr,mapped-partition"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,mapped-partition
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_compatible_IDX_0_STRING_TOKEN zephyr_mapped_partition
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MAPPED_PARTITION
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_compatible_LEN 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_dma_coherent 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40023c00/flash@8000000/partitions/partition@60000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000
 *
 * Binding (compatible = zephyr,mapped-partition):
 *   $ZEPHYR_BASE\dts\bindings\mtd\zephyr,mapped-partition.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_PATH "/soc/flash-controller@40023c00/flash@8000000/partitions/partition@60000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FULL_NAME "partition@60000"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FULL_NAME_UNQUOTED partition@60000
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FULL_NAME_TOKEN partition_60000
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FULL_NAME_UPPER_TOKEN PARTITION_60000

/* Node parent (/soc/flash-controller@40023c00/flash@8000000/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_PARENT DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FOREACH_NODELABEL(fn) fn(slot1_partition)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot1_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_40023c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_HASH JydPAAgpVdSCqDJPyywcRF4bAtb5T8H3jcM3xvG9sfk

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_ORD 120
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_ORD_STR_SORTABLE 00120

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_REQUIRES_ORDS \
	117, /* /soc/flash-controller@40023c00/flash@8000000/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_IDX_0_C_TOKEN slot1_partition

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_EXISTS 1
#define DT_N_INST_2_zephyr_mapped_partition DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000
#define DT_N_NODELABEL_slot1_partition      DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_REG_IDX_0_VAL_ADDRESS 134610944 /* 0x8060000 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_COMPAT_MATCHES_zephyr_mapped_partition 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_COMPAT_MODEL_IDX_0 "mapped-partition"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_PARTITION_ID 2

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_label "image-1"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_label_STRING_UNQUOTED image-1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_label_STRING_TOKEN image_1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_label_STRING_UPPER_TOKEN IMAGE_1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_label_IDX_0 "image-1"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, label, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, label, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_read_only 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_reg {393216 /* 0x60000 */, 262144 /* 0x40000 */}
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_reg_IDX_0 393216
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_reg_IDX_1 262144
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_compatible {"zephyr,mapped-partition"}
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_compatible_IDX_0 "zephyr,mapped-partition"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,mapped-partition
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_compatible_IDX_0_STRING_TOKEN zephyr_mapped_partition
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MAPPED_PARTITION
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_compatible_LEN 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_dma_coherent 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40023c00/flash@8000000/partitions/partition@a0000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000
 *
 * Binding (compatible = zephyr,mapped-partition):
 *   $ZEPHYR_BASE\dts\bindings\mtd\zephyr,mapped-partition.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_PATH "/soc/flash-controller@40023c00/flash@8000000/partitions/partition@a0000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FULL_NAME "partition@a0000"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FULL_NAME_UNQUOTED partition@a0000
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FULL_NAME_TOKEN partition_a0000
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FULL_NAME_UPPER_TOKEN PARTITION_A0000

/* Node parent (/soc/flash-controller@40023c00/flash@8000000/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_PARENT DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FOREACH_NODELABEL(fn) fn(scratch_partition)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FOREACH_NODELABEL_VARGS(fn, ...) fn(scratch_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_40023c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_HASH TlJ29F68dOu20mBQ_avRAUaH0_TwFlxqBOAe5x2nVyo

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_ORD 121
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_ORD_STR_SORTABLE 00121

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_REQUIRES_ORDS \
	117, /* /soc/flash-controller@40023c00/flash@8000000/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_IDX_0_C_TOKEN scratch_partition

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_EXISTS 1
#define DT_N_INST_3_zephyr_mapped_partition DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000
#define DT_N_NODELABEL_scratch_partition    DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_REG_IDX_0_VAL_ADDRESS 134873088 /* 0x80a0000 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_REG_IDX_0_VAL_SIZE 131072 /* 0x20000 */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_COMPAT_MATCHES_zephyr_mapped_partition 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_COMPAT_MODEL_IDX_0 "mapped-partition"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_PARTITION_ID 3

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_label "image-scratch"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_label_STRING_UNQUOTED image-scratch
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_label_STRING_TOKEN image_scratch
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_label_STRING_UPPER_TOKEN IMAGE_SCRATCH
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_label_IDX_0 "image-scratch"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, label, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, label, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_read_only 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_reg {655360 /* 0xa0000 */, 131072 /* 0x20000 */}
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_reg_IDX_0 655360
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_reg_IDX_1 131072
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_compatible {"zephyr,mapped-partition"}
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_compatible_IDX_0 "zephyr,mapped-partition"
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,mapped-partition
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_compatible_IDX_0_STRING_TOKEN zephyr_mapped_partition
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MAPPED_PARTITION
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_compatible_LEN 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_dma_coherent 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/memory-controller@a0000000
 *
 * Node identifier: DT_N_S_soc_S_memory_controller_a0000000
 *
 * Binding (compatible = st,stm32-fmc):
 *   $ZEPHYR_BASE\dts\bindings\memory-controllers\st,stm32-fmc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_memory_controller_a0000000_PATH "/soc/memory-controller@a0000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_memory_controller_a0000000_FULL_NAME "memory-controller@a0000000"
#define DT_N_S_soc_S_memory_controller_a0000000_FULL_NAME_UNQUOTED memory-controller@a0000000
#define DT_N_S_soc_S_memory_controller_a0000000_FULL_NAME_TOKEN memory_controller_a0000000
#define DT_N_S_soc_S_memory_controller_a0000000_FULL_NAME_UPPER_TOKEN MEMORY_CONTROLLER_A0000000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_controller_a0000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_memory_controller_a0000000_CHILD_IDX 56

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_memory_controller_a0000000_NODELABEL_NUM 1
#define DT_N_S_soc_S_memory_controller_a0000000_FOREACH_NODELABEL(fn) fn(fmc)
#define DT_N_S_soc_S_memory_controller_a0000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(fmc, __VA_ARGS__)
#define DT_N_S_soc_S_memory_controller_a0000000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_memory_controller_a0000000_CHILD_NUM 1
#define DT_N_S_soc_S_memory_controller_a0000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_memory_controller_a0000000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_memory_controller_a0000000_S_sdram)
#define DT_N_S_soc_S_memory_controller_a0000000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_memory_controller_a0000000_S_sdram)
#define DT_N_S_soc_S_memory_controller_a0000000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_controller_a0000000_S_sdram, __VA_ARGS__)
#define DT_N_S_soc_S_memory_controller_a0000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_a0000000_S_sdram, __VA_ARGS__)
#define DT_N_S_soc_S_memory_controller_a0000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_memory_controller_a0000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_controller_a0000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_controller_a0000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_memory_controller_a0000000_HASH lnthcLeGWhgFF_OA2kAgc2I_JOgZOx3sYRSW2VyZp74

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_controller_a0000000_ORD 122
#define DT_N_S_soc_S_memory_controller_a0000000_ORD_STR_SORTABLE 00122

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_controller_a0000000_REQUIRES_ORDS \
	4, /* /soc */ \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_controller_a0000000_SUPPORTS_ORDS \
	123, /* /soc/memory-controller@a0000000/sdram */
#define DT_N_NODELABEL_DT_N_S_soc_S_memory_controller_a0000000_IDX_0_C_TOKEN fmc

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_controller_a0000000_EXISTS 1
#define DT_N_INST_0_st_stm32_fmc DT_N_S_soc_S_memory_controller_a0000000
#define DT_N_NODELABEL_fmc       DT_N_S_soc_S_memory_controller_a0000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_memory_controller_a0000000_REG_NUM 1
#define DT_N_S_soc_S_memory_controller_a0000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_REG_IDX_0_VAL_ADDRESS 2684354560 /* 0xa0000000 */
#define DT_N_S_soc_S_memory_controller_a0000000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_memory_controller_a0000000_FOREACH_REG(fn) fn(DT_N_S_soc_S_memory_controller_a0000000, 0)
#define DT_N_S_soc_S_memory_controller_a0000000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_memory_controller_a0000000, 0)
#define DT_N_S_soc_S_memory_controller_a0000000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_controller_a0000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_controller_a0000000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_a0000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_controller_a0000000_RANGES_NUM 0
#define DT_N_S_soc_S_memory_controller_a0000000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_memory_controller_a0000000_IRQ_NUM 0
#define DT_N_S_soc_S_memory_controller_a0000000_IRQ_LEVEL 0
#define DT_N_S_soc_S_memory_controller_a0000000_COMPAT_MATCHES_st_stm32_fmc 1
#define DT_N_S_soc_S_memory_controller_a0000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_memory_controller_a0000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_COMPAT_MODEL_IDX_0 "stm32-fmc"
#define DT_N_S_soc_S_memory_controller_a0000000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_memory_controller_a0000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_memory_controller_a0000000_P_reg {2684354560 /* 0xa0000000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_memory_controller_a0000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_reg_IDX_0 2684354560
#define DT_N_S_soc_S_memory_controller_a0000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_memory_controller_a0000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_memory_controller_a0000000_P_clocks_IDX_0_VAL_bus 56
#define DT_N_S_soc_S_memory_controller_a0000000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_clocks_IDX_0_VAL_bits 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_memory_controller_a0000000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_memory_controller_a0000000, clocks, 0, bits)
#define DT_N_S_soc_S_memory_controller_a0000000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_memory_controller_a0000000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_memory_controller_a0000000, clocks, 0, bits)
#define DT_N_S_soc_S_memory_controller_a0000000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_memory_controller_a0000000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_controller_a0000000, clocks, 0)
#define DT_N_S_soc_S_memory_controller_a0000000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_controller_a0000000, clocks, 0)
#define DT_N_S_soc_S_memory_controller_a0000000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_controller_a0000000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_controller_a0000000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_a0000000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_controller_a0000000_P_clocks_LEN 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_status "disabled"
#define DT_N_S_soc_S_memory_controller_a0000000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_memory_controller_a0000000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_memory_controller_a0000000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_memory_controller_a0000000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_memory_controller_a0000000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_controller_a0000000, status, 0)
#define DT_N_S_soc_S_memory_controller_a0000000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_controller_a0000000, status, 0)
#define DT_N_S_soc_S_memory_controller_a0000000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_controller_a0000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_controller_a0000000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_a0000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_controller_a0000000_P_status_LEN 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_status_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_compatible {"st,stm32-fmc"}
#define DT_N_S_soc_S_memory_controller_a0000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_compatible_IDX_0 "st,stm32-fmc"
#define DT_N_S_soc_S_memory_controller_a0000000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-fmc
#define DT_N_S_soc_S_memory_controller_a0000000_P_compatible_IDX_0_STRING_TOKEN st_stm32_fmc
#define DT_N_S_soc_S_memory_controller_a0000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_FMC
#define DT_N_S_soc_S_memory_controller_a0000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_controller_a0000000, compatible, 0)
#define DT_N_S_soc_S_memory_controller_a0000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_controller_a0000000, compatible, 0)
#define DT_N_S_soc_S_memory_controller_a0000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_controller_a0000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_controller_a0000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_a0000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_controller_a0000000_P_compatible_LEN 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_dma_coherent 0
#define DT_N_S_soc_S_memory_controller_a0000000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_memory_controller_a0000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_wakeup_source 0
#define DT_N_S_soc_S_memory_controller_a0000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_memory_controller_a0000000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/memory-controller@a0000000/sdram
 *
 * Node identifier: DT_N_S_soc_S_memory_controller_a0000000_S_sdram
 *
 * Binding (compatible = st,stm32-fmc-sdram):
 *   $ZEPHYR_BASE\dts\bindings\memory-controllers\st,stm32-fmc-sdram.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_PATH "/soc/memory-controller@a0000000/sdram"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FULL_NAME "sdram"
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FULL_NAME_UNQUOTED sdram
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FULL_NAME_TOKEN sdram
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FULL_NAME_UPPER_TOKEN SDRAM

/* Node parent (/soc/memory-controller@a0000000) identifier: */
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_PARENT DT_N_S_soc_S_memory_controller_a0000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_NODELABEL_NUM 1
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FOREACH_NODELABEL(fn) fn(sdram)
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FOREACH_NODELABEL_VARGS(fn, ...) fn(sdram, __VA_ARGS__)
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_memory_controller_a0000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_CHILD_NUM 0
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_HASH RbLCdyS4_UgTGkUJFj0FhY8YBPfEb1s24NvoCz_xU3w

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_ORD 123
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_ORD_STR_SORTABLE 00123

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_REQUIRES_ORDS \
	122, /* /soc/memory-controller@a0000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_memory_controller_a0000000_S_sdram_IDX_0_C_TOKEN sdram

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_EXISTS 1
#define DT_N_INST_0_st_stm32_fmc_sdram DT_N_S_soc_S_memory_controller_a0000000_S_sdram
#define DT_N_NODELABEL_sdram           DT_N_S_soc_S_memory_controller_a0000000_S_sdram

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_REG_NUM 0
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FOREACH_REG(fn) 
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_RANGES_NUM 0
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_IRQ_NUM 0
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_IRQ_LEVEL 0
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_COMPAT_MATCHES_st_stm32_fmc_sdram 1
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_COMPAT_MODEL_IDX_0 "stm32-fmc-sdram"
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_power_up_delay 100
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_power_up_delay_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_num_auto_refresh 8
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_num_auto_refresh_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_status "disabled"
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_controller_a0000000_S_sdram, status, 0)
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_controller_a0000000_S_sdram, status, 0)
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_controller_a0000000_S_sdram, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_a0000000_S_sdram, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_status_LEN 1
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_status_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_compatible {"st,stm32-fmc-sdram"}
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_compatible_IDX_0 "st,stm32-fmc-sdram"
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-fmc-sdram
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_compatible_IDX_0_STRING_TOKEN st_stm32_fmc_sdram
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_FMC_SDRAM
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_controller_a0000000_S_sdram, compatible, 0)
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_controller_a0000000_S_sdram, compatible, 0)
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_controller_a0000000_S_sdram, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_a0000000_S_sdram, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_compatible_LEN 1
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_compatible_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_dma_coherent 0
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_wakeup_source 0
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_memory_controller_a0000000_S_sdram_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/gpio@40021000
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000
 *
 * Binding (compatible = st,stm32-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\st,stm32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_PATH "/soc/pin-controller@40020000/gpio@40021000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FULL_NAME "gpio@40021000"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FULL_NAME_UNQUOTED gpio@40021000
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FULL_NAME_TOKEN gpio_40021000
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FULL_NAME_UPPER_TOKEN GPIO_40021000

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FOREACH_NODELABEL(fn) fn(gpioe)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpioe, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_HASH y6ySB9SVNvgSAnRaYUJQf_xzLTzGM1jbpI6ixHqcE78

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_ORD 124
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_ORD_STR_SORTABLE 00124

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_REQUIRES_ORDS \
	9, /* /soc/rcc@40023800 */ \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_IDX_0_C_TOKEN gpioe

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_EXISTS 1
#define DT_N_INST_4_st_stm32_gpio DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000
#define DT_N_NODELABEL_gpioe      DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_REG_IDX_0_VAL_ADDRESS 1073876992 /* 0x40021000 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_COMPAT_MATCHES_st_stm32_gpio 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_COMPAT_MODEL_IDX_0 "stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_reg {1073876992 /* 0x40021000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_reg_IDX_0 1073876992
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_clocks_IDX_0_VAL_bus 48
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_clocks_IDX_0_VAL_bits 16
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_clocks_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_ngpios 16
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_gpio_controller 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_compatible {"st,stm32-gpio"}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_compatible_IDX_0 "st,stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/gpio@40021400
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400
 *
 * Binding (compatible = st,stm32-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\st,stm32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_PATH "/soc/pin-controller@40020000/gpio@40021400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FULL_NAME "gpio@40021400"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FULL_NAME_UNQUOTED gpio@40021400
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FULL_NAME_TOKEN gpio_40021400
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FULL_NAME_UPPER_TOKEN GPIO_40021400

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FOREACH_NODELABEL(fn) fn(gpiof)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpiof, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_HASH O_vGFqKtgqRF_snzB4gvxQC9WW_O_gOq77IxDmcuqkM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_ORD 125
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_ORD_STR_SORTABLE 00125

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_REQUIRES_ORDS \
	9, /* /soc/rcc@40023800 */ \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_IDX_0_C_TOKEN gpiof

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_EXISTS 1
#define DT_N_INST_5_st_stm32_gpio DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400
#define DT_N_NODELABEL_gpiof      DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_REG_IDX_0_VAL_ADDRESS 1073878016 /* 0x40021400 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_COMPAT_MATCHES_st_stm32_gpio 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_COMPAT_MODEL_IDX_0 "stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_reg {1073878016 /* 0x40021400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_reg_IDX_0 1073878016
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_clocks_IDX_0_VAL_bus 48
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_clocks_IDX_0_VAL_bits 32
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_clocks_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_ngpios 16
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_gpio_controller 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_compatible {"st,stm32-gpio"}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_compatible_IDX_0 "st,stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/gpio@40021800
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800
 *
 * Binding (compatible = st,stm32-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\st,stm32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_PATH "/soc/pin-controller@40020000/gpio@40021800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FULL_NAME "gpio@40021800"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FULL_NAME_UNQUOTED gpio@40021800
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FULL_NAME_TOKEN gpio_40021800
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FULL_NAME_UPPER_TOKEN GPIO_40021800

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_CHILD_IDX 6

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FOREACH_NODELABEL(fn) fn(gpiog)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpiog, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_HASH Cdgy_wuDO6anCVDzTkK3776vvDe1vHzGEbRvGTvxOq4

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_ORD 126
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_ORD_STR_SORTABLE 00126

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_REQUIRES_ORDS \
	9, /* /soc/rcc@40023800 */ \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_IDX_0_C_TOKEN gpiog

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_EXISTS 1
#define DT_N_INST_6_st_stm32_gpio DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800
#define DT_N_NODELABEL_gpiog      DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_REG_IDX_0_VAL_ADDRESS 1073879040 /* 0x40021800 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_COMPAT_MATCHES_st_stm32_gpio 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_COMPAT_MODEL_IDX_0 "stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_reg {1073879040 /* 0x40021800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_reg_IDX_0 1073879040
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_clocks_IDX_0_VAL_bus 48
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_clocks_IDX_0_VAL_bits 64
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_clocks_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_ngpios 16
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_gpio_controller 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_compatible {"st,stm32-gpio"}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_compatible_IDX_0 "st,stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/gpio@40021c00
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00
 *
 * Binding (compatible = st,stm32-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\st,stm32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_PATH "/soc/pin-controller@40020000/gpio@40021c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FULL_NAME "gpio@40021c00"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FULL_NAME_UNQUOTED gpio@40021c00
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FULL_NAME_TOKEN gpio_40021c00
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FULL_NAME_UPPER_TOKEN GPIO_40021C00

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_CHILD_IDX 7

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FOREACH_NODELABEL(fn) fn(gpioh)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpioh, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_HASH 7WT39Zb7KyOZNC2TXCBmlQILVbGwPtOYHUuclpmZvxE

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_ORD 127
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_ORD_STR_SORTABLE 00127

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_REQUIRES_ORDS \
	9, /* /soc/rcc@40023800 */ \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_IDX_0_C_TOKEN gpioh

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_EXISTS 1
#define DT_N_INST_7_st_stm32_gpio DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00
#define DT_N_NODELABEL_gpioh      DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_REG_IDX_0_VAL_ADDRESS 1073880064 /* 0x40021c00 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_COMPAT_MATCHES_st_stm32_gpio 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_COMPAT_MODEL_IDX_0 "stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_reg {1073880064 /* 0x40021c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_reg_IDX_0 1073880064
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_clocks_IDX_0_VAL_bus 48
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_clocks_IDX_0_VAL_bits 128
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_clocks_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_ngpios 16
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_gpio_controller 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_compatible {"st,stm32-gpio"}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_compatible_IDX_0 "st,stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/gpio@40022000
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000
 *
 * Binding (compatible = st,stm32-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\st,stm32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_PATH "/soc/pin-controller@40020000/gpio@40022000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FULL_NAME "gpio@40022000"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FULL_NAME_UNQUOTED gpio@40022000
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FULL_NAME_TOKEN gpio_40022000
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FULL_NAME_UPPER_TOKEN GPIO_40022000

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_CHILD_IDX 8

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FOREACH_NODELABEL(fn) fn(gpioi)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpioi, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_HASH 9HQlFNQ6HMaD0L_TUIGU_cZ2QMIIBaM9oJC_KOQX9NM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_ORD 128
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_ORD_STR_SORTABLE 00128

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_REQUIRES_ORDS \
	9, /* /soc/rcc@40023800 */ \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_IDX_0_C_TOKEN gpioi

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_EXISTS 1
#define DT_N_INST_8_st_stm32_gpio DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000
#define DT_N_NODELABEL_gpioi      DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_REG_IDX_0_VAL_ADDRESS 1073881088 /* 0x40022000 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_COMPAT_MATCHES_st_stm32_gpio 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_COMPAT_MODEL_IDX_0 "stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_reg {1073881088 /* 0x40022000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_reg_IDX_0 1073881088
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_clocks_IDX_0_VAL_bus 48
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_clocks_IDX_0_VAL_bits 256
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_clocks_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_ngpios 16
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_gpio_controller 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_compatible {"st,stm32-gpio"}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_compatible_IDX_0 "st,stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/gpio@40022400
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400
 *
 * Binding (compatible = st,stm32-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\st,stm32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_PATH "/soc/pin-controller@40020000/gpio@40022400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FULL_NAME "gpio@40022400"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FULL_NAME_UNQUOTED gpio@40022400
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FULL_NAME_TOKEN gpio_40022400
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FULL_NAME_UPPER_TOKEN GPIO_40022400

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_CHILD_IDX 9

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FOREACH_NODELABEL(fn) fn(gpioj)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpioj, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_HASH q9yTtJM_j2rbVEL9zpPFDcVtxZ2uVcplP8meghyp570

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_ORD 129
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_ORD_STR_SORTABLE 00129

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_REQUIRES_ORDS \
	9, /* /soc/rcc@40023800 */ \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_IDX_0_C_TOKEN gpioj

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_EXISTS 1
#define DT_N_INST_9_st_stm32_gpio DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400
#define DT_N_NODELABEL_gpioj      DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_REG_IDX_0_VAL_ADDRESS 1073882112 /* 0x40022400 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_COMPAT_MATCHES_st_stm32_gpio 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_COMPAT_MODEL_IDX_0 "stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_reg {1073882112 /* 0x40022400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_reg_IDX_0 1073882112
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_clocks_IDX_0_VAL_bus 48
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_clocks_IDX_0_VAL_bits 512
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_clocks_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_ngpios 16
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_gpio_controller 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_compatible {"st,stm32-gpio"}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_compatible_IDX_0 "st,stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/gpio@40022800
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800
 *
 * Binding (compatible = st,stm32-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\st,stm32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_PATH "/soc/pin-controller@40020000/gpio@40022800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FULL_NAME "gpio@40022800"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FULL_NAME_UNQUOTED gpio@40022800
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FULL_NAME_TOKEN gpio_40022800
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FULL_NAME_UPPER_TOKEN GPIO_40022800

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_CHILD_IDX 10

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FOREACH_NODELABEL(fn) fn(gpiok)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpiok, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_HASH XvZeizEM8PP7xtznV8y44oRLsfMCZi1WEXza2UTlAjc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_ORD 130
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_ORD_STR_SORTABLE 00130

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_REQUIRES_ORDS \
	9, /* /soc/rcc@40023800 */ \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_IDX_0_C_TOKEN gpiok

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_EXISTS 1
#define DT_N_INST_10_st_stm32_gpio DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800
#define DT_N_NODELABEL_gpiok       DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_REG_IDX_0_VAL_ADDRESS 1073883136 /* 0x40022800 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_COMPAT_MATCHES_st_stm32_gpio 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_COMPAT_MODEL_IDX_0 "stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_reg {1073883136 /* 0x40022800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_reg_IDX_0 1073883136
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_clocks_IDX_0_VAL_bus 48
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_clocks_IDX_0_VAL_bits 1024
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, clocks, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_clocks_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_ngpios 16
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_gpio_controller 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_compatible {"st,stm32-gpio"}
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_compatible_IDX_0 "st,stm32-gpio"
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, compatible, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/rtc@40002800
 *
 * Node identifier: DT_N_S_soc_S_rtc_40002800
 *
 * Binding (compatible = st,stm32-rtc):
 *   $ZEPHYR_BASE\dts\bindings\rtc\st,stm32-rtc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rtc_40002800_PATH "/soc/rtc@40002800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rtc_40002800_FULL_NAME "rtc@40002800"
#define DT_N_S_soc_S_rtc_40002800_FULL_NAME_UNQUOTED rtc@40002800
#define DT_N_S_soc_S_rtc_40002800_FULL_NAME_TOKEN rtc_40002800
#define DT_N_S_soc_S_rtc_40002800_FULL_NAME_UPPER_TOKEN RTC_40002800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_rtc_40002800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rtc_40002800_CHILD_IDX 24

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_rtc_40002800_NODELABEL_NUM 1
#define DT_N_S_soc_S_rtc_40002800_FOREACH_NODELABEL(fn) fn(rtc)
#define DT_N_S_soc_S_rtc_40002800_FOREACH_NODELABEL_VARGS(fn, ...) fn(rtc, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rtc_40002800_CHILD_NUM 1
#define DT_N_S_soc_S_rtc_40002800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_rtc_40002800_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_rtc_40002800_S_backup_regs)
#define DT_N_S_soc_S_rtc_40002800_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40002800_S_backup_regs)
#define DT_N_S_soc_S_rtc_40002800_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_40002800_S_backup_regs, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_40002800_S_backup_regs, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_rtc_40002800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_rtc_40002800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_rtc_40002800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_rtc_40002800_HASH gMDUpS7Ndbl4XKI6XlHTk7n7PIqWK98QhTUf_xffseI

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rtc_40002800_ORD 131
#define DT_N_S_soc_S_rtc_40002800_ORD_STR_SORTABLE 00131

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rtc_40002800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rtc_40002800_SUPPORTS_ORDS \
	132, /* /soc/rtc@40002800/backup_regs */
#define DT_N_NODELABEL_DT_N_S_soc_S_rtc_40002800_IDX_0_C_TOKEN rtc

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rtc_40002800_EXISTS 1
#define DT_N_ALIAS_rtc           DT_N_S_soc_S_rtc_40002800
#define DT_N_INST_0_st_stm32_rtc DT_N_S_soc_S_rtc_40002800
#define DT_N_NODELABEL_rtc       DT_N_S_soc_S_rtc_40002800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rtc_40002800_REG_NUM 1
#define DT_N_S_soc_S_rtc_40002800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_REG_IDX_0_VAL_ADDRESS 1073752064 /* 0x40002800 */
#define DT_N_S_soc_S_rtc_40002800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_rtc_40002800_FOREACH_REG(fn) fn(DT_N_S_soc_S_rtc_40002800, 0)
#define DT_N_S_soc_S_rtc_40002800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40002800, 0)
#define DT_N_S_soc_S_rtc_40002800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_40002800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_40002800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_RANGES_NUM 0
#define DT_N_S_soc_S_rtc_40002800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rtc_40002800_IRQ_NUM 1
#define DT_N_S_soc_S_rtc_40002800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_IRQ_IDX_0_VAL_irq 41
#define DT_N_S_soc_S_rtc_40002800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_rtc_40002800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_rtc_40002800_IRQ_LEVEL 1
#define DT_N_S_soc_S_rtc_40002800_COMPAT_MATCHES_st_stm32_rtc 1
#define DT_N_S_soc_S_rtc_40002800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_rtc_40002800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_COMPAT_MODEL_IDX_0 "stm32-rtc"
#define DT_N_S_soc_S_rtc_40002800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rtc_40002800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_rtc_40002800_P_reg {1073752064 /* 0x40002800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_rtc_40002800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_reg_IDX_0 1073752064
#define DT_N_S_soc_S_rtc_40002800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_rtc_40002800_P_reg_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_alarms_count 2
#define DT_N_S_soc_S_rtc_40002800_P_alarms_count_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_alrm_exti_line 17
#define DT_N_S_soc_S_rtc_40002800_P_alrm_exti_line_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_interrupts {41 /* 0x29 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_rtc_40002800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_interrupts_IDX_0 41
#define DT_N_S_soc_S_rtc_40002800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_rtc_40002800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_prescaler 32768
#define DT_N_S_soc_S_rtc_40002800_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_status "okay"
#define DT_N_S_soc_S_rtc_40002800_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_rtc_40002800_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_rtc_40002800_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_rtc_40002800_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_rtc_40002800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_rtc_40002800_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_40002800, status, 0)
#define DT_N_S_soc_S_rtc_40002800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40002800, status, 0)
#define DT_N_S_soc_S_rtc_40002800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_40002800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_40002800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_P_status_LEN 1
#define DT_N_S_soc_S_rtc_40002800_P_status_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_compatible {"st,stm32-rtc"}
#define DT_N_S_soc_S_rtc_40002800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_compatible_IDX_0 "st,stm32-rtc"
#define DT_N_S_soc_S_rtc_40002800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-rtc
#define DT_N_S_soc_S_rtc_40002800_P_compatible_IDX_0_STRING_TOKEN st_stm32_rtc
#define DT_N_S_soc_S_rtc_40002800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_RTC
#define DT_N_S_soc_S_rtc_40002800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_40002800, compatible, 0)
#define DT_N_S_soc_S_rtc_40002800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40002800, compatible, 0)
#define DT_N_S_soc_S_rtc_40002800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_40002800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_40002800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_P_compatible_LEN 1
#define DT_N_S_soc_S_rtc_40002800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_0_VAL_bits 268435456
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_rtc_40002800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_rtc_40002800, clocks, 0, bits)
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40002800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_rtc_40002800, clocks, 0, bits)
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_1_VAL_bus 3
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_1_VAL_bits 36175984
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_rtc_40002800, clocks, 1, bus) \
	fn(DT_N_S_soc_S_rtc_40002800, clocks, 1, bits)
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40002800, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_rtc_40002800, clocks, 1, bits)
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_rtc_40002800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_40002800, clocks, 0) \
	fn(DT_N_S_soc_S_rtc_40002800, clocks, 1)
#define DT_N_S_soc_S_rtc_40002800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40002800, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_rtc_40002800, clocks, 1)
#define DT_N_S_soc_S_rtc_40002800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_40002800, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_rtc_40002800, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_40002800, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_rtc_40002800, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_P_clocks_LEN 2
#define DT_N_S_soc_S_rtc_40002800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_dma_coherent 0
#define DT_N_S_soc_S_rtc_40002800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_rtc_40002800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_wakeup_source 0
#define DT_N_S_soc_S_rtc_40002800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_rtc_40002800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/rtc@40002800/backup_regs
 *
 * Node identifier: DT_N_S_soc_S_rtc_40002800_S_backup_regs
 *
 * Binding (compatible = st,stm32-bbram):
 *   $ZEPHYR_BASE\dts\bindings\memory-controllers\st,stm32-bbram.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_PATH "/soc/rtc@40002800/backup_regs"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FULL_NAME "backup_regs"
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FULL_NAME_UNQUOTED backup_regs
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FULL_NAME_TOKEN backup_regs
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FULL_NAME_UPPER_TOKEN BACKUP_REGS

/* Node parent (/soc/rtc@40002800) identifier: */
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_PARENT DT_N_S_soc_S_rtc_40002800

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_NODELABEL_NUM 1
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FOREACH_NODELABEL(fn) fn(bbram)
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FOREACH_NODELABEL_VARGS(fn, ...) fn(bbram, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_rtc_40002800) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_CHILD_NUM 0
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_HASH 87KLygauUkNGUe3q_y8ziT69orcsnQqP1AwsJG8Gz24

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_ORD 132
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_ORD_STR_SORTABLE 00132

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_REQUIRES_ORDS \
	131, /* /soc/rtc@40002800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_rtc_40002800_S_backup_regs_IDX_0_C_TOKEN bbram

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_EXISTS 1
#define DT_N_INST_0_st_stm32_bbram DT_N_S_soc_S_rtc_40002800_S_backup_regs
#define DT_N_NODELABEL_bbram       DT_N_S_soc_S_rtc_40002800_S_backup_regs

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_REG_NUM 0
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FOREACH_REG(fn) 
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_RANGES_NUM 0
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_IRQ_NUM 0
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_IRQ_LEVEL 0
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_COMPAT_MATCHES_st_stm32_bbram 1
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_COMPAT_MODEL_IDX_0 "stm32-bbram"
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_st_backup_regs 20
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_st_backup_regs_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_status "disabled"
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_40002800_S_backup_regs, status, 0)
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40002800_S_backup_regs, status, 0)
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_40002800_S_backup_regs, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_40002800_S_backup_regs, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_status_LEN 1
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_status_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_compatible {"st,stm32-bbram"}
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_compatible_IDX_0 "st,stm32-bbram"
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-bbram
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_compatible_IDX_0_STRING_TOKEN st_stm32_bbram
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_BBRAM
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_40002800_S_backup_regs, compatible, 0)
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40002800_S_backup_regs, compatible, 0)
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_40002800_S_backup_regs, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_40002800_S_backup_regs, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_compatible_LEN 1
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_compatible_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_dma_coherent 0
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_wakeup_source 0
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_rtc_40002800_S_backup_regs_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/dma@40026400
 *
 * Node identifier: DT_N_S_soc_S_dma_40026400
 *
 * Binding (compatible = st,stm32-dma-v1):
 *   $ZEPHYR_BASE\dts\bindings\dma\st,stm32-dma-v1.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_dma_40026400_PATH "/soc/dma@40026400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_dma_40026400_FULL_NAME "dma@40026400"
#define DT_N_S_soc_S_dma_40026400_FULL_NAME_UNQUOTED dma@40026400
#define DT_N_S_soc_S_dma_40026400_FULL_NAME_TOKEN dma_40026400
#define DT_N_S_soc_S_dma_40026400_FULL_NAME_UPPER_TOKEN DMA_40026400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_dma_40026400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_dma_40026400_CHILD_IDX 27

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_dma_40026400_NODELABEL_NUM 1
#define DT_N_S_soc_S_dma_40026400_FOREACH_NODELABEL(fn) fn(dma2)
#define DT_N_S_soc_S_dma_40026400_FOREACH_NODELABEL_VARGS(fn, ...) fn(dma2, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40026400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_dma_40026400_CHILD_NUM 0
#define DT_N_S_soc_S_dma_40026400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_dma_40026400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_dma_40026400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_dma_40026400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_dma_40026400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_dma_40026400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_dma_40026400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_dma_40026400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_dma_40026400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_dma_40026400_HASH 5LOz0siDq9ob6S_i9Yo0hK0gKkgtYAiRyCoqqc6zgBg

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_dma_40026400_ORD 133
#define DT_N_S_soc_S_dma_40026400_ORD_STR_SORTABLE 00133

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_dma_40026400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_dma_40026400_SUPPORTS_ORDS \
	134, /* /soc/sai1@40015800 */ \
	135, /* /soc/sai1@40015800/sai1a@4 */ \
	136, /* /soc/sai1@40015800/sai1b@24 */
#define DT_N_NODELABEL_DT_N_S_soc_S_dma_40026400_IDX_0_C_TOKEN dma2

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_dma_40026400_EXISTS 1
#define DT_N_INST_0_st_stm32_dma_v1 DT_N_S_soc_S_dma_40026400
#define DT_N_NODELABEL_dma2         DT_N_S_soc_S_dma_40026400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_dma_40026400_REG_NUM 1
#define DT_N_S_soc_S_dma_40026400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_REG_IDX_0_VAL_ADDRESS 1073898496 /* 0x40026400 */
#define DT_N_S_soc_S_dma_40026400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_dma_40026400_FOREACH_REG(fn) fn(DT_N_S_soc_S_dma_40026400, 0)
#define DT_N_S_soc_S_dma_40026400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40026400, 0)
#define DT_N_S_soc_S_dma_40026400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40026400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40026400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40026400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40026400_RANGES_NUM 0
#define DT_N_S_soc_S_dma_40026400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_dma_40026400_IRQ_NUM 8
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_0_VAL_irq 56
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_1_VAL_irq 57
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_2_VAL_irq 58
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_2_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_2_VAL_priority 0
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_2_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_2_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_3_VAL_irq 59
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_3_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_3_VAL_priority 0
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_3_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_3_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_4_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_4_VAL_irq 60
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_4_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_4_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_4_VAL_priority 0
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_4_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_4_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_5_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_5_VAL_irq 68
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_5_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_5_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_5_VAL_priority 0
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_5_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_5_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_6_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_6_VAL_irq 69
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_6_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_6_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_6_VAL_priority 0
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_6_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_6_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_7_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_7_VAL_irq 70
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_7_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_7_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_7_VAL_priority 0
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_7_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_IRQ_IDX_7_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40026400_IRQ_LEVEL 1
#define DT_N_S_soc_S_dma_40026400_COMPAT_MATCHES_st_stm32_dma_v1 1
#define DT_N_S_soc_S_dma_40026400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_dma_40026400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_COMPAT_MODEL_IDX_0 "stm32-dma-v1"
#define DT_N_S_soc_S_dma_40026400_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_dma_40026400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_dma_40026400_P_reg {1073898496 /* 0x40026400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_dma_40026400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_reg_IDX_0 1073898496
#define DT_N_S_soc_S_dma_40026400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_dma_40026400_P_reg_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_interrupts {56 /* 0x38 */, 0 /* 0x0 */, 57 /* 0x39 */, 0 /* 0x0 */, 58 /* 0x3a */, 0 /* 0x0 */, 59 /* 0x3b */, 0 /* 0x0 */, 60 /* 0x3c */, 0 /* 0x0 */, 68 /* 0x44 */, 0 /* 0x0 */, 69 /* 0x45 */, 0 /* 0x0 */, 70 /* 0x46 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_0 56
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_2 57
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_4_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_4 58
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_5_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_5 0
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_6_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_6 59
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_7_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_7 0
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_8_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_8 60
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_9_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_9 0
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_10_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_10 68
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_11_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_11 0
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_12_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_12 69
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_13_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_13 0
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_14_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_14 70
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_15_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_interrupts_IDX_15 0
#define DT_N_S_soc_S_dma_40026400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_st_mem2mem 1
#define DT_N_S_soc_S_dma_40026400_P_st_mem2mem_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_status "okay"
#define DT_N_S_soc_S_dma_40026400_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_dma_40026400_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_dma_40026400_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_dma_40026400_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_dma_40026400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_dma_40026400_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40026400, status, 0)
#define DT_N_S_soc_S_dma_40026400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40026400, status, 0)
#define DT_N_S_soc_S_dma_40026400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40026400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40026400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40026400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40026400_P_status_LEN 1
#define DT_N_S_soc_S_dma_40026400_P_status_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_compatible {"st,stm32-dma-v1"}
#define DT_N_S_soc_S_dma_40026400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_compatible_IDX_0 "st,stm32-dma-v1"
#define DT_N_S_soc_S_dma_40026400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-dma-v1
#define DT_N_S_soc_S_dma_40026400_P_compatible_IDX_0_STRING_TOKEN st_stm32_dma_v1
#define DT_N_S_soc_S_dma_40026400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_DMA_V1
#define DT_N_S_soc_S_dma_40026400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40026400, compatible, 0)
#define DT_N_S_soc_S_dma_40026400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40026400, compatible, 0)
#define DT_N_S_soc_S_dma_40026400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40026400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40026400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40026400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40026400_P_compatible_LEN 1
#define DT_N_S_soc_S_dma_40026400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_dma_40026400_P_clocks_IDX_0_VAL_bus 48
#define DT_N_S_soc_S_dma_40026400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_clocks_IDX_0_VAL_bits 4194304
#define DT_N_S_soc_S_dma_40026400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_dma_40026400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_dma_40026400, clocks, 0, bits)
#define DT_N_S_soc_S_dma_40026400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40026400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_dma_40026400, clocks, 0, bits)
#define DT_N_S_soc_S_dma_40026400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_dma_40026400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40026400, clocks, 0)
#define DT_N_S_soc_S_dma_40026400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40026400, clocks, 0)
#define DT_N_S_soc_S_dma_40026400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40026400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40026400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40026400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40026400_P_clocks_LEN 1
#define DT_N_S_soc_S_dma_40026400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_dma_coherent 0
#define DT_N_S_soc_S_dma_40026400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_dma_40026400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_wakeup_source 0
#define DT_N_S_soc_S_dma_40026400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_dma_40026400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_dma_40026400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/sai1@40015800
 *
 * Node identifier: DT_N_S_soc_S_sai1_40015800
 *
 * Binding (compatible = st,stm32-sai):
 *   $ZEPHYR_BASE\dts\bindings\i2s\st,stm32-sai.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_sai1_40015800_PATH "/soc/sai1@40015800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_sai1_40015800_FULL_NAME "sai1@40015800"
#define DT_N_S_soc_S_sai1_40015800_FULL_NAME_UNQUOTED sai1@40015800
#define DT_N_S_soc_S_sai1_40015800_FULL_NAME_TOKEN sai1_40015800
#define DT_N_S_soc_S_sai1_40015800_FULL_NAME_UPPER_TOKEN SAI1_40015800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_sai1_40015800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_sai1_40015800_CHILD_IDX 57

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_sai1_40015800_NODELABEL_NUM 1
#define DT_N_S_soc_S_sai1_40015800_FOREACH_NODELABEL(fn) fn(sai1)
#define DT_N_S_soc_S_sai1_40015800_FOREACH_NODELABEL_VARGS(fn, ...) fn(sai1, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_sai1_40015800_CHILD_NUM 2
#define DT_N_S_soc_S_sai1_40015800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_sai1_40015800_CHILD_UNIT_ADDR_INT_1073829892 DT_N_S_soc_S_sai1_40015800_S_sai1a_4
#define DT_N_S_soc_S_sai1_40015800_CHILD_UNIT_ADDR_INT_1073829924 DT_N_S_soc_S_sai1_40015800_S_sai1b_24
#define DT_N_S_soc_S_sai1_40015800_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24)
#define DT_N_S_soc_S_sai1_40015800_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24)
#define DT_N_S_soc_S_sai1_40015800_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, __VA_ARGS__) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_sai1_40015800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_sai1_40015800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_sai1_40015800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_sai1_40015800_HASH WR5_w2dA2xtA5oaW_H1mBO1gf3x_3rDHwhEiGTtzcPk

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_sai1_40015800_ORD 134
#define DT_N_S_soc_S_sai1_40015800_ORD_STR_SORTABLE 00134

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_sai1_40015800_REQUIRES_ORDS \
	4, /* /soc */ \
	9, /* /soc/rcc@40023800 */ \
	133, /* /soc/dma@40026400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_sai1_40015800_SUPPORTS_ORDS \
	135, /* /soc/sai1@40015800/sai1a@4 */ \
	136, /* /soc/sai1@40015800/sai1b@24 */
#define DT_N_NODELABEL_DT_N_S_soc_S_sai1_40015800_IDX_0_C_TOKEN sai1

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_sai1_40015800_EXISTS 1
#define DT_N_INST_0_st_stm32_sai DT_N_S_soc_S_sai1_40015800
#define DT_N_NODELABEL_sai1      DT_N_S_soc_S_sai1_40015800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_sai1_40015800_REG_NUM 1
#define DT_N_S_soc_S_sai1_40015800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_REG_IDX_0_VAL_ADDRESS 1073829888 /* 0x40015800 */
#define DT_N_S_soc_S_sai1_40015800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_sai1_40015800_FOREACH_REG(fn) fn(DT_N_S_soc_S_sai1_40015800, 0)
#define DT_N_S_soc_S_sai1_40015800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015800, 0)
#define DT_N_S_soc_S_sai1_40015800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_RANGES_NUM 1
#define DT_N_S_soc_S_sai1_40015800_RANGES_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_RANGES_IDX_0_VAL_CHILD_BUS_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_sai1_40015800_RANGES_IDX_0_VAL_PARENT_BUS_ADDRESS 1073829888 /* 0x40015800 */
#define DT_N_S_soc_S_sai1_40015800_RANGES_IDX_0_VAL_LENGTH 1024 /* 0x400 */
#define DT_N_S_soc_S_sai1_40015800_FOREACH_RANGE(fn) fn(DT_N_S_soc_S_sai1_40015800, 0)
#define DT_N_S_soc_S_sai1_40015800_IRQ_NUM 0
#define DT_N_S_soc_S_sai1_40015800_IRQ_LEVEL 0
#define DT_N_S_soc_S_sai1_40015800_COMPAT_MATCHES_st_stm32_sai 1
#define DT_N_S_soc_S_sai1_40015800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_sai1_40015800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_COMPAT_MODEL_IDX_0 "stm32-sai"
#define DT_N_S_soc_S_sai1_40015800_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_sai1_40015800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_sai1_40015800_P_reg {1073829888 /* 0x40015800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_sai1_40015800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_reg_IDX_0 1073829888
#define DT_N_S_soc_S_sai1_40015800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_sai1_40015800_P_reg_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_ranges {0 /* 0x0 */, 1073829888 /* 0x40015800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_sai1_40015800_P_ranges_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_ranges_IDX_0 0
#define DT_N_S_soc_S_sai1_40015800_P_ranges_IDX_1_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_ranges_IDX_1 1073829888
#define DT_N_S_soc_S_sai1_40015800_P_ranges_IDX_2_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_ranges_IDX_2 1024
#define DT_N_S_soc_S_sai1_40015800_P_ranges_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_status "disabled"
#define DT_N_S_soc_S_sai1_40015800_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_sai1_40015800_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_sai1_40015800_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_sai1_40015800_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_sai1_40015800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_sai1_40015800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015800, status, 0)
#define DT_N_S_soc_S_sai1_40015800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015800, status, 0)
#define DT_N_S_soc_S_sai1_40015800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_P_status_LEN 1
#define DT_N_S_soc_S_sai1_40015800_P_status_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_compatible {"st,stm32-sai"}
#define DT_N_S_soc_S_sai1_40015800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_compatible_IDX_0 "st,stm32-sai"
#define DT_N_S_soc_S_sai1_40015800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-sai
#define DT_N_S_soc_S_sai1_40015800_P_compatible_IDX_0_STRING_TOKEN st_stm32_sai
#define DT_N_S_soc_S_sai1_40015800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SAI
#define DT_N_S_soc_S_sai1_40015800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015800, compatible, 0)
#define DT_N_S_soc_S_sai1_40015800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015800, compatible, 0)
#define DT_N_S_soc_S_sai1_40015800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_P_compatible_LEN 1
#define DT_N_S_soc_S_sai1_40015800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_sai1_40015800_P_clocks_IDX_0_VAL_bus 68
#define DT_N_S_soc_S_sai1_40015800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_clocks_IDX_0_VAL_bits 4194304
#define DT_N_S_soc_S_sai1_40015800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_sai1_40015800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_sai1_40015800, clocks, 0, bits)
#define DT_N_S_soc_S_sai1_40015800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_sai1_40015800, clocks, 0, bits)
#define DT_N_S_soc_S_sai1_40015800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_sai1_40015800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015800, clocks, 0)
#define DT_N_S_soc_S_sai1_40015800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015800, clocks, 0)
#define DT_N_S_soc_S_sai1_40015800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_P_clocks_LEN 1
#define DT_N_S_soc_S_sai1_40015800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_dma_coherent 0
#define DT_N_S_soc_S_sai1_40015800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_sai1_40015800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_wakeup_source 0
#define DT_N_S_soc_S_sai1_40015800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_sai1_40015800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/sai1@40015800/sai1a@4
 *
 * Node identifier: DT_N_S_soc_S_sai1_40015800_S_sai1a_4
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_PATH "/soc/sai1@40015800/sai1a@4"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FULL_NAME "sai1a@4"
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FULL_NAME_UNQUOTED sai1a@4
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FULL_NAME_TOKEN sai1a_4
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FULL_NAME_UPPER_TOKEN SAI1A_4

/* Node parent (/soc/sai1@40015800) identifier: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_PARENT DT_N_S_soc_S_sai1_40015800

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_NODELABEL_NUM 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FOREACH_NODELABEL(fn) fn(sai1_a)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FOREACH_NODELABEL_VARGS(fn, ...) fn(sai1_a, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_sai1_40015800) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_CHILD_NUM 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_HASH JK8EiiFan3AbINWWnMUUAhEfvomK34oVBIhJ0_yrZtI

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_ORD 135
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_ORD_STR_SORTABLE 00135

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_REQUIRES_ORDS \
	133, /* /soc/dma@40026400 */ \
	134, /* /soc/sai1@40015800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_sai1_40015800_S_sai1a_4_IDX_0_C_TOKEN sai1_a

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_EXISTS 1
#define DT_N_NODELABEL_sai1_a DT_N_S_soc_S_sai1_40015800_S_sai1a_4

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_REG_NUM 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_REG_IDX_0_VAL_ADDRESS 1073829892 /* 0x40015804 */
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_REG_IDX_0_VAL_SIZE 32 /* 0x20 */
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FOREACH_REG(fn) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_RANGES_NUM 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_IRQ_NUM 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_IRQ_LEVEL 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_reg {4 /* 0x4 */, 32 /* 0x20 */}
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_reg_IDX_0 4
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_reg_IDX_1 32
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_reg_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_IDX_0_PH DT_N_S_soc_S_dma_40026400
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_IDX_0_VAL_channel 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_IDX_0_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_IDX_0_VAL_slot 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_IDX_0_VAL_slot_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_IDX_0_VAL_channel_config 141312
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_IDX_0_VAL_channel_config_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_IDX_0_VAL_features 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_IDX_0_VAL_features_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, dmas, 0, channel) \
	fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, dmas, 0, slot) \
	fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, dmas, 0, channel-config) \
	fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, dmas, 0, features)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, dmas, 0, channel) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, dmas, 0, slot) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, dmas, 0, channel-config) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, dmas, 0, features)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_IDX_0_NUM_CELLS 4
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, dmas, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, dmas, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, dmas, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, dmas, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_LEN 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dmas_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_mclk_enable 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_mclk_enable_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_mclk_divider "no-div"
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_mclk_divider_STRING_UNQUOTED no-div
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_mclk_divider_STRING_TOKEN no_div
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_mclk_divider_STRING_UPPER_TOKEN NO_DIV
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_mclk_divider_IDX_0 "no-div"
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_mclk_divider_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_mclk_divider_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_mclk_divider_IDX_0_ENUM_VAL_no_div_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_mclk_divider_ENUM_VAL_no_div_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_mclk_divider_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, mclk_divider, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_mclk_divider_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, mclk_divider, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_mclk_divider_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, mclk_divider, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_mclk_divider_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, mclk_divider, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_mclk_divider_LEN 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_mclk_divider_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_synchronous 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_synchronous_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_fifo_threshold "full"
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_fifo_threshold_STRING_UNQUOTED full
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_fifo_threshold_STRING_TOKEN full
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_fifo_threshold_STRING_UPPER_TOKEN FULL
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_fifo_threshold_IDX_0 "full"
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_fifo_threshold_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_fifo_threshold_IDX_0_ENUM_IDX 4
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_fifo_threshold_IDX_0_ENUM_VAL_full_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_fifo_threshold_ENUM_VAL_full_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_fifo_threshold_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, fifo_threshold, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_fifo_threshold_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, fifo_threshold, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_fifo_threshold_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, fifo_threshold, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_fifo_threshold_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, fifo_threshold, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_fifo_threshold_LEN 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_fifo_threshold_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_status "disabled"
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, status, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, status, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_status_LEN 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_status_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dma_coherent 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_wakeup_source 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1a_4_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/sai1@40015800/sai1b@24
 *
 * Node identifier: DT_N_S_soc_S_sai1_40015800_S_sai1b_24
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_PATH "/soc/sai1@40015800/sai1b@24"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FULL_NAME "sai1b@24"
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FULL_NAME_UNQUOTED sai1b@24
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FULL_NAME_TOKEN sai1b_24
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FULL_NAME_UPPER_TOKEN SAI1B_24

/* Node parent (/soc/sai1@40015800) identifier: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_PARENT DT_N_S_soc_S_sai1_40015800

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_NODELABEL_NUM 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FOREACH_NODELABEL(fn) fn(sai1_b)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FOREACH_NODELABEL_VARGS(fn, ...) fn(sai1_b, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_sai1_40015800) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_CHILD_NUM 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_HASH j7LE7CvI2oVXw4isbuSvdbJSjeGGUECdD7WDE4uXtcU

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_ORD 136
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_ORD_STR_SORTABLE 00136

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_REQUIRES_ORDS \
	133, /* /soc/dma@40026400 */ \
	134, /* /soc/sai1@40015800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_sai1_40015800_S_sai1b_24_IDX_0_C_TOKEN sai1_b

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_EXISTS 1
#define DT_N_NODELABEL_sai1_b DT_N_S_soc_S_sai1_40015800_S_sai1b_24

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_REG_NUM 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_REG_IDX_0_VAL_ADDRESS 1073829924 /* 0x40015824 */
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_REG_IDX_0_VAL_SIZE 32 /* 0x20 */
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FOREACH_REG(fn) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_RANGES_NUM 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_IRQ_NUM 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_IRQ_LEVEL 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_reg {36 /* 0x24 */, 32 /* 0x20 */}
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_reg_IDX_0 36
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_reg_IDX_1 32
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_reg_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_IDX_0_PH DT_N_S_soc_S_dma_40026400
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_IDX_0_VAL_channel 5
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_IDX_0_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_IDX_0_VAL_slot 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_IDX_0_VAL_slot_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_IDX_0_VAL_channel_config 141312
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_IDX_0_VAL_channel_config_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_IDX_0_VAL_features 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_IDX_0_VAL_features_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, dmas, 0, channel) \
	fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, dmas, 0, slot) \
	fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, dmas, 0, channel-config) \
	fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, dmas, 0, features)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, dmas, 0, channel) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, dmas, 0, slot) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, dmas, 0, channel-config) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, dmas, 0, features)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_IDX_0_NUM_CELLS 4
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, dmas, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, dmas, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, dmas, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, dmas, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_LEN 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dmas_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_mclk_enable 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_mclk_enable_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_mclk_divider "no-div"
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_mclk_divider_STRING_UNQUOTED no-div
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_mclk_divider_STRING_TOKEN no_div
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_mclk_divider_STRING_UPPER_TOKEN NO_DIV
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_mclk_divider_IDX_0 "no-div"
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_mclk_divider_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_mclk_divider_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_mclk_divider_IDX_0_ENUM_VAL_no_div_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_mclk_divider_ENUM_VAL_no_div_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_mclk_divider_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, mclk_divider, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_mclk_divider_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, mclk_divider, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_mclk_divider_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, mclk_divider, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_mclk_divider_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, mclk_divider, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_mclk_divider_LEN 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_mclk_divider_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_synchronous 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_synchronous_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_fifo_threshold "full"
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_fifo_threshold_STRING_UNQUOTED full
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_fifo_threshold_STRING_TOKEN full
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_fifo_threshold_STRING_UPPER_TOKEN FULL
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_fifo_threshold_IDX_0 "full"
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_fifo_threshold_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_fifo_threshold_IDX_0_ENUM_IDX 4
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_fifo_threshold_IDX_0_ENUM_VAL_full_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_fifo_threshold_ENUM_VAL_full_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_fifo_threshold_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, fifo_threshold, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_fifo_threshold_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, fifo_threshold, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_fifo_threshold_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, fifo_threshold, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_fifo_threshold_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, fifo_threshold, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_fifo_threshold_LEN 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_fifo_threshold_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_status "disabled"
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, status, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, status, 0)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_status_LEN 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_status_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dma_coherent 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_wakeup_source 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_sai1_40015800_S_sai1b_24_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000000
 *
 * Node identifier: DT_N_S_soc_S_timers_40000000
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE\dts\bindings\timer\st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000000_PATH "/soc/timers@40000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000000_FULL_NAME "timers@40000000"
#define DT_N_S_soc_S_timers_40000000_FULL_NAME_UNQUOTED timers@40000000
#define DT_N_S_soc_S_timers_40000000_FULL_NAME_TOKEN timers_40000000
#define DT_N_S_soc_S_timers_40000000_FULL_NAME_UPPER_TOKEN TIMERS_40000000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000000_CHILD_IDX 17

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000000_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40000000_FOREACH_NODELABEL(fn) fn(timers2)
#define DT_N_S_soc_S_timers_40000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers2, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000000_CHILD_NUM 3
#define DT_N_S_soc_S_timers_40000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40000000_S_pwm) fn(DT_N_S_soc_S_timers_40000000_S_counter) fn(DT_N_S_soc_S_timers_40000000_S_qdec)
#define DT_N_S_soc_S_timers_40000000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000000_S_counter) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000000_S_qdec)
#define DT_N_S_soc_S_timers_40000000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000000_S_counter, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000000_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000000_HASH EG81bdVGBcHLEHOWL0pmGPFAUziNY8yKUHEsHXKaWCc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000000_ORD 137
#define DT_N_S_soc_S_timers_40000000_ORD_STR_SORTABLE 00137

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000000_SUPPORTS_ORDS \
	138, /* /soc/timers@40000000/counter */ \
	139, /* /soc/timers@40000000/pwm */ \
	140, /* /soc/timers@40000000/qdec */
#define DT_N_NODELABEL_DT_N_S_soc_S_timers_40000000_IDX_0_C_TOKEN timers2

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000000_EXISTS 1
#define DT_N_INST_1_st_stm32_timers DT_N_S_soc_S_timers_40000000
#define DT_N_NODELABEL_timers2      DT_N_S_soc_S_timers_40000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000000_REG_NUM 1
#define DT_N_S_soc_S_timers_40000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_REG_IDX_0_VAL_ADDRESS 1073741824 /* 0x40000000 */
#define DT_N_S_soc_S_timers_40000000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40000000_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40000000, 0)
#define DT_N_S_soc_S_timers_40000000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, 0)
#define DT_N_S_soc_S_timers_40000000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000000_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_VAL_irq 28
#define DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40000000_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40000000_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40000000_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40000000_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40000000_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40000000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000000_P_reg {1073741824 /* 0x40000000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_reg_IDX_0 1073741824
#define DT_N_S_soc_S_timers_40000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_VAL_bits 1
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40000000, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000000, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_1_VAL_bus 21
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000000, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40000000, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000000, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40000000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40000000, clocks, 1)
#define DT_N_S_soc_S_timers_40000000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000000, clocks, 1)
#define DT_N_S_soc_S_timers_40000000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40000000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40000000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_VAL_id 1024
#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000000, resets, 0, id)
#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, resets, 0, id)
#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40000000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, resets, 0)
#define DT_N_S_soc_S_timers_40000000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, resets, 0)
#define DT_N_S_soc_S_timers_40000000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40000000_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40000000_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_countermode 0
#define DT_N_S_soc_S_timers_40000000_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40000000_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_slavemode "disabled"
#define DT_N_S_soc_S_timers_40000000_P_st_slavemode_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000000_P_st_slavemode_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000000_P_st_slavemode_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000000_P_st_slavemode_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000000_P_st_slavemode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_slavemode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000000_P_st_slavemode_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_slavemode_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_slavemode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40000000_P_st_slavemode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40000000_P_st_slavemode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_st_slavemode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_st_slavemode_LEN 1
#define DT_N_S_soc_S_timers_40000000_P_st_slavemode_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_trigger_selection "ITR0"
#define DT_N_S_soc_S_timers_40000000_P_st_trigger_selection_STRING_UNQUOTED ITR0
#define DT_N_S_soc_S_timers_40000000_P_st_trigger_selection_STRING_TOKEN ITR0
#define DT_N_S_soc_S_timers_40000000_P_st_trigger_selection_STRING_UPPER_TOKEN ITR0
#define DT_N_S_soc_S_timers_40000000_P_st_trigger_selection_IDX_0 "ITR0"
#define DT_N_S_soc_S_timers_40000000_P_st_trigger_selection_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_trigger_selection_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000000_P_st_trigger_selection_IDX_0_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_trigger_selection_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_trigger_selection_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40000000_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40000000_P_st_trigger_selection_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_st_trigger_selection_LEN 1
#define DT_N_S_soc_S_timers_40000000_P_st_trigger_selection_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_status "disabled"
#define DT_N_S_soc_S_timers_40000000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, status, 0)
#define DT_N_S_soc_S_timers_40000000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, status, 0)
#define DT_N_S_soc_S_timers_40000000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000000_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40000000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40000000_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, compatible, 0)
#define DT_N_S_soc_S_timers_40000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, compatible, 0)
#define DT_N_S_soc_S_timers_40000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_interrupts {28 /* 0x1c */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40000000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_interrupts_IDX_0 28
#define DT_N_S_soc_S_timers_40000000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40000000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000000/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40000000_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE\dts\bindings\counter\st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000000_S_counter_PATH "/soc/timers@40000000/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000000_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40000000_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40000000_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40000000_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40000000) identifier: */
#define DT_N_S_soc_S_timers_40000000_S_counter_PARENT DT_N_S_soc_S_timers_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000000_S_counter_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000000_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000000_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000000_S_counter_HASH q1HYCxKR_QqakI62hwcbYK3CrWp5E_XbPwXUySU4se8

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000000_S_counter_ORD 138
#define DT_N_S_soc_S_timers_40000000_S_counter_ORD_STR_SORTABLE 00138

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000000_S_counter_REQUIRES_ORDS \
	137, /* /soc/timers@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000000_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000000_S_counter_EXISTS 1
#define DT_N_INST_1_st_stm32_counter DT_N_S_soc_S_timers_40000000_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000000_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000000_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000000_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000000_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40000000_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000000_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40000000_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000000_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000000_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000000_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000000_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000000_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000000/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40000000_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_PATH "/soc/timers@40000000/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40000000_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40000000_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40000000_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40000000) identifier: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_PARENT DT_N_S_soc_S_timers_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000000_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_HASH EPAdjmCelZ_p_2x7j2JfW0691g5_Ul9BLhqJG9tnJMk

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_ORD 139
#define DT_N_S_soc_S_timers_40000000_S_pwm_ORD_STR_SORTABLE 00139

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_REQUIRES_ORDS \
	137, /* /soc/timers@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_EXISTS 1
#define DT_N_INST_1_st_stm32_pwm DT_N_S_soc_S_timers_40000000_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000000_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40000000_S_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status "disabled"
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000000/qdec
 *
 * Node identifier: DT_N_S_soc_S_timers_40000000_S_qdec
 *
 * Binding (compatible = st,stm32-qdec):
 *   $ZEPHYR_BASE\dts\bindings\sensor\st,stm32-qdec.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_PATH "/soc/timers@40000000/qdec"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_FULL_NAME "qdec"
#define DT_N_S_soc_S_timers_40000000_S_qdec_FULL_NAME_UNQUOTED qdec
#define DT_N_S_soc_S_timers_40000000_S_qdec_FULL_NAME_TOKEN qdec
#define DT_N_S_soc_S_timers_40000000_S_qdec_FULL_NAME_UPPER_TOKEN QDEC

/* Node parent (/soc/timers@40000000) identifier: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_PARENT DT_N_S_soc_S_timers_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000000_S_qdec_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_HASH xeDccz_QkMBo6l8_wMCsnsC88OsLpoM_UNpiSWf6rWM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_ORD 140
#define DT_N_S_soc_S_timers_40000000_S_qdec_ORD_STR_SORTABLE 00140

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_REQUIRES_ORDS \
	137, /* /soc/timers@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_EXISTS 1
#define DT_N_INST_1_st_stm32_qdec DT_N_S_soc_S_timers_40000000_S_qdec

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_REG_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_COMPAT_MATCHES_st_stm32_qdec 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000000_S_qdec_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_COMPAT_MODEL_IDX_0 "stm32-qdec"
#define DT_N_S_soc_S_timers_40000000_S_qdec_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_encoder_mode 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_encoder_mode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_encoder_mode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_encoder_mode_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_encoder_mode_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_encoder_mode_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_input_polarity_inverted 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_input_polarity_inverted_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_input_filter_level 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_input_filter_level_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status "disabled"
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible {"st,stm32-qdec"}
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_IDX_0 "st,stm32-qdec"
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-qdec
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_IDX_0_STRING_TOKEN st_stm32_qdec
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_QDEC
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000400
 *
 * Node identifier: DT_N_S_soc_S_timers_40000400
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE\dts\bindings\timer\st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000400_PATH "/soc/timers@40000400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000400_FULL_NAME "timers@40000400"
#define DT_N_S_soc_S_timers_40000400_FULL_NAME_UNQUOTED timers@40000400
#define DT_N_S_soc_S_timers_40000400_FULL_NAME_TOKEN timers_40000400
#define DT_N_S_soc_S_timers_40000400_FULL_NAME_UPPER_TOKEN TIMERS_40000400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40000400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000400_CHILD_IDX 18

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000400_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40000400_FOREACH_NODELABEL(fn) fn(timers3)
#define DT_N_S_soc_S_timers_40000400_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers3, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000400_CHILD_NUM 3
#define DT_N_S_soc_S_timers_40000400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000400_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40000400_S_pwm) fn(DT_N_S_soc_S_timers_40000400_S_counter) fn(DT_N_S_soc_S_timers_40000400_S_qdec)
#define DT_N_S_soc_S_timers_40000400_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000400_S_counter) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000400_S_qdec)
#define DT_N_S_soc_S_timers_40000400_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000400_S_counter, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000400_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000400_HASH baeUapzy1gNL2E23NOiz9371NQp1G8KhvyeXIcEPqLk

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000400_ORD 141
#define DT_N_S_soc_S_timers_40000400_ORD_STR_SORTABLE 00141

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000400_SUPPORTS_ORDS \
	142, /* /soc/timers@40000400/counter */ \
	143, /* /soc/timers@40000400/pwm */ \
	144, /* /soc/timers@40000400/qdec */
#define DT_N_NODELABEL_DT_N_S_soc_S_timers_40000400_IDX_0_C_TOKEN timers3

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000400_EXISTS 1
#define DT_N_INST_2_st_stm32_timers DT_N_S_soc_S_timers_40000400
#define DT_N_NODELABEL_timers3      DT_N_S_soc_S_timers_40000400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000400_REG_NUM 1
#define DT_N_S_soc_S_timers_40000400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_REG_IDX_0_VAL_ADDRESS 1073742848 /* 0x40000400 */
#define DT_N_S_soc_S_timers_40000400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40000400_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40000400, 0)
#define DT_N_S_soc_S_timers_40000400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, 0)
#define DT_N_S_soc_S_timers_40000400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000400_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_VAL_irq 29
#define DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40000400_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40000400_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40000400_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40000400_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40000400_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40000400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40000400_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000400_P_reg {1073742848 /* 0x40000400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40000400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_reg_IDX_0 1073742848
#define DT_N_S_soc_S_timers_40000400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40000400_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_VAL_bits 2
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40000400, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000400, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_1_VAL_bus 21
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000400, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40000400, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000400, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40000400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40000400, clocks, 1)
#define DT_N_S_soc_S_timers_40000400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000400, clocks, 1)
#define DT_N_S_soc_S_timers_40000400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40000400, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000400, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40000400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_VAL_id 1025
#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000400, resets, 0, id)
#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, resets, 0, id)
#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40000400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, resets, 0)
#define DT_N_S_soc_S_timers_40000400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, resets, 0)
#define DT_N_S_soc_S_timers_40000400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40000400_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40000400_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_countermode 0
#define DT_N_S_soc_S_timers_40000400_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40000400_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_slavemode "disabled"
#define DT_N_S_soc_S_timers_40000400_P_st_slavemode_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000400_P_st_slavemode_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000400_P_st_slavemode_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000400_P_st_slavemode_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000400_P_st_slavemode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_slavemode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000400_P_st_slavemode_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_slavemode_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_slavemode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40000400_P_st_slavemode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40000400_P_st_slavemode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_st_slavemode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_st_slavemode_LEN 1
#define DT_N_S_soc_S_timers_40000400_P_st_slavemode_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_trigger_selection "ITR0"
#define DT_N_S_soc_S_timers_40000400_P_st_trigger_selection_STRING_UNQUOTED ITR0
#define DT_N_S_soc_S_timers_40000400_P_st_trigger_selection_STRING_TOKEN ITR0
#define DT_N_S_soc_S_timers_40000400_P_st_trigger_selection_STRING_UPPER_TOKEN ITR0
#define DT_N_S_soc_S_timers_40000400_P_st_trigger_selection_IDX_0 "ITR0"
#define DT_N_S_soc_S_timers_40000400_P_st_trigger_selection_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_trigger_selection_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000400_P_st_trigger_selection_IDX_0_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_trigger_selection_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_trigger_selection_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40000400_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40000400_P_st_trigger_selection_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_st_trigger_selection_LEN 1
#define DT_N_S_soc_S_timers_40000400_P_st_trigger_selection_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_status "disabled"
#define DT_N_S_soc_S_timers_40000400_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000400_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000400_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000400_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, status, 0)
#define DT_N_S_soc_S_timers_40000400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, status, 0)
#define DT_N_S_soc_S_timers_40000400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000400_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40000400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40000400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40000400_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40000400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40000400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, compatible, 0)
#define DT_N_S_soc_S_timers_40000400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, compatible, 0)
#define DT_N_S_soc_S_timers_40000400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_interrupts {29 /* 0x1d */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40000400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_interrupts_IDX_0 29
#define DT_N_S_soc_S_timers_40000400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40000400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000400/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40000400_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE\dts\bindings\counter\st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000400_S_counter_PATH "/soc/timers@40000400/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000400_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40000400_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40000400_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40000400_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40000400) identifier: */
#define DT_N_S_soc_S_timers_40000400_S_counter_PARENT DT_N_S_soc_S_timers_40000400

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000400_S_counter_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000400_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000400) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000400_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000400_S_counter_HASH JNkHbJAdpxqum04dZjR7ujFGNxo62pj2eB31ikv0Phc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000400_S_counter_ORD 142
#define DT_N_S_soc_S_timers_40000400_S_counter_ORD_STR_SORTABLE 00142

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000400_S_counter_REQUIRES_ORDS \
	141, /* /soc/timers@40000400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000400_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000400_S_counter_EXISTS 1
#define DT_N_INST_2_st_stm32_counter DT_N_S_soc_S_timers_40000400_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000400_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000400_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000400_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000400_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40000400_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000400_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40000400_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000400_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000400_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000400_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000400_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000400_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000400/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40000400_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_PATH "/soc/timers@40000400/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40000400_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40000400_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40000400_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40000400) identifier: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_PARENT DT_N_S_soc_S_timers_40000400

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000400) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000400_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_HASH 3XEqw4Q0MqUTTpvQ0Yrht2rVkAAPsKyjdgccEVU8gEE

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_ORD 143
#define DT_N_S_soc_S_timers_40000400_S_pwm_ORD_STR_SORTABLE 00143

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_REQUIRES_ORDS \
	141, /* /soc/timers@40000400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_EXISTS 1
#define DT_N_INST_2_st_stm32_pwm DT_N_S_soc_S_timers_40000400_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000400_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40000400_S_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status "disabled"
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000400/qdec
 *
 * Node identifier: DT_N_S_soc_S_timers_40000400_S_qdec
 *
 * Binding (compatible = st,stm32-qdec):
 *   $ZEPHYR_BASE\dts\bindings\sensor\st,stm32-qdec.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_PATH "/soc/timers@40000400/qdec"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_FULL_NAME "qdec"
#define DT_N_S_soc_S_timers_40000400_S_qdec_FULL_NAME_UNQUOTED qdec
#define DT_N_S_soc_S_timers_40000400_S_qdec_FULL_NAME_TOKEN qdec
#define DT_N_S_soc_S_timers_40000400_S_qdec_FULL_NAME_UPPER_TOKEN QDEC

/* Node parent (/soc/timers@40000400) identifier: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_PARENT DT_N_S_soc_S_timers_40000400

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000400) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000400_S_qdec_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_HASH XoYaEyYM5OKvrXAYNQJb_KuMBHYcObyudHjfcpXT8_Q

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_ORD 144
#define DT_N_S_soc_S_timers_40000400_S_qdec_ORD_STR_SORTABLE 00144

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_REQUIRES_ORDS \
	141, /* /soc/timers@40000400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_EXISTS 1
#define DT_N_INST_2_st_stm32_qdec DT_N_S_soc_S_timers_40000400_S_qdec

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_REG_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_COMPAT_MATCHES_st_stm32_qdec 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000400_S_qdec_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_COMPAT_MODEL_IDX_0 "stm32-qdec"
#define DT_N_S_soc_S_timers_40000400_S_qdec_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_encoder_mode 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_encoder_mode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_encoder_mode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_encoder_mode_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_encoder_mode_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_encoder_mode_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_input_polarity_inverted 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_input_polarity_inverted_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_input_filter_level 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_input_filter_level_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status "disabled"
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible {"st,stm32-qdec"}
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_IDX_0 "st,stm32-qdec"
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-qdec
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_IDX_0_STRING_TOKEN st_stm32_qdec
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_QDEC
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000800
 *
 * Node identifier: DT_N_S_soc_S_timers_40000800
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE\dts\bindings\timer\st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000800_PATH "/soc/timers@40000800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000800_FULL_NAME "timers@40000800"
#define DT_N_S_soc_S_timers_40000800_FULL_NAME_UNQUOTED timers@40000800
#define DT_N_S_soc_S_timers_40000800_FULL_NAME_TOKEN timers_40000800
#define DT_N_S_soc_S_timers_40000800_FULL_NAME_UPPER_TOKEN TIMERS_40000800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40000800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000800_CHILD_IDX 19

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000800_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40000800_FOREACH_NODELABEL(fn) fn(timers4)
#define DT_N_S_soc_S_timers_40000800_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers4, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000800_CHILD_NUM 3
#define DT_N_S_soc_S_timers_40000800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000800_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40000800_S_pwm) fn(DT_N_S_soc_S_timers_40000800_S_counter) fn(DT_N_S_soc_S_timers_40000800_S_qdec)
#define DT_N_S_soc_S_timers_40000800_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000800_S_counter) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000800_S_qdec)
#define DT_N_S_soc_S_timers_40000800_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000800_S_counter, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000800_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000800_HASH VTBFi6bYiewunKr1vKL59kMmaq2wTI7eroMWbGtK2dw

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000800_ORD 145
#define DT_N_S_soc_S_timers_40000800_ORD_STR_SORTABLE 00145

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000800_SUPPORTS_ORDS \
	146, /* /soc/timers@40000800/counter */ \
	147, /* /soc/timers@40000800/pwm */ \
	148, /* /soc/timers@40000800/qdec */
#define DT_N_NODELABEL_DT_N_S_soc_S_timers_40000800_IDX_0_C_TOKEN timers4

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000800_EXISTS 1
#define DT_N_INST_3_st_stm32_timers DT_N_S_soc_S_timers_40000800
#define DT_N_NODELABEL_timers4      DT_N_S_soc_S_timers_40000800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000800_REG_NUM 1
#define DT_N_S_soc_S_timers_40000800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_REG_IDX_0_VAL_ADDRESS 1073743872 /* 0x40000800 */
#define DT_N_S_soc_S_timers_40000800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40000800_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40000800, 0)
#define DT_N_S_soc_S_timers_40000800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, 0)
#define DT_N_S_soc_S_timers_40000800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000800_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_VAL_irq 30
#define DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40000800_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40000800_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40000800_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40000800_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40000800_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40000800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40000800_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000800_P_reg {1073743872 /* 0x40000800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40000800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_reg_IDX_0 1073743872
#define DT_N_S_soc_S_timers_40000800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40000800_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_VAL_bits 4
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40000800, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000800, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_1_VAL_bus 21
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000800, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40000800, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000800, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40000800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40000800, clocks, 1)
#define DT_N_S_soc_S_timers_40000800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000800, clocks, 1)
#define DT_N_S_soc_S_timers_40000800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40000800, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000800, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40000800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_VAL_id 1026
#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000800, resets, 0, id)
#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, resets, 0, id)
#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40000800_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, resets, 0)
#define DT_N_S_soc_S_timers_40000800_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, resets, 0)
#define DT_N_S_soc_S_timers_40000800_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40000800_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40000800_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_countermode 0
#define DT_N_S_soc_S_timers_40000800_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40000800_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_slavemode "disabled"
#define DT_N_S_soc_S_timers_40000800_P_st_slavemode_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000800_P_st_slavemode_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000800_P_st_slavemode_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000800_P_st_slavemode_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000800_P_st_slavemode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_slavemode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000800_P_st_slavemode_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_slavemode_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_slavemode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40000800_P_st_slavemode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40000800_P_st_slavemode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_st_slavemode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_st_slavemode_LEN 1
#define DT_N_S_soc_S_timers_40000800_P_st_slavemode_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_trigger_selection "ITR0"
#define DT_N_S_soc_S_timers_40000800_P_st_trigger_selection_STRING_UNQUOTED ITR0
#define DT_N_S_soc_S_timers_40000800_P_st_trigger_selection_STRING_TOKEN ITR0
#define DT_N_S_soc_S_timers_40000800_P_st_trigger_selection_STRING_UPPER_TOKEN ITR0
#define DT_N_S_soc_S_timers_40000800_P_st_trigger_selection_IDX_0 "ITR0"
#define DT_N_S_soc_S_timers_40000800_P_st_trigger_selection_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_trigger_selection_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000800_P_st_trigger_selection_IDX_0_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_trigger_selection_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_trigger_selection_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40000800_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40000800_P_st_trigger_selection_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_st_trigger_selection_LEN 1
#define DT_N_S_soc_S_timers_40000800_P_st_trigger_selection_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_status "disabled"
#define DT_N_S_soc_S_timers_40000800_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000800_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000800_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000800_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, status, 0)
#define DT_N_S_soc_S_timers_40000800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, status, 0)
#define DT_N_S_soc_S_timers_40000800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000800_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40000800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40000800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40000800_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40000800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40000800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, compatible, 0)
#define DT_N_S_soc_S_timers_40000800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, compatible, 0)
#define DT_N_S_soc_S_timers_40000800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_interrupts {30 /* 0x1e */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40000800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_interrupts_IDX_0 30
#define DT_N_S_soc_S_timers_40000800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40000800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000800/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40000800_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE\dts\bindings\counter\st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000800_S_counter_PATH "/soc/timers@40000800/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000800_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40000800_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40000800_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40000800_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40000800) identifier: */
#define DT_N_S_soc_S_timers_40000800_S_counter_PARENT DT_N_S_soc_S_timers_40000800

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000800_S_counter_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000800_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000800) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000800_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000800_S_counter_HASH It81r5Kkjm8b1AfJHPW0z0jZ9dof3VW5417OU_gyZtc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000800_S_counter_ORD 146
#define DT_N_S_soc_S_timers_40000800_S_counter_ORD_STR_SORTABLE 00146

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000800_S_counter_REQUIRES_ORDS \
	145, /* /soc/timers@40000800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000800_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000800_S_counter_EXISTS 1
#define DT_N_INST_3_st_stm32_counter DT_N_S_soc_S_timers_40000800_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000800_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000800_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000800_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000800_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40000800_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000800_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40000800_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000800_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000800_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000800_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000800_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000800_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000800/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40000800_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_PATH "/soc/timers@40000800/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40000800_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40000800_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40000800_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40000800) identifier: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_PARENT DT_N_S_soc_S_timers_40000800

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000800) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000800_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_HASH rmmRd1gBchFTmlpcPkj2kPN2S9h0o7_bVDPViAglyik

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_ORD 147
#define DT_N_S_soc_S_timers_40000800_S_pwm_ORD_STR_SORTABLE 00147

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_REQUIRES_ORDS \
	145, /* /soc/timers@40000800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_EXISTS 1
#define DT_N_INST_3_st_stm32_pwm DT_N_S_soc_S_timers_40000800_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000800_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40000800_S_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status "disabled"
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000800/qdec
 *
 * Node identifier: DT_N_S_soc_S_timers_40000800_S_qdec
 *
 * Binding (compatible = st,stm32-qdec):
 *   $ZEPHYR_BASE\dts\bindings\sensor\st,stm32-qdec.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_PATH "/soc/timers@40000800/qdec"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_FULL_NAME "qdec"
#define DT_N_S_soc_S_timers_40000800_S_qdec_FULL_NAME_UNQUOTED qdec
#define DT_N_S_soc_S_timers_40000800_S_qdec_FULL_NAME_TOKEN qdec
#define DT_N_S_soc_S_timers_40000800_S_qdec_FULL_NAME_UPPER_TOKEN QDEC

/* Node parent (/soc/timers@40000800) identifier: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_PARENT DT_N_S_soc_S_timers_40000800

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000800) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000800_S_qdec_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_HASH NyJhopD0plir_yCl3bvK19fzvR7T8hmdf4SgsPGbBRs

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_ORD 148
#define DT_N_S_soc_S_timers_40000800_S_qdec_ORD_STR_SORTABLE 00148

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_REQUIRES_ORDS \
	145, /* /soc/timers@40000800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_EXISTS 1
#define DT_N_INST_3_st_stm32_qdec DT_N_S_soc_S_timers_40000800_S_qdec

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_REG_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_COMPAT_MATCHES_st_stm32_qdec 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000800_S_qdec_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_COMPAT_MODEL_IDX_0 "stm32-qdec"
#define DT_N_S_soc_S_timers_40000800_S_qdec_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_encoder_mode 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_encoder_mode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_encoder_mode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_encoder_mode_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_encoder_mode_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_encoder_mode_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_input_polarity_inverted 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_input_polarity_inverted_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_input_filter_level 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_input_filter_level_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status "disabled"
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible {"st,stm32-qdec"}
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_IDX_0 "st,stm32-qdec"
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-qdec
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_IDX_0_STRING_TOKEN st_stm32_qdec
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_QDEC
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000c00
 *
 * Node identifier: DT_N_S_soc_S_timers_40000c00
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE\dts\bindings\timer\st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000c00_PATH "/soc/timers@40000c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000c00_FULL_NAME "timers@40000c00"
#define DT_N_S_soc_S_timers_40000c00_FULL_NAME_UNQUOTED timers@40000c00
#define DT_N_S_soc_S_timers_40000c00_FULL_NAME_TOKEN timers_40000c00
#define DT_N_S_soc_S_timers_40000c00_FULL_NAME_UPPER_TOKEN TIMERS_40000C00

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40000c00_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000c00_CHILD_IDX 20

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40000c00_FOREACH_NODELABEL(fn) fn(timers5)
#define DT_N_S_soc_S_timers_40000c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers5, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000c00_CHILD_NUM 3
#define DT_N_S_soc_S_timers_40000c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000c00_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40000c00_S_pwm) fn(DT_N_S_soc_S_timers_40000c00_S_counter) fn(DT_N_S_soc_S_timers_40000c00_S_qdec)
#define DT_N_S_soc_S_timers_40000c00_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000c00_S_counter) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000c00_S_qdec)
#define DT_N_S_soc_S_timers_40000c00_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000c00_S_counter, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000c00_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000c00_HASH QK_gD7RT_mF_sn_to7wpxIKr0c1D_KZ7j86aqguJXxk

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000c00_ORD 149
#define DT_N_S_soc_S_timers_40000c00_ORD_STR_SORTABLE 00149

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000c00_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000c00_SUPPORTS_ORDS \
	150, /* /soc/timers@40000c00/counter */ \
	151, /* /soc/timers@40000c00/pwm */ \
	152, /* /soc/timers@40000c00/qdec */
#define DT_N_NODELABEL_DT_N_S_soc_S_timers_40000c00_IDX_0_C_TOKEN timers5

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000c00_EXISTS 1
#define DT_N_INST_4_st_stm32_timers DT_N_S_soc_S_timers_40000c00
#define DT_N_NODELABEL_timers5      DT_N_S_soc_S_timers_40000c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000c00_REG_NUM 1
#define DT_N_S_soc_S_timers_40000c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_REG_IDX_0_VAL_ADDRESS 1073744896 /* 0x40000c00 */
#define DT_N_S_soc_S_timers_40000c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40000c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40000c00, 0)
#define DT_N_S_soc_S_timers_40000c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, 0)
#define DT_N_S_soc_S_timers_40000c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000c00_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40000c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_IRQ_IDX_0_VAL_irq 50
#define DT_N_S_soc_S_timers_40000c00_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40000c00_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40000c00_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40000c00_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40000c00_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40000c00_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40000c00_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40000c00_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40000c00_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40000c00_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40000c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40000c00_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000c00_P_reg {1073744896 /* 0x40000c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40000c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_reg_IDX_0 1073744896
#define DT_N_S_soc_S_timers_40000c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40000c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_VAL_bits 8
#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40000c00, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000c00, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_1_VAL_bus 21
#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000c00, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40000c00, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000c00, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40000c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40000c00, clocks, 1)
#define DT_N_S_soc_S_timers_40000c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000c00, clocks, 1)
#define DT_N_S_soc_S_timers_40000c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40000c00, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000c00, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40000c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_timers_40000c00_P_resets_IDX_0_VAL_id 1027
#define DT_N_S_soc_S_timers_40000c00_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000c00, resets, 0, id)
#define DT_N_S_soc_S_timers_40000c00_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, resets, 0, id)
#define DT_N_S_soc_S_timers_40000c00_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40000c00_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00, resets, 0)
#define DT_N_S_soc_S_timers_40000c00_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, resets, 0)
#define DT_N_S_soc_S_timers_40000c00_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40000c00_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40000c00_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_st_countermode 0
#define DT_N_S_soc_S_timers_40000c00_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40000c00_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40000c00_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40000c00_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40000c00_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40000c00_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40000c00_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000c00_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40000c00_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40000c00_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40000c00_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_st_slavemode "disabled"
#define DT_N_S_soc_S_timers_40000c00_P_st_slavemode_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000c00_P_st_slavemode_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000c00_P_st_slavemode_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000c00_P_st_slavemode_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000c00_P_st_slavemode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_st_slavemode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000c00_P_st_slavemode_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_st_slavemode_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_st_slavemode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40000c00_P_st_slavemode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40000c00_P_st_slavemode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_P_st_slavemode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_P_st_slavemode_LEN 1
#define DT_N_S_soc_S_timers_40000c00_P_st_slavemode_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_st_trigger_selection "ITR0"
#define DT_N_S_soc_S_timers_40000c00_P_st_trigger_selection_STRING_UNQUOTED ITR0
#define DT_N_S_soc_S_timers_40000c00_P_st_trigger_selection_STRING_TOKEN ITR0
#define DT_N_S_soc_S_timers_40000c00_P_st_trigger_selection_STRING_UPPER_TOKEN ITR0
#define DT_N_S_soc_S_timers_40000c00_P_st_trigger_selection_IDX_0 "ITR0"
#define DT_N_S_soc_S_timers_40000c00_P_st_trigger_selection_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_st_trigger_selection_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000c00_P_st_trigger_selection_IDX_0_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_st_trigger_selection_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_st_trigger_selection_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40000c00_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40000c00_P_st_trigger_selection_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_P_st_trigger_selection_LEN 1
#define DT_N_S_soc_S_timers_40000c00_P_st_trigger_selection_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_status "disabled"
#define DT_N_S_soc_S_timers_40000c00_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000c00_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000c00_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000c00_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000c00_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00, status, 0)
#define DT_N_S_soc_S_timers_40000c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, status, 0)
#define DT_N_S_soc_S_timers_40000c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000c00_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40000c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40000c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40000c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40000c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40000c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00, compatible, 0)
#define DT_N_S_soc_S_timers_40000c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, compatible, 0)
#define DT_N_S_soc_S_timers_40000c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_interrupts {50 /* 0x32 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40000c00_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_interrupts_IDX_0 50
#define DT_N_S_soc_S_timers_40000c00_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40000c00_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000c00_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000c00/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40000c00_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE\dts\bindings\counter\st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000c00_S_counter_PATH "/soc/timers@40000c00/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000c00_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40000c00_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40000c00_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40000c00_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40000c00) identifier: */
#define DT_N_S_soc_S_timers_40000c00_S_counter_PARENT DT_N_S_soc_S_timers_40000c00

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000c00_S_counter_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000c00_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000c00_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000c00_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000c00_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000c00_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000c00_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000c00_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000c00_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000c00_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000c00_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000c00_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000c00_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000c00_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000c00_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000c00_S_counter_HASH SRmSz9_Gy7Y2Ew5bN2f2oN589iJ0Ygd6yjjRU92Vo2Q

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000c00_S_counter_ORD 150
#define DT_N_S_soc_S_timers_40000c00_S_counter_ORD_STR_SORTABLE 00150

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000c00_S_counter_REQUIRES_ORDS \
	149, /* /soc/timers@40000c00 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000c00_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000c00_S_counter_EXISTS 1
#define DT_N_INST_4_st_stm32_counter DT_N_S_soc_S_timers_40000c00_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000c00_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40000c00_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000c00_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000c00_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000c00_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000c00_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000c00_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000c00_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000c00_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000c00_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40000c00_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000c00_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40000c00_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000c00_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000c00_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000c00/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40000c00_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000c00_S_pwm_PATH "/soc/timers@40000c00/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40000c00) identifier: */
#define DT_N_S_soc_S_timers_40000c00_S_pwm_PARENT DT_N_S_soc_S_timers_40000c00

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000c00_S_pwm_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000c00_S_pwm_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000c00_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000c00_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000c00_S_pwm_HASH KSO3eNoSPYFOR_AlcenmOupE8OUZymwAp8eJUzabeJg

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000c00_S_pwm_ORD 151
#define DT_N_S_soc_S_timers_40000c00_S_pwm_ORD_STR_SORTABLE 00151

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000c00_S_pwm_REQUIRES_ORDS \
	149, /* /soc/timers@40000c00 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000c00_S_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000c00_S_pwm_EXISTS 1
#define DT_N_INST_4_st_stm32_pwm DT_N_S_soc_S_timers_40000c00_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000c00_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000c00_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000c00_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000c00_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000c00_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000c00_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40000c00_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000c00_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40000c00_S_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000c00_S_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status "disabled"
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000c00/qdec
 *
 * Node identifier: DT_N_S_soc_S_timers_40000c00_S_qdec
 *
 * Binding (compatible = st,stm32-qdec):
 *   $ZEPHYR_BASE\dts\bindings\sensor\st,stm32-qdec.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000c00_S_qdec_PATH "/soc/timers@40000c00/qdec"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FULL_NAME "qdec"
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FULL_NAME_UNQUOTED qdec
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FULL_NAME_TOKEN qdec
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FULL_NAME_UPPER_TOKEN QDEC

/* Node parent (/soc/timers@40000c00) identifier: */
#define DT_N_S_soc_S_timers_40000c00_S_qdec_PARENT DT_N_S_soc_S_timers_40000c00

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000c00_S_qdec_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000c00_S_qdec_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000c00_S_qdec_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000c00_S_qdec_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000c00_S_qdec_HASH jNirdOed3M2njdX81LmcaX9MYHY_UGZKXxxi6PNUwD0

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000c00_S_qdec_ORD 152
#define DT_N_S_soc_S_timers_40000c00_S_qdec_ORD_STR_SORTABLE 00152

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000c00_S_qdec_REQUIRES_ORDS \
	149, /* /soc/timers@40000c00 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000c00_S_qdec_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000c00_S_qdec_EXISTS 1
#define DT_N_INST_4_st_stm32_qdec DT_N_S_soc_S_timers_40000c00_S_qdec

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000c00_S_qdec_REG_NUM 0
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000c00_S_qdec_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000c00_S_qdec_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000c00_S_qdec_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000c00_S_qdec_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000c00_S_qdec_COMPAT_MATCHES_st_stm32_qdec 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000c00_S_qdec_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_COMPAT_MODEL_IDX_0 "stm32-qdec"
#define DT_N_S_soc_S_timers_40000c00_S_qdec_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000c00_S_qdec_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_st_encoder_mode 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_st_encoder_mode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_st_encoder_mode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_st_encoder_mode_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_st_encoder_mode_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_st_encoder_mode_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_st_input_polarity_inverted 0
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_st_input_polarity_inverted_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_st_input_filter_level 0
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_st_input_filter_level_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_status "disabled"
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_compatible {"st,stm32-qdec"}
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_compatible_IDX_0 "st,stm32-qdec"
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-qdec
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_compatible_IDX_0_STRING_TOKEN st_stm32_qdec
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_QDEC
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000c00_S_qdec_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40001000
 *
 * Node identifier: DT_N_S_soc_S_timers_40001000
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE\dts\bindings\timer\st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40001000_PATH "/soc/timers@40001000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40001000_FULL_NAME "timers@40001000"
#define DT_N_S_soc_S_timers_40001000_FULL_NAME_UNQUOTED timers@40001000
#define DT_N_S_soc_S_timers_40001000_FULL_NAME_TOKEN timers_40001000
#define DT_N_S_soc_S_timers_40001000_FULL_NAME_UPPER_TOKEN TIMERS_40001000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40001000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40001000_CHILD_IDX 37

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40001000_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40001000_FOREACH_NODELABEL(fn) fn(timers6)
#define DT_N_S_soc_S_timers_40001000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers6, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40001000_CHILD_NUM 1
#define DT_N_S_soc_S_timers_40001000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40001000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40001000_S_counter)
#define DT_N_S_soc_S_timers_40001000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000_S_counter)
#define DT_N_S_soc_S_timers_40001000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40001000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40001000_HASH Nsz_iy2H8UvqHZMouFTv3bvFrOuL3LyjaTTN24v0eBQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40001000_ORD 153
#define DT_N_S_soc_S_timers_40001000_ORD_STR_SORTABLE 00153

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40001000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40001000_SUPPORTS_ORDS \
	154, /* /soc/timers@40001000/counter */
#define DT_N_NODELABEL_DT_N_S_soc_S_timers_40001000_IDX_0_C_TOKEN timers6

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40001000_EXISTS 1
#define DT_N_INST_8_st_stm32_timers DT_N_S_soc_S_timers_40001000
#define DT_N_NODELABEL_timers6      DT_N_S_soc_S_timers_40001000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40001000_REG_NUM 1
#define DT_N_S_soc_S_timers_40001000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_REG_IDX_0_VAL_ADDRESS 1073745920 /* 0x40001000 */
#define DT_N_S_soc_S_timers_40001000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40001000_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40001000, 0)
#define DT_N_S_soc_S_timers_40001000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, 0)
#define DT_N_S_soc_S_timers_40001000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40001000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40001000_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_VAL_irq 54
#define DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40001000_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40001000_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40001000_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40001000_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40001000_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40001000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40001000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40001000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40001000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40001000_P_reg {1073745920 /* 0x40001000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40001000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_reg_IDX_0 1073745920
#define DT_N_S_soc_S_timers_40001000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40001000_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_VAL_bits 16
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40001000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40001000, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001000, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_1_VAL_bus 21
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40001000, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40001000, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001000, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40001000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40001000, clocks, 1)
#define DT_N_S_soc_S_timers_40001000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001000, clocks, 1)
#define DT_N_S_soc_S_timers_40001000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40001000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40001000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_VAL_id 1028
#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40001000, resets, 0, id)
#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, resets, 0, id)
#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40001000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, resets, 0)
#define DT_N_S_soc_S_timers_40001000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, resets, 0)
#define DT_N_S_soc_S_timers_40001000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40001000_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40001000_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_countermode 0
#define DT_N_S_soc_S_timers_40001000_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40001000_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_slavemode "disabled"
#define DT_N_S_soc_S_timers_40001000_P_st_slavemode_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40001000_P_st_slavemode_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40001000_P_st_slavemode_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40001000_P_st_slavemode_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40001000_P_st_slavemode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_slavemode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40001000_P_st_slavemode_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_slavemode_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_slavemode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40001000_P_st_slavemode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40001000_P_st_slavemode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_st_slavemode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_st_slavemode_LEN 1
#define DT_N_S_soc_S_timers_40001000_P_st_slavemode_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_trigger_selection "ITR0"
#define DT_N_S_soc_S_timers_40001000_P_st_trigger_selection_STRING_UNQUOTED ITR0
#define DT_N_S_soc_S_timers_40001000_P_st_trigger_selection_STRING_TOKEN ITR0
#define DT_N_S_soc_S_timers_40001000_P_st_trigger_selection_STRING_UPPER_TOKEN ITR0
#define DT_N_S_soc_S_timers_40001000_P_st_trigger_selection_IDX_0 "ITR0"
#define DT_N_S_soc_S_timers_40001000_P_st_trigger_selection_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_trigger_selection_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40001000_P_st_trigger_selection_IDX_0_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_trigger_selection_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_trigger_selection_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40001000_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40001000_P_st_trigger_selection_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_st_trigger_selection_LEN 1
#define DT_N_S_soc_S_timers_40001000_P_st_trigger_selection_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_status "disabled"
#define DT_N_S_soc_S_timers_40001000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40001000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40001000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40001000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40001000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40001000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, status, 0)
#define DT_N_S_soc_S_timers_40001000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, status, 0)
#define DT_N_S_soc_S_timers_40001000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_status_LEN 1
#define DT_N_S_soc_S_timers_40001000_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40001000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40001000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40001000_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40001000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40001000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, compatible, 0)
#define DT_N_S_soc_S_timers_40001000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, compatible, 0)
#define DT_N_S_soc_S_timers_40001000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40001000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_interrupts {54 /* 0x36 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40001000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_interrupts_IDX_0 54
#define DT_N_S_soc_S_timers_40001000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40001000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40001000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40001000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40001000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40001000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40001000/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40001000_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE\dts\bindings\counter\st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40001000_S_counter_PATH "/soc/timers@40001000/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40001000_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40001000_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40001000_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40001000_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40001000) identifier: */
#define DT_N_S_soc_S_timers_40001000_S_counter_PARENT DT_N_S_soc_S_timers_40001000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40001000_S_counter_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40001000_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40001000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40001000_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40001000_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40001000_S_counter_HASH kRqNwCO_GFQ9B_IU80aWEsZniZ2xLsueygEKHK_oRqE

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40001000_S_counter_ORD 154
#define DT_N_S_soc_S_timers_40001000_S_counter_ORD_STR_SORTABLE 00154

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40001000_S_counter_REQUIRES_ORDS \
	153, /* /soc/timers@40001000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40001000_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40001000_S_counter_EXISTS 1
#define DT_N_INST_8_st_stm32_counter DT_N_S_soc_S_timers_40001000_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40001000_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40001000_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40001000_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40001000_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40001000_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40001000_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40001000_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40001000_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40001000_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40001000_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40001000_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40001000_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40001000_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40001400
 *
 * Node identifier: DT_N_S_soc_S_timers_40001400
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE\dts\bindings\timer\st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40001400_PATH "/soc/timers@40001400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40001400_FULL_NAME "timers@40001400"
#define DT_N_S_soc_S_timers_40001400_FULL_NAME_UNQUOTED timers@40001400
#define DT_N_S_soc_S_timers_40001400_FULL_NAME_TOKEN timers_40001400
#define DT_N_S_soc_S_timers_40001400_FULL_NAME_UPPER_TOKEN TIMERS_40001400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40001400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40001400_CHILD_IDX 38

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40001400_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40001400_FOREACH_NODELABEL(fn) fn(timers7)
#define DT_N_S_soc_S_timers_40001400_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers7, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40001400_CHILD_NUM 1
#define DT_N_S_soc_S_timers_40001400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40001400_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40001400_S_counter)
#define DT_N_S_soc_S_timers_40001400_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400_S_counter)
#define DT_N_S_soc_S_timers_40001400_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40001400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40001400_HASH NWGZgzDJgqZSuO0DPWROIlkjRWjN3_VzkmbGsEAbECw

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40001400_ORD 155
#define DT_N_S_soc_S_timers_40001400_ORD_STR_SORTABLE 00155

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40001400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40001400_SUPPORTS_ORDS \
	156, /* /soc/timers@40001400/counter */
#define DT_N_NODELABEL_DT_N_S_soc_S_timers_40001400_IDX_0_C_TOKEN timers7

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40001400_EXISTS 1
#define DT_N_INST_9_st_stm32_timers DT_N_S_soc_S_timers_40001400
#define DT_N_NODELABEL_timers7      DT_N_S_soc_S_timers_40001400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40001400_REG_NUM 1
#define DT_N_S_soc_S_timers_40001400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_REG_IDX_0_VAL_ADDRESS 1073746944 /* 0x40001400 */
#define DT_N_S_soc_S_timers_40001400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40001400_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40001400, 0)
#define DT_N_S_soc_S_timers_40001400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, 0)
#define DT_N_S_soc_S_timers_40001400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40001400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40001400_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_VAL_irq 55
#define DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40001400_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40001400_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40001400_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40001400_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40001400_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40001400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40001400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40001400_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40001400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40001400_P_reg {1073746944 /* 0x40001400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40001400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_reg_IDX_0 1073746944
#define DT_N_S_soc_S_timers_40001400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40001400_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_VAL_bits 32
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40001400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40001400, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001400, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_1_VAL_bus 21
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40001400, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40001400, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001400, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40001400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40001400, clocks, 1)
#define DT_N_S_soc_S_timers_40001400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001400, clocks, 1)
#define DT_N_S_soc_S_timers_40001400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40001400, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001400, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40001400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_VAL_id 1029
#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40001400, resets, 0, id)
#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, resets, 0, id)
#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40001400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, resets, 0)
#define DT_N_S_soc_S_timers_40001400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, resets, 0)
#define DT_N_S_soc_S_timers_40001400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40001400_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40001400_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_countermode 0
#define DT_N_S_soc_S_timers_40001400_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40001400_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_slavemode "disabled"
#define DT_N_S_soc_S_timers_40001400_P_st_slavemode_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40001400_P_st_slavemode_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40001400_P_st_slavemode_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40001400_P_st_slavemode_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40001400_P_st_slavemode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_slavemode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40001400_P_st_slavemode_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_slavemode_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_slavemode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40001400_P_st_slavemode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40001400_P_st_slavemode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_st_slavemode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_st_slavemode_LEN 1
#define DT_N_S_soc_S_timers_40001400_P_st_slavemode_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_trigger_selection "ITR0"
#define DT_N_S_soc_S_timers_40001400_P_st_trigger_selection_STRING_UNQUOTED ITR0
#define DT_N_S_soc_S_timers_40001400_P_st_trigger_selection_STRING_TOKEN ITR0
#define DT_N_S_soc_S_timers_40001400_P_st_trigger_selection_STRING_UPPER_TOKEN ITR0
#define DT_N_S_soc_S_timers_40001400_P_st_trigger_selection_IDX_0 "ITR0"
#define DT_N_S_soc_S_timers_40001400_P_st_trigger_selection_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_trigger_selection_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40001400_P_st_trigger_selection_IDX_0_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_trigger_selection_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_trigger_selection_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40001400_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40001400_P_st_trigger_selection_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_st_trigger_selection_LEN 1
#define DT_N_S_soc_S_timers_40001400_P_st_trigger_selection_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_status "disabled"
#define DT_N_S_soc_S_timers_40001400_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40001400_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40001400_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40001400_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40001400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40001400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, status, 0)
#define DT_N_S_soc_S_timers_40001400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, status, 0)
#define DT_N_S_soc_S_timers_40001400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_status_LEN 1
#define DT_N_S_soc_S_timers_40001400_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40001400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40001400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40001400_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40001400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40001400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, compatible, 0)
#define DT_N_S_soc_S_timers_40001400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, compatible, 0)
#define DT_N_S_soc_S_timers_40001400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40001400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_interrupts {55 /* 0x37 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40001400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_interrupts_IDX_0 55
#define DT_N_S_soc_S_timers_40001400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40001400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40001400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40001400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40001400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40001400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40001400/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40001400_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE\dts\bindings\counter\st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40001400_S_counter_PATH "/soc/timers@40001400/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40001400_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40001400_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40001400_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40001400_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40001400) identifier: */
#define DT_N_S_soc_S_timers_40001400_S_counter_PARENT DT_N_S_soc_S_timers_40001400

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40001400_S_counter_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40001400_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40001400) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40001400_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40001400_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40001400_S_counter_HASH yUMrsaqgcXElOUnLnHc7vIdLGcToiUBEnmAPHwvJ0BA

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40001400_S_counter_ORD 156
#define DT_N_S_soc_S_timers_40001400_S_counter_ORD_STR_SORTABLE 00156

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40001400_S_counter_REQUIRES_ORDS \
	155, /* /soc/timers@40001400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40001400_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40001400_S_counter_EXISTS 1
#define DT_N_INST_9_st_stm32_counter DT_N_S_soc_S_timers_40001400_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40001400_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40001400_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40001400_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40001400_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40001400_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40001400_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40001400_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40001400_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40001400_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40001400_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40001400_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40001400_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40001400_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40001800
 *
 * Node identifier: DT_N_S_soc_S_timers_40001800
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE\dts\bindings\timer\st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40001800_PATH "/soc/timers@40001800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40001800_FULL_NAME "timers@40001800"
#define DT_N_S_soc_S_timers_40001800_FULL_NAME_UNQUOTED timers@40001800
#define DT_N_S_soc_S_timers_40001800_FULL_NAME_TOKEN timers_40001800
#define DT_N_S_soc_S_timers_40001800_FULL_NAME_UPPER_TOKEN TIMERS_40001800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40001800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40001800_CHILD_IDX 40

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40001800_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40001800_FOREACH_NODELABEL(fn) fn(timers12)
#define DT_N_S_soc_S_timers_40001800_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers12, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40001800_CHILD_NUM 2
#define DT_N_S_soc_S_timers_40001800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40001800_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40001800_S_pwm) fn(DT_N_S_soc_S_timers_40001800_S_counter)
#define DT_N_S_soc_S_timers_40001800_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001800_S_counter)
#define DT_N_S_soc_S_timers_40001800_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001800_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001800_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40001800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40001800_HASH qfLQQZgyR253_Bl3FxzOIzJN7i8JBpwjwqhvZ_fm11E

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40001800_ORD 157
#define DT_N_S_soc_S_timers_40001800_ORD_STR_SORTABLE 00157

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40001800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40001800_SUPPORTS_ORDS \
	158, /* /soc/timers@40001800/counter */ \
	159, /* /soc/timers@40001800/pwm */
#define DT_N_NODELABEL_DT_N_S_soc_S_timers_40001800_IDX_0_C_TOKEN timers12

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40001800_EXISTS 1
#define DT_N_INST_11_st_stm32_timers DT_N_S_soc_S_timers_40001800
#define DT_N_NODELABEL_timers12      DT_N_S_soc_S_timers_40001800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40001800_REG_NUM 1
#define DT_N_S_soc_S_timers_40001800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_REG_IDX_0_VAL_ADDRESS 1073747968 /* 0x40001800 */
#define DT_N_S_soc_S_timers_40001800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40001800_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40001800, 0)
#define DT_N_S_soc_S_timers_40001800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, 0)
#define DT_N_S_soc_S_timers_40001800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40001800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40001800_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40001800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_IRQ_IDX_0_VAL_irq 43
#define DT_N_S_soc_S_timers_40001800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40001800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40001800_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40001800_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40001800_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40001800_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40001800_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40001800_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40001800_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40001800_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40001800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40001800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40001800_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40001800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40001800_P_reg {1073747968 /* 0x40001800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40001800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_reg_IDX_0 1073747968
#define DT_N_S_soc_S_timers_40001800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40001800_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_VAL_bits 64
#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40001800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40001800, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001800, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_1_VAL_bus 21
#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40001800, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40001800, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001800, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40001800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40001800, clocks, 1)
#define DT_N_S_soc_S_timers_40001800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001800, clocks, 1)
#define DT_N_S_soc_S_timers_40001800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40001800, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001800, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40001800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_timers_40001800_P_resets_IDX_0_VAL_id 1030
#define DT_N_S_soc_S_timers_40001800_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40001800, resets, 0, id)
#define DT_N_S_soc_S_timers_40001800_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, resets, 0, id)
#define DT_N_S_soc_S_timers_40001800_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40001800_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800, resets, 0)
#define DT_N_S_soc_S_timers_40001800_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, resets, 0)
#define DT_N_S_soc_S_timers_40001800_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40001800_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40001800_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_st_countermode 0
#define DT_N_S_soc_S_timers_40001800_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40001800_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40001800_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40001800_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40001800_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40001800_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40001800_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40001800_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40001800_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40001800_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40001800_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_st_slavemode "disabled"
#define DT_N_S_soc_S_timers_40001800_P_st_slavemode_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40001800_P_st_slavemode_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40001800_P_st_slavemode_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40001800_P_st_slavemode_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40001800_P_st_slavemode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_st_slavemode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40001800_P_st_slavemode_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_st_slavemode_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_st_slavemode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40001800_P_st_slavemode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40001800_P_st_slavemode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_P_st_slavemode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_P_st_slavemode_LEN 1
#define DT_N_S_soc_S_timers_40001800_P_st_slavemode_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_st_trigger_selection "ITR0"
#define DT_N_S_soc_S_timers_40001800_P_st_trigger_selection_STRING_UNQUOTED ITR0
#define DT_N_S_soc_S_timers_40001800_P_st_trigger_selection_STRING_TOKEN ITR0
#define DT_N_S_soc_S_timers_40001800_P_st_trigger_selection_STRING_UPPER_TOKEN ITR0
#define DT_N_S_soc_S_timers_40001800_P_st_trigger_selection_IDX_0 "ITR0"
#define DT_N_S_soc_S_timers_40001800_P_st_trigger_selection_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_st_trigger_selection_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40001800_P_st_trigger_selection_IDX_0_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_st_trigger_selection_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_st_trigger_selection_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40001800_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40001800_P_st_trigger_selection_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_P_st_trigger_selection_LEN 1
#define DT_N_S_soc_S_timers_40001800_P_st_trigger_selection_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_status "disabled"
#define DT_N_S_soc_S_timers_40001800_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40001800_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40001800_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40001800_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40001800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40001800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800, status, 0)
#define DT_N_S_soc_S_timers_40001800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, status, 0)
#define DT_N_S_soc_S_timers_40001800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_P_status_LEN 1
#define DT_N_S_soc_S_timers_40001800_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40001800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40001800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40001800_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40001800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40001800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800, compatible, 0)
#define DT_N_S_soc_S_timers_40001800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, compatible, 0)
#define DT_N_S_soc_S_timers_40001800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40001800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_interrupts {43 /* 0x2b */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40001800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_interrupts_IDX_0 43
#define DT_N_S_soc_S_timers_40001800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40001800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40001800_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40001800_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40001800_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40001800_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40001800_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40001800_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40001800_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40001800_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40001800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40001800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40001800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40001800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40001800/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40001800_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE\dts\bindings\counter\st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40001800_S_counter_PATH "/soc/timers@40001800/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40001800_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40001800_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40001800_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40001800_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40001800) identifier: */
#define DT_N_S_soc_S_timers_40001800_S_counter_PARENT DT_N_S_soc_S_timers_40001800

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40001800_S_counter_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40001800_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40001800_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40001800_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001800_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40001800) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40001800_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40001800_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40001800_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40001800_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001800_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001800_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40001800_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40001800_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001800_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001800_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40001800_S_counter_HASH fwQklgV179p_6HslAjdqF1c8jjC2BF4aua0ZbByE3PE

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40001800_S_counter_ORD 158
#define DT_N_S_soc_S_timers_40001800_S_counter_ORD_STR_SORTABLE 00158

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40001800_S_counter_REQUIRES_ORDS \
	157, /* /soc/timers@40001800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40001800_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40001800_S_counter_EXISTS 1
#define DT_N_INST_11_st_stm32_counter DT_N_S_soc_S_timers_40001800_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40001800_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40001800_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40001800_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001800_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001800_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40001800_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40001800_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40001800_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40001800_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40001800_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40001800_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40001800_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40001800_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40001800_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40001800_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40001800_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40001800_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40001800_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40001800_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40001800/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40001800_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40001800_S_pwm_PATH "/soc/timers@40001800/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40001800_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40001800_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40001800_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40001800_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40001800) identifier: */
#define DT_N_S_soc_S_timers_40001800_S_pwm_PARENT DT_N_S_soc_S_timers_40001800

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40001800_S_pwm_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40001800_S_pwm_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40001800_S_pwm_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40001800_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001800_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40001800) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40001800_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40001800_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40001800_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40001800_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001800_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001800_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40001800_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40001800_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001800_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001800_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40001800_S_pwm_HASH K6wIUvCEy1gKgAak61GnZ_6WjWnijyfqkSvLs81dD80

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40001800_S_pwm_ORD 159
#define DT_N_S_soc_S_timers_40001800_S_pwm_ORD_STR_SORTABLE 00159

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40001800_S_pwm_REQUIRES_ORDS \
	157, /* /soc/timers@40001800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40001800_S_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40001800_S_pwm_EXISTS 1
#define DT_N_INST_9_st_stm32_pwm DT_N_S_soc_S_timers_40001800_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40001800_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40001800_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40001800_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001800_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001800_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40001800_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40001800_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40001800_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40001800_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40001800_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40001800_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40001800_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40001800_S_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40001800_S_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status "disabled"
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40001800_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40001c00
 *
 * Node identifier: DT_N_S_soc_S_timers_40001c00
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE\dts\bindings\timer\st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40001c00_PATH "/soc/timers@40001c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40001c00_FULL_NAME "timers@40001c00"
#define DT_N_S_soc_S_timers_40001c00_FULL_NAME_UNQUOTED timers@40001c00
#define DT_N_S_soc_S_timers_40001c00_FULL_NAME_TOKEN timers_40001c00
#define DT_N_S_soc_S_timers_40001c00_FULL_NAME_UPPER_TOKEN TIMERS_40001C00

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40001c00_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40001c00_CHILD_IDX 41

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40001c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40001c00_FOREACH_NODELABEL(fn) fn(timers13)
#define DT_N_S_soc_S_timers_40001c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers13, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40001c00_CHILD_NUM 2
#define DT_N_S_soc_S_timers_40001c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40001c00_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40001c00_S_pwm) fn(DT_N_S_soc_S_timers_40001c00_S_counter)
#define DT_N_S_soc_S_timers_40001c00_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001c00_S_counter)
#define DT_N_S_soc_S_timers_40001c00_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001c00_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001c00_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40001c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40001c00_HASH C10pHSqK_DBrhy8hrLH60y9fcj7aeZfIUJONPe1VrQs

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40001c00_ORD 160
#define DT_N_S_soc_S_timers_40001c00_ORD_STR_SORTABLE 00160

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40001c00_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40001c00_SUPPORTS_ORDS \
	161, /* /soc/timers@40001c00/counter */ \
	162, /* /soc/timers@40001c00/pwm */
#define DT_N_NODELABEL_DT_N_S_soc_S_timers_40001c00_IDX_0_C_TOKEN timers13

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40001c00_EXISTS 1
#define DT_N_INST_12_st_stm32_timers DT_N_S_soc_S_timers_40001c00
#define DT_N_NODELABEL_timers13      DT_N_S_soc_S_timers_40001c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40001c00_REG_NUM 1
#define DT_N_S_soc_S_timers_40001c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_REG_IDX_0_VAL_ADDRESS 1073748992 /* 0x40001c00 */
#define DT_N_S_soc_S_timers_40001c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40001c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40001c00, 0)
#define DT_N_S_soc_S_timers_40001c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, 0)
#define DT_N_S_soc_S_timers_40001c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40001c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40001c00_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40001c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_IRQ_IDX_0_VAL_irq 44
#define DT_N_S_soc_S_timers_40001c00_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40001c00_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40001c00_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40001c00_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40001c00_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40001c00_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40001c00_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40001c00_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40001c00_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40001c00_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40001c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40001c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40001c00_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40001c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40001c00_P_reg {1073748992 /* 0x40001c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40001c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_reg_IDX_0 1073748992
#define DT_N_S_soc_S_timers_40001c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40001c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_VAL_bits 128
#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40001c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40001c00, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001c00, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_1_VAL_bus 21
#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40001c00, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40001c00, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001c00, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40001c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40001c00, clocks, 1)
#define DT_N_S_soc_S_timers_40001c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001c00, clocks, 1)
#define DT_N_S_soc_S_timers_40001c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40001c00, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001c00, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40001c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_timers_40001c00_P_resets_IDX_0_VAL_id 1031
#define DT_N_S_soc_S_timers_40001c00_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40001c00, resets, 0, id)
#define DT_N_S_soc_S_timers_40001c00_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, resets, 0, id)
#define DT_N_S_soc_S_timers_40001c00_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40001c00_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00, resets, 0)
#define DT_N_S_soc_S_timers_40001c00_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, resets, 0)
#define DT_N_S_soc_S_timers_40001c00_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40001c00_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40001c00_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_st_countermode 0
#define DT_N_S_soc_S_timers_40001c00_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40001c00_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40001c00_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40001c00_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40001c00_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40001c00_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40001c00_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40001c00_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40001c00_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40001c00_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40001c00_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_st_slavemode "disabled"
#define DT_N_S_soc_S_timers_40001c00_P_st_slavemode_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40001c00_P_st_slavemode_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40001c00_P_st_slavemode_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40001c00_P_st_slavemode_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40001c00_P_st_slavemode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_st_slavemode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40001c00_P_st_slavemode_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_st_slavemode_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_st_slavemode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40001c00_P_st_slavemode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40001c00_P_st_slavemode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_P_st_slavemode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_P_st_slavemode_LEN 1
#define DT_N_S_soc_S_timers_40001c00_P_st_slavemode_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_st_trigger_selection "ITR0"
#define DT_N_S_soc_S_timers_40001c00_P_st_trigger_selection_STRING_UNQUOTED ITR0
#define DT_N_S_soc_S_timers_40001c00_P_st_trigger_selection_STRING_TOKEN ITR0
#define DT_N_S_soc_S_timers_40001c00_P_st_trigger_selection_STRING_UPPER_TOKEN ITR0
#define DT_N_S_soc_S_timers_40001c00_P_st_trigger_selection_IDX_0 "ITR0"
#define DT_N_S_soc_S_timers_40001c00_P_st_trigger_selection_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_st_trigger_selection_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40001c00_P_st_trigger_selection_IDX_0_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_st_trigger_selection_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_st_trigger_selection_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40001c00_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40001c00_P_st_trigger_selection_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_P_st_trigger_selection_LEN 1
#define DT_N_S_soc_S_timers_40001c00_P_st_trigger_selection_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_status "disabled"
#define DT_N_S_soc_S_timers_40001c00_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40001c00_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40001c00_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40001c00_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40001c00_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40001c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00, status, 0)
#define DT_N_S_soc_S_timers_40001c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, status, 0)
#define DT_N_S_soc_S_timers_40001c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_P_status_LEN 1
#define DT_N_S_soc_S_timers_40001c00_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40001c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40001c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40001c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40001c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40001c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00, compatible, 0)
#define DT_N_S_soc_S_timers_40001c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, compatible, 0)
#define DT_N_S_soc_S_timers_40001c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40001c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_interrupts {44 /* 0x2c */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40001c00_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_interrupts_IDX_0 44
#define DT_N_S_soc_S_timers_40001c00_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40001c00_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40001c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40001c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40001c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40001c00_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40001c00/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40001c00_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE\dts\bindings\counter\st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40001c00_S_counter_PATH "/soc/timers@40001c00/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40001c00_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40001c00_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40001c00_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40001c00_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40001c00) identifier: */
#define DT_N_S_soc_S_timers_40001c00_S_counter_PARENT DT_N_S_soc_S_timers_40001c00

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40001c00_S_counter_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40001c00_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40001c00_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40001c00_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001c00_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40001c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40001c00_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40001c00_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40001c00_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40001c00_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001c00_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001c00_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40001c00_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40001c00_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001c00_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001c00_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40001c00_S_counter_HASH 9d8shZK9BRqoW9USlHmfnTMZSMrS4V_cs1TIO8Lq_48

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40001c00_S_counter_ORD 161
#define DT_N_S_soc_S_timers_40001c00_S_counter_ORD_STR_SORTABLE 00161

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40001c00_S_counter_REQUIRES_ORDS \
	160, /* /soc/timers@40001c00 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40001c00_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40001c00_S_counter_EXISTS 1
#define DT_N_INST_12_st_stm32_counter DT_N_S_soc_S_timers_40001c00_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40001c00_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40001c00_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40001c00_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001c00_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001c00_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40001c00_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40001c00_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40001c00_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40001c00_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40001c00_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40001c00_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40001c00_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40001c00_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40001c00_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40001c00_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40001c00/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40001c00_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40001c00_S_pwm_PATH "/soc/timers@40001c00/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40001c00) identifier: */
#define DT_N_S_soc_S_timers_40001c00_S_pwm_PARENT DT_N_S_soc_S_timers_40001c00

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40001c00_S_pwm_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40001c00_S_pwm_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40001c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40001c00_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40001c00_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40001c00_S_pwm_HASH a7Cf86O7zDlEGiIaLzI_4ROzwp0EjjUcTtMDoWesoDc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40001c00_S_pwm_ORD 162
#define DT_N_S_soc_S_timers_40001c00_S_pwm_ORD_STR_SORTABLE 00162

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40001c00_S_pwm_REQUIRES_ORDS \
	160, /* /soc/timers@40001c00 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40001c00_S_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40001c00_S_pwm_EXISTS 1
#define DT_N_INST_10_st_stm32_pwm DT_N_S_soc_S_timers_40001c00_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40001c00_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40001c00_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40001c00_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40001c00_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40001c00_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40001c00_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40001c00_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40001c00_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40001c00_S_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40001c00_S_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status "disabled"
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40002000
 *
 * Node identifier: DT_N_S_soc_S_timers_40002000
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE\dts\bindings\timer\st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40002000_PATH "/soc/timers@40002000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40002000_FULL_NAME "timers@40002000"
#define DT_N_S_soc_S_timers_40002000_FULL_NAME_UNQUOTED timers@40002000
#define DT_N_S_soc_S_timers_40002000_FULL_NAME_TOKEN timers_40002000
#define DT_N_S_soc_S_timers_40002000_FULL_NAME_UPPER_TOKEN TIMERS_40002000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40002000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40002000_CHILD_IDX 42

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40002000_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40002000_FOREACH_NODELABEL(fn) fn(timers14)
#define DT_N_S_soc_S_timers_40002000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers14, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40002000_CHILD_NUM 2
#define DT_N_S_soc_S_timers_40002000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40002000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40002000_S_pwm) fn(DT_N_S_soc_S_timers_40002000_S_counter)
#define DT_N_S_soc_S_timers_40002000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40002000_S_counter)
#define DT_N_S_soc_S_timers_40002000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002000_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40002000_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40002000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40002000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40002000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40002000_HASH Bwr917V_KDoq_2_yT2ELAebGrj8EfjUgvAAGsUjSK2c

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40002000_ORD 163
#define DT_N_S_soc_S_timers_40002000_ORD_STR_SORTABLE 00163

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40002000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40002000_SUPPORTS_ORDS \
	164, /* /soc/timers@40002000/counter */ \
	165, /* /soc/timers@40002000/pwm */
#define DT_N_NODELABEL_DT_N_S_soc_S_timers_40002000_IDX_0_C_TOKEN timers14

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40002000_EXISTS 1
#define DT_N_INST_13_st_stm32_timers DT_N_S_soc_S_timers_40002000
#define DT_N_NODELABEL_timers14      DT_N_S_soc_S_timers_40002000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40002000_REG_NUM 1
#define DT_N_S_soc_S_timers_40002000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_REG_IDX_0_VAL_ADDRESS 1073750016 /* 0x40002000 */
#define DT_N_S_soc_S_timers_40002000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40002000_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40002000, 0)
#define DT_N_S_soc_S_timers_40002000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, 0)
#define DT_N_S_soc_S_timers_40002000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40002000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40002000_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40002000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_IRQ_IDX_0_VAL_irq 45
#define DT_N_S_soc_S_timers_40002000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40002000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40002000_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40002000_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40002000_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40002000_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40002000_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40002000_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40002000_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40002000_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40002000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40002000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40002000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40002000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40002000_P_reg {1073750016 /* 0x40002000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40002000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_reg_IDX_0 1073750016
#define DT_N_S_soc_S_timers_40002000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40002000_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_VAL_bus 64
#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_VAL_bits 256
#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40002000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40002000, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40002000, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_1_VAL_bus 21
#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40002000, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40002000, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40002000, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40002000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40002000, clocks, 1)
#define DT_N_S_soc_S_timers_40002000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40002000, clocks, 1)
#define DT_N_S_soc_S_timers_40002000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40002000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40002000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40002000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_timers_40002000_P_resets_IDX_0_VAL_id 1032
#define DT_N_S_soc_S_timers_40002000_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40002000, resets, 0, id)
#define DT_N_S_soc_S_timers_40002000_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, resets, 0, id)
#define DT_N_S_soc_S_timers_40002000_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40002000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000, resets, 0)
#define DT_N_S_soc_S_timers_40002000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, resets, 0)
#define DT_N_S_soc_S_timers_40002000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40002000_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40002000_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_st_countermode 0
#define DT_N_S_soc_S_timers_40002000_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40002000_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40002000_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40002000_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40002000_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40002000_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40002000_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40002000_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40002000_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40002000_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40002000_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_st_slavemode "disabled"
#define DT_N_S_soc_S_timers_40002000_P_st_slavemode_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40002000_P_st_slavemode_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40002000_P_st_slavemode_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40002000_P_st_slavemode_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40002000_P_st_slavemode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_st_slavemode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40002000_P_st_slavemode_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_st_slavemode_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_st_slavemode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40002000_P_st_slavemode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40002000_P_st_slavemode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_P_st_slavemode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_P_st_slavemode_LEN 1
#define DT_N_S_soc_S_timers_40002000_P_st_slavemode_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_st_trigger_selection "ITR0"
#define DT_N_S_soc_S_timers_40002000_P_st_trigger_selection_STRING_UNQUOTED ITR0
#define DT_N_S_soc_S_timers_40002000_P_st_trigger_selection_STRING_TOKEN ITR0
#define DT_N_S_soc_S_timers_40002000_P_st_trigger_selection_STRING_UPPER_TOKEN ITR0
#define DT_N_S_soc_S_timers_40002000_P_st_trigger_selection_IDX_0 "ITR0"
#define DT_N_S_soc_S_timers_40002000_P_st_trigger_selection_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_st_trigger_selection_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40002000_P_st_trigger_selection_IDX_0_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_st_trigger_selection_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_st_trigger_selection_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40002000_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40002000_P_st_trigger_selection_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_P_st_trigger_selection_LEN 1
#define DT_N_S_soc_S_timers_40002000_P_st_trigger_selection_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_status "disabled"
#define DT_N_S_soc_S_timers_40002000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40002000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40002000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40002000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40002000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40002000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000, status, 0)
#define DT_N_S_soc_S_timers_40002000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, status, 0)
#define DT_N_S_soc_S_timers_40002000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_P_status_LEN 1
#define DT_N_S_soc_S_timers_40002000_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40002000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40002000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40002000_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40002000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40002000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000, compatible, 0)
#define DT_N_S_soc_S_timers_40002000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, compatible, 0)
#define DT_N_S_soc_S_timers_40002000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40002000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_interrupts {45 /* 0x2d */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40002000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_interrupts_IDX_0 45
#define DT_N_S_soc_S_timers_40002000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40002000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40002000_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40002000_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40002000_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40002000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40002000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40002000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40002000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40002000_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40002000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40002000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40002000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40002000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40002000/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40002000_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE\dts\bindings\counter\st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40002000_S_counter_PATH "/soc/timers@40002000/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40002000_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40002000_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40002000_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40002000_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40002000) identifier: */
#define DT_N_S_soc_S_timers_40002000_S_counter_PARENT DT_N_S_soc_S_timers_40002000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40002000_S_counter_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40002000_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40002000_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40002000_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40002000_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40002000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40002000_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40002000_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40002000_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40002000_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40002000_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40002000_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40002000_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40002000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40002000_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40002000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40002000_S_counter_HASH zJvOaxLLjATz51CJNhv5ls0CmMiTKSdYQecKTBIOLLU

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40002000_S_counter_ORD 164
#define DT_N_S_soc_S_timers_40002000_S_counter_ORD_STR_SORTABLE 00164

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40002000_S_counter_REQUIRES_ORDS \
	163, /* /soc/timers@40002000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40002000_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40002000_S_counter_EXISTS 1
#define DT_N_INST_13_st_stm32_counter DT_N_S_soc_S_timers_40002000_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40002000_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40002000_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40002000_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40002000_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40002000_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40002000_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40002000_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40002000_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40002000_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40002000_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40002000_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40002000_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40002000_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40002000_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40002000_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40002000_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40002000_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40002000_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40002000_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40002000/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40002000_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40002000_S_pwm_PATH "/soc/timers@40002000/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40002000_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40002000_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40002000_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40002000_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40002000) identifier: */
#define DT_N_S_soc_S_timers_40002000_S_pwm_PARENT DT_N_S_soc_S_timers_40002000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40002000_S_pwm_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40002000_S_pwm_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40002000_S_pwm_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40002000_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40002000_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40002000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40002000_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40002000_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40002000_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40002000_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40002000_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40002000_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40002000_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40002000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40002000_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40002000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40002000_S_pwm_HASH c6um8v5jI9Kwk4onLqCxe9XQjuDnMLyybl6AyMLjikc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40002000_S_pwm_ORD 165
#define DT_N_S_soc_S_timers_40002000_S_pwm_ORD_STR_SORTABLE 00165

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40002000_S_pwm_REQUIRES_ORDS \
	163, /* /soc/timers@40002000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40002000_S_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40002000_S_pwm_EXISTS 1
#define DT_N_INST_11_st_stm32_pwm DT_N_S_soc_S_timers_40002000_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40002000_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40002000_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40002000_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40002000_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40002000_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40002000_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40002000_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40002000_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40002000_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40002000_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40002000_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40002000_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40002000_S_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40002000_S_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status "disabled"
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40002000_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40010000
 *
 * Node identifier: DT_N_S_soc_S_timers_40010000
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE\dts\bindings\timer\st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40010000_PATH "/soc/timers@40010000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40010000_FULL_NAME "timers@40010000"
#define DT_N_S_soc_S_timers_40010000_FULL_NAME_UNQUOTED timers@40010000
#define DT_N_S_soc_S_timers_40010000_FULL_NAME_TOKEN timers_40010000
#define DT_N_S_soc_S_timers_40010000_FULL_NAME_UPPER_TOKEN TIMERS_40010000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40010000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40010000_CHILD_IDX 16

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40010000_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40010000_FOREACH_NODELABEL(fn) fn(timers1)
#define DT_N_S_soc_S_timers_40010000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40010000_CHILD_NUM 3
#define DT_N_S_soc_S_timers_40010000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm) fn(DT_N_S_soc_S_timers_40010000_S_counter) fn(DT_N_S_soc_S_timers_40010000_S_qdec)
#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010000_S_counter) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010000_S_qdec)
#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010000_S_counter, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010000_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm)
#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm)
#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_timers_40010000_HASH wxcvRN_mA3ySgl7Qy6w43tAOklIzHZ0umwDnKMTErAk

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40010000_ORD 166
#define DT_N_S_soc_S_timers_40010000_ORD_STR_SORTABLE 00166

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40010000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40010000_SUPPORTS_ORDS \
	167, /* /soc/timers@40010000/counter */ \
	169, /* /soc/timers@40010000/pwm */ \
	170, /* /soc/timers@40010000/qdec */
#define DT_N_NODELABEL_DT_N_S_soc_S_timers_40010000_IDX_0_C_TOKEN timers1

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40010000_EXISTS 1
#define DT_N_INST_0_st_stm32_timers DT_N_S_soc_S_timers_40010000
#define DT_N_NODELABEL_timers1      DT_N_S_soc_S_timers_40010000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40010000_REG_NUM 1
#define DT_N_S_soc_S_timers_40010000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_REG_IDX_0_VAL_ADDRESS 1073807360 /* 0x40010000 */
#define DT_N_S_soc_S_timers_40010000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40010000_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40010000, 0)
#define DT_N_S_soc_S_timers_40010000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, 0)
#define DT_N_S_soc_S_timers_40010000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40010000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40010000_IRQ_NUM 4
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_VAL_irq 24
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_VAL_irq 25
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_VAL_irq 26
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_VAL_priority 0
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_VAL_irq 27
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_VAL_priority 0
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40010000_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_brk_VAL_irq DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_brk_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_brk_VAL_priority DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_brk_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_brk_CONTROLLER DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_up_VAL_irq DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_VAL_irq
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_up_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_up_VAL_priority DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_VAL_priority
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_up_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_up_CONTROLLER DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_CONTROLLER
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_trgcom_VAL_irq DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_VAL_irq
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_trgcom_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_trgcom_VAL_priority DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_VAL_priority
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_trgcom_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_trgcom_CONTROLLER DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_CONTROLLER
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_cc_VAL_irq DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_VAL_irq
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_cc_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_cc_VAL_priority DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_VAL_priority
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_cc_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_cc_CONTROLLER DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_CONTROLLER
#define DT_N_S_soc_S_timers_40010000_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40010000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40010000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40010000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40010000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40010000_P_reg {1073807360 /* 0x40010000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_0 1073807360
#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40010000_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bus 68
#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bits 1
#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40010000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40010000, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010000, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_1_VAL_bus 22
#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40010000, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40010000, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010000, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40010000, clocks, 1)
#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010000, clocks, 1)
#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40010000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40010000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_VAL_id 1152
#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40010000, resets, 0, id)
#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, resets, 0, id)
#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, resets, 0)
#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, resets, 0)
#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40010000_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_st_prescaler 10000
#define DT_N_S_soc_S_timers_40010000_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_st_countermode 0
#define DT_N_S_soc_S_timers_40010000_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40010000_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40010000_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40010000_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40010000_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40010000_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40010000_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40010000_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40010000_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40010000_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40010000_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_st_slavemode "disabled"
#define DT_N_S_soc_S_timers_40010000_P_st_slavemode_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40010000_P_st_slavemode_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40010000_P_st_slavemode_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40010000_P_st_slavemode_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40010000_P_st_slavemode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_st_slavemode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40010000_P_st_slavemode_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_st_slavemode_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_st_slavemode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40010000_P_st_slavemode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40010000_P_st_slavemode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_P_st_slavemode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_P_st_slavemode_LEN 1
#define DT_N_S_soc_S_timers_40010000_P_st_slavemode_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_st_trigger_selection "ITR0"
#define DT_N_S_soc_S_timers_40010000_P_st_trigger_selection_STRING_UNQUOTED ITR0
#define DT_N_S_soc_S_timers_40010000_P_st_trigger_selection_STRING_TOKEN ITR0
#define DT_N_S_soc_S_timers_40010000_P_st_trigger_selection_STRING_UPPER_TOKEN ITR0
#define DT_N_S_soc_S_timers_40010000_P_st_trigger_selection_IDX_0 "ITR0"
#define DT_N_S_soc_S_timers_40010000_P_st_trigger_selection_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_st_trigger_selection_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40010000_P_st_trigger_selection_IDX_0_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_st_trigger_selection_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_st_trigger_selection_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40010000_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40010000_P_st_trigger_selection_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_P_st_trigger_selection_LEN 1
#define DT_N_S_soc_S_timers_40010000_P_st_trigger_selection_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_status "okay"
#define DT_N_S_soc_S_timers_40010000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_timers_40010000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_timers_40010000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_timers_40010000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_timers_40010000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40010000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, status, 0)
#define DT_N_S_soc_S_timers_40010000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, status, 0)
#define DT_N_S_soc_S_timers_40010000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_P_status_LEN 1
#define DT_N_S_soc_S_timers_40010000_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40010000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, compatible, 0)
#define DT_N_S_soc_S_timers_40010000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, compatible, 0)
#define DT_N_S_soc_S_timers_40010000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40010000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_interrupts {24 /* 0x18 */, 0 /* 0x0 */, 25 /* 0x19 */, 0 /* 0x0 */, 26 /* 0x1a */, 0 /* 0x0 */, 27 /* 0x1b */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_0 24
#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_2 25
#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_4_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_4 26
#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_5_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_5 0
#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_6_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_6 27
#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_7_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_7 0
#define DT_N_S_soc_S_timers_40010000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names {"brk", "up", "trgcom", "cc"}
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0 "brk"
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0_STRING_UNQUOTED brk
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0_STRING_TOKEN brk
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN BRK
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1 "up"
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1_STRING_UNQUOTED up
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1_STRING_TOKEN up
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN UP
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2 "trgcom"
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2_STRING_UNQUOTED trgcom
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2_STRING_TOKEN trgcom
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN TRGCOM
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3 "cc"
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3_STRING_UNQUOTED cc
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3_STRING_TOKEN cc
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3_STRING_UPPER_TOKEN CC
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 0) \
	fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 1) \
	fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 2) \
	fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 3)
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 3)
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 3, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 3, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_LEN 4
#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40010000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40010000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40010000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40010000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40010000/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40010000_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE\dts\bindings\counter\st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40010000_S_counter_PATH "/soc/timers@40010000/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40010000_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40010000_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40010000_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40010000_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40010000) identifier: */
#define DT_N_S_soc_S_timers_40010000_S_counter_PARENT DT_N_S_soc_S_timers_40010000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40010000_S_counter_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40010000_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40010000_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40010000_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010000_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40010000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40010000_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40010000_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40010000_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40010000_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010000_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010000_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40010000_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40010000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010000_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40010000_S_counter_HASH GiZJQ2sfKJabcD1EaPYUADy7ZluQeCeiPlFK5cg8oYA

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40010000_S_counter_ORD 167
#define DT_N_S_soc_S_timers_40010000_S_counter_ORD_STR_SORTABLE 00167

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40010000_S_counter_REQUIRES_ORDS \
	166, /* /soc/timers@40010000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40010000_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40010000_S_counter_EXISTS 1
#define DT_N_INST_0_st_stm32_counter DT_N_S_soc_S_timers_40010000_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40010000_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40010000_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40010000_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010000_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010000_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40010000_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40010000_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40010000_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40010000_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40010000_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40010000_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40010000_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40010000_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40010000_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40010000_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40010000_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40010000_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40010000_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40010000_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40010000_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40010000_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40010000_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40010000_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40010000_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40010000_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40010000_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40010000_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40010000_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40010000_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40010000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40010000_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40010000_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40010000_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40010000_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40010000_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40010000_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@40020000/tim1_ch3_pe13
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_PATH "/soc/pin-controller@40020000/tim1_ch3_pe13"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FULL_NAME "tim1_ch3_pe13"
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FULL_NAME_UNQUOTED tim1_ch3_pe13
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FULL_NAME_TOKEN tim1_ch3_pe13
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FULL_NAME_UPPER_TOKEN TIM1_CH3_PE13

/* Node parent (/soc/pin-controller@40020000) identifier: */
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_PARENT DT_N_S_soc_S_pin_controller_40020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_CHILD_IDX 29

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FOREACH_NODELABEL(fn) fn(tim1_ch3_pe13)
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FOREACH_NODELABEL_VARGS(fn, ...) fn(tim1_ch3_pe13, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_HASH kUzAit9AeaWML_MifdXvFXhiC_yU8Jh8Fj6La3frs04

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_ORD 168
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_ORD_STR_SORTABLE 00168

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_REQUIRES_ORDS \
	10, /* /soc/pin-controller@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_SUPPORTS_ORDS \
	169, /* /soc/timers@40010000/pwm */
#define DT_N_NODELABEL_DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_IDX_0_C_TOKEN tim1_ch3_pe13

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_EXISTS 1
#define DT_N_NODELABEL_tim1_ch3_pe13 DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_pinmux 2465
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_output_low 0
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_output_high 0
#define DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/timers@40010000/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40010000_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40010000_S_pwm_PATH "/soc/timers@40010000/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40010000_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40010000_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40010000_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40010000_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40010000) identifier: */
#define DT_N_S_soc_S_timers_40010000_S_pwm_PARENT DT_N_S_soc_S_timers_40010000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40010000_S_pwm_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40010000_S_pwm_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_NODELABEL(fn) fn(pwm1)
#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40010000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40010000_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40010000_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40010000_S_pwm_HASH Z55Ao8vxhtP2i2tfz7SNLkdCnBJdzyWWXJ_lALG31Pk

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40010000_S_pwm_ORD 169
#define DT_N_S_soc_S_timers_40010000_S_pwm_ORD_STR_SORTABLE 00169

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40010000_S_pwm_REQUIRES_ORDS \
	166, /* /soc/timers@40010000 */ \
	168, /* /soc/pin-controller@40020000/tim1_ch3_pe13 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40010000_S_pwm_SUPPORTS_ORDS /* nothing */
#define DT_N_NODELABEL_DT_N_S_soc_S_timers_40010000_S_pwm_IDX_0_C_TOKEN pwm1

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40010000_S_pwm_EXISTS 1
#define DT_N_INST_0_st_stm32_pwm DT_N_S_soc_S_timers_40010000_S_pwm
#define DT_N_NODELABEL_pwm1      DT_N_S_soc_S_timers_40010000_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40010000_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40010000_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40010000_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40010000_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40010000_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40010000_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40010000_S_pwm_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40010000_S_pwm_PINCTRL_NUM 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_timers_40010000_S_pwm_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_timers_40010000_S_pwm_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_timers_40010000_S_pwm_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_0, 0)
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_0, 0)
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_names, 0)
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_names, 0)
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status "okay"
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40010000_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40010000/qdec
 *
 * Node identifier: DT_N_S_soc_S_timers_40010000_S_qdec
 *
 * Binding (compatible = st,stm32-qdec):
 *   $ZEPHYR_BASE\dts\bindings\sensor\st,stm32-qdec.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40010000_S_qdec_PATH "/soc/timers@40010000/qdec"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40010000_S_qdec_FULL_NAME "qdec"
#define DT_N_S_soc_S_timers_40010000_S_qdec_FULL_NAME_UNQUOTED qdec
#define DT_N_S_soc_S_timers_40010000_S_qdec_FULL_NAME_TOKEN qdec
#define DT_N_S_soc_S_timers_40010000_S_qdec_FULL_NAME_UPPER_TOKEN QDEC

/* Node parent (/soc/timers@40010000) identifier: */
#define DT_N_S_soc_S_timers_40010000_S_qdec_PARENT DT_N_S_soc_S_timers_40010000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40010000_S_qdec_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40010000_S_qdec_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40010000_S_qdec_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40010000_S_qdec_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010000_S_qdec_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40010000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40010000_S_qdec_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40010000_S_qdec_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40010000_S_qdec_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40010000_S_qdec_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010000_S_qdec_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010000_S_qdec_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40010000_S_qdec_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40010000_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010000_S_qdec_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010000_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40010000_S_qdec_HASH nimxSBHzM3GBta7zp_OI6YuwMlUlErQBlbeggPys5UI

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40010000_S_qdec_ORD 170
#define DT_N_S_soc_S_timers_40010000_S_qdec_ORD_STR_SORTABLE 00170

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40010000_S_qdec_REQUIRES_ORDS \
	166, /* /soc/timers@40010000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40010000_S_qdec_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40010000_S_qdec_EXISTS 1
#define DT_N_INST_0_st_stm32_qdec DT_N_S_soc_S_timers_40010000_S_qdec

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40010000_S_qdec_REG_NUM 0
#define DT_N_S_soc_S_timers_40010000_S_qdec_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40010000_S_qdec_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010000_S_qdec_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010000_S_qdec_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40010000_S_qdec_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40010000_S_qdec_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40010000_S_qdec_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40010000_S_qdec_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40010000_S_qdec_COMPAT_MATCHES_st_stm32_qdec 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40010000_S_qdec_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_COMPAT_MODEL_IDX_0 "stm32-qdec"
#define DT_N_S_soc_S_timers_40010000_S_qdec_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40010000_S_qdec_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_st_encoder_mode 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_st_encoder_mode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_st_encoder_mode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_st_encoder_mode_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_st_encoder_mode_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_st_encoder_mode_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_st_input_polarity_inverted 0
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_st_input_polarity_inverted_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_st_input_filter_level 0
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_st_input_filter_level_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_status "disabled"
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_status_LEN 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_compatible {"st,stm32-qdec"}
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_compatible_IDX_0 "st,stm32-qdec"
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-qdec
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_compatible_IDX_0_STRING_TOKEN st_stm32_qdec
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_QDEC
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40010000_S_qdec_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40010400
 *
 * Node identifier: DT_N_S_soc_S_timers_40010400
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE\dts\bindings\timer\st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40010400_PATH "/soc/timers@40010400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40010400_FULL_NAME "timers@40010400"
#define DT_N_S_soc_S_timers_40010400_FULL_NAME_UNQUOTED timers@40010400
#define DT_N_S_soc_S_timers_40010400_FULL_NAME_TOKEN timers_40010400
#define DT_N_S_soc_S_timers_40010400_FULL_NAME_UPPER_TOKEN TIMERS_40010400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40010400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40010400_CHILD_IDX 39

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40010400_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40010400_FOREACH_NODELABEL(fn) fn(timers8)
#define DT_N_S_soc_S_timers_40010400_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers8, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40010400_CHILD_NUM 3
#define DT_N_S_soc_S_timers_40010400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40010400_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40010400_S_pwm) fn(DT_N_S_soc_S_timers_40010400_S_counter) fn(DT_N_S_soc_S_timers_40010400_S_qdec)
#define DT_N_S_soc_S_timers_40010400_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010400_S_counter) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010400_S_qdec)
#define DT_N_S_soc_S_timers_40010400_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010400_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010400_S_counter, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010400_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40010400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40010400_HASH NPzXzIr4jFBRLlwwLLrw1OQABEA_j6hU6F_PLAZ5J4U

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40010400_ORD 171
#define DT_N_S_soc_S_timers_40010400_ORD_STR_SORTABLE 00171

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40010400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40010400_SUPPORTS_ORDS \
	172, /* /soc/timers@40010400/counter */ \
	173, /* /soc/timers@40010400/pwm */ \
	174, /* /soc/timers@40010400/qdec */
#define DT_N_NODELABEL_DT_N_S_soc_S_timers_40010400_IDX_0_C_TOKEN timers8

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40010400_EXISTS 1
#define DT_N_INST_10_st_stm32_timers DT_N_S_soc_S_timers_40010400
#define DT_N_NODELABEL_timers8       DT_N_S_soc_S_timers_40010400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40010400_REG_NUM 1
#define DT_N_S_soc_S_timers_40010400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_REG_IDX_0_VAL_ADDRESS 1073808384 /* 0x40010400 */
#define DT_N_S_soc_S_timers_40010400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40010400_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40010400, 0)
#define DT_N_S_soc_S_timers_40010400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400, 0)
#define DT_N_S_soc_S_timers_40010400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40010400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40010400_IRQ_NUM 4
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_0_VAL_irq 43
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_1_VAL_irq 44
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_2_VAL_irq 45
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_2_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_2_VAL_priority 0
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_2_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_2_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_3_VAL_irq 46
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_3_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_3_VAL_priority 0
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_3_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_IDX_3_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40010400_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_brk_VAL_irq DT_N_S_soc_S_timers_40010400_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_brk_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_brk_VAL_priority DT_N_S_soc_S_timers_40010400_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_brk_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_brk_CONTROLLER DT_N_S_soc_S_timers_40010400_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_up_VAL_irq DT_N_S_soc_S_timers_40010400_IRQ_IDX_1_VAL_irq
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_up_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_up_VAL_priority DT_N_S_soc_S_timers_40010400_IRQ_IDX_1_VAL_priority
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_up_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_up_CONTROLLER DT_N_S_soc_S_timers_40010400_IRQ_IDX_1_CONTROLLER
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_trgcom_VAL_irq DT_N_S_soc_S_timers_40010400_IRQ_IDX_2_VAL_irq
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_trgcom_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_trgcom_VAL_priority DT_N_S_soc_S_timers_40010400_IRQ_IDX_2_VAL_priority
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_trgcom_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_trgcom_CONTROLLER DT_N_S_soc_S_timers_40010400_IRQ_IDX_2_CONTROLLER
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_cc_VAL_irq DT_N_S_soc_S_timers_40010400_IRQ_IDX_3_VAL_irq
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_cc_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_cc_VAL_priority DT_N_S_soc_S_timers_40010400_IRQ_IDX_3_VAL_priority
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_cc_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_IRQ_NAME_cc_CONTROLLER DT_N_S_soc_S_timers_40010400_IRQ_IDX_3_CONTROLLER
#define DT_N_S_soc_S_timers_40010400_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40010400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40010400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40010400_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40010400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40010400_P_reg {1073808384 /* 0x40010400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40010400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_reg_IDX_0 1073808384
#define DT_N_S_soc_S_timers_40010400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40010400_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_VAL_bus 68
#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_VAL_bits 2
#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40010400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40010400, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010400, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_1_VAL_bus 22
#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40010400, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40010400, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010400, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40010400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40010400, clocks, 1)
#define DT_N_S_soc_S_timers_40010400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010400, clocks, 1)
#define DT_N_S_soc_S_timers_40010400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40010400, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010400, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40010400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_timers_40010400_P_resets_IDX_0_VAL_id 1153
#define DT_N_S_soc_S_timers_40010400_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40010400, resets, 0, id)
#define DT_N_S_soc_S_timers_40010400_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400, resets, 0, id)
#define DT_N_S_soc_S_timers_40010400_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40010400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400, resets, 0)
#define DT_N_S_soc_S_timers_40010400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400, resets, 0)
#define DT_N_S_soc_S_timers_40010400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40010400_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40010400_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_st_countermode 0
#define DT_N_S_soc_S_timers_40010400_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40010400_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40010400_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40010400_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40010400_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40010400_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40010400_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40010400_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40010400_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40010400_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40010400_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_st_slavemode "disabled"
#define DT_N_S_soc_S_timers_40010400_P_st_slavemode_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40010400_P_st_slavemode_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40010400_P_st_slavemode_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40010400_P_st_slavemode_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40010400_P_st_slavemode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_st_slavemode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40010400_P_st_slavemode_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_st_slavemode_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_st_slavemode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40010400_P_st_slavemode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40010400_P_st_slavemode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_P_st_slavemode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_P_st_slavemode_LEN 1
#define DT_N_S_soc_S_timers_40010400_P_st_slavemode_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_st_trigger_selection "ITR0"
#define DT_N_S_soc_S_timers_40010400_P_st_trigger_selection_STRING_UNQUOTED ITR0
#define DT_N_S_soc_S_timers_40010400_P_st_trigger_selection_STRING_TOKEN ITR0
#define DT_N_S_soc_S_timers_40010400_P_st_trigger_selection_STRING_UPPER_TOKEN ITR0
#define DT_N_S_soc_S_timers_40010400_P_st_trigger_selection_IDX_0 "ITR0"
#define DT_N_S_soc_S_timers_40010400_P_st_trigger_selection_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_st_trigger_selection_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40010400_P_st_trigger_selection_IDX_0_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_st_trigger_selection_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_st_trigger_selection_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40010400_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40010400_P_st_trigger_selection_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_P_st_trigger_selection_LEN 1
#define DT_N_S_soc_S_timers_40010400_P_st_trigger_selection_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_status "disabled"
#define DT_N_S_soc_S_timers_40010400_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40010400_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40010400_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40010400_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40010400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40010400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400, status, 0)
#define DT_N_S_soc_S_timers_40010400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400, status, 0)
#define DT_N_S_soc_S_timers_40010400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_P_status_LEN 1
#define DT_N_S_soc_S_timers_40010400_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40010400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40010400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40010400_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40010400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40010400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400, compatible, 0)
#define DT_N_S_soc_S_timers_40010400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400, compatible, 0)
#define DT_N_S_soc_S_timers_40010400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40010400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_interrupts {43 /* 0x2b */, 0 /* 0x0 */, 44 /* 0x2c */, 0 /* 0x0 */, 45 /* 0x2d */, 0 /* 0x0 */, 46 /* 0x2e */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_0 43
#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_2 44
#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_4_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_4 45
#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_5_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_5 0
#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_6_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_6 46
#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_7_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_7 0
#define DT_N_S_soc_S_timers_40010400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names {"brk", "up", "trgcom", "cc"}
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_0 "brk"
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_0_STRING_UNQUOTED brk
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_0_STRING_TOKEN brk
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN BRK
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_1 "up"
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_1_STRING_UNQUOTED up
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_1_STRING_TOKEN up
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN UP
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_2_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_2 "trgcom"
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_2_STRING_UNQUOTED trgcom
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_2_STRING_TOKEN trgcom
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN TRGCOM
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_3_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_3 "cc"
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_3_STRING_UNQUOTED cc
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_3_STRING_TOKEN cc
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_3_STRING_UPPER_TOKEN CC
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 0) \
	fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 1) \
	fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 2) \
	fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 3)
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 3)
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 3, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 3, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_LEN 4
#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40010400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40010400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40010400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40010400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40010400/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40010400_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE\dts\bindings\counter\st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40010400_S_counter_PATH "/soc/timers@40010400/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40010400_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40010400_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40010400_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40010400_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40010400) identifier: */
#define DT_N_S_soc_S_timers_40010400_S_counter_PARENT DT_N_S_soc_S_timers_40010400

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40010400_S_counter_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40010400_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40010400_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40010400_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010400_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40010400) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40010400_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40010400_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40010400_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40010400_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010400_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010400_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40010400_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40010400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010400_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40010400_S_counter_HASH bp4sbGM3BadnUTcyoKw3RKnAyHOSUTfLSW4HxiUXtb8

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40010400_S_counter_ORD 172
#define DT_N_S_soc_S_timers_40010400_S_counter_ORD_STR_SORTABLE 00172

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40010400_S_counter_REQUIRES_ORDS \
	171, /* /soc/timers@40010400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40010400_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40010400_S_counter_EXISTS 1
#define DT_N_INST_10_st_stm32_counter DT_N_S_soc_S_timers_40010400_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40010400_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40010400_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40010400_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010400_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010400_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40010400_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40010400_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40010400_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40010400_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40010400_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40010400_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40010400_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40010400_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40010400_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40010400_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40010400_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40010400_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40010400_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40010400_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40010400_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40010400_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40010400_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40010400_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40010400_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40010400_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40010400_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40010400_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40010400_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40010400_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40010400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40010400_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40010400_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40010400_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40010400_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40010400_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40010400_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40010400/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40010400_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40010400_S_pwm_PATH "/soc/timers@40010400/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40010400_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40010400_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40010400_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40010400_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40010400) identifier: */
#define DT_N_S_soc_S_timers_40010400_S_pwm_PARENT DT_N_S_soc_S_timers_40010400

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40010400_S_pwm_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40010400_S_pwm_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40010400_S_pwm_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40010400_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010400_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40010400) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40010400_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40010400_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40010400_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40010400_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010400_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010400_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40010400_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40010400_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010400_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010400_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40010400_S_pwm_HASH eluEMoLASiCnBNpjXGb0gqHlmoRtkjfjgbVEXs4QAVA

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40010400_S_pwm_ORD 173
#define DT_N_S_soc_S_timers_40010400_S_pwm_ORD_STR_SORTABLE 00173

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40010400_S_pwm_REQUIRES_ORDS \
	171, /* /soc/timers@40010400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40010400_S_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40010400_S_pwm_EXISTS 1
#define DT_N_INST_8_st_stm32_pwm DT_N_S_soc_S_timers_40010400_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40010400_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40010400_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40010400_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010400_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010400_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40010400_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40010400_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40010400_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40010400_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40010400_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40010400_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40010400_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40010400_S_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40010400_S_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status "disabled"
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40010400_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40010400/qdec
 *
 * Node identifier: DT_N_S_soc_S_timers_40010400_S_qdec
 *
 * Binding (compatible = st,stm32-qdec):
 *   $ZEPHYR_BASE\dts\bindings\sensor\st,stm32-qdec.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40010400_S_qdec_PATH "/soc/timers@40010400/qdec"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40010400_S_qdec_FULL_NAME "qdec"
#define DT_N_S_soc_S_timers_40010400_S_qdec_FULL_NAME_UNQUOTED qdec
#define DT_N_S_soc_S_timers_40010400_S_qdec_FULL_NAME_TOKEN qdec
#define DT_N_S_soc_S_timers_40010400_S_qdec_FULL_NAME_UPPER_TOKEN QDEC

/* Node parent (/soc/timers@40010400) identifier: */
#define DT_N_S_soc_S_timers_40010400_S_qdec_PARENT DT_N_S_soc_S_timers_40010400

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40010400_S_qdec_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40010400_S_qdec_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40010400_S_qdec_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40010400_S_qdec_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010400_S_qdec_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40010400) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40010400_S_qdec_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40010400_S_qdec_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40010400_S_qdec_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40010400_S_qdec_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010400_S_qdec_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010400_S_qdec_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40010400_S_qdec_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40010400_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010400_S_qdec_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010400_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40010400_S_qdec_HASH 3zLXCgShqDV3aNUv4HvR6jjR1ufv4Fl3bmh3_tNLhWM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40010400_S_qdec_ORD 174
#define DT_N_S_soc_S_timers_40010400_S_qdec_ORD_STR_SORTABLE 00174

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40010400_S_qdec_REQUIRES_ORDS \
	171, /* /soc/timers@40010400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40010400_S_qdec_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40010400_S_qdec_EXISTS 1
#define DT_N_INST_5_st_stm32_qdec DT_N_S_soc_S_timers_40010400_S_qdec

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40010400_S_qdec_REG_NUM 0
#define DT_N_S_soc_S_timers_40010400_S_qdec_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40010400_S_qdec_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40010400_S_qdec_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40010400_S_qdec_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40010400_S_qdec_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40010400_S_qdec_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40010400_S_qdec_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40010400_S_qdec_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40010400_S_qdec_COMPAT_MATCHES_st_stm32_qdec 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40010400_S_qdec_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_COMPAT_MODEL_IDX_0 "stm32-qdec"
#define DT_N_S_soc_S_timers_40010400_S_qdec_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40010400_S_qdec_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_st_encoder_mode 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_st_encoder_mode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_st_encoder_mode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_st_encoder_mode_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_st_encoder_mode_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_st_encoder_mode_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_st_input_polarity_inverted 0
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_st_input_polarity_inverted_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_st_input_filter_level 0
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_st_input_filter_level_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_status "disabled"
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_status_LEN 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_compatible {"st,stm32-qdec"}
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_compatible_IDX_0 "st,stm32-qdec"
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-qdec
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_compatible_IDX_0_STRING_TOKEN st_stm32_qdec
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_QDEC
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40010400_S_qdec_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40014000
 *
 * Node identifier: DT_N_S_soc_S_timers_40014000
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE\dts\bindings\timer\st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40014000_PATH "/soc/timers@40014000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40014000_FULL_NAME "timers@40014000"
#define DT_N_S_soc_S_timers_40014000_FULL_NAME_UNQUOTED timers@40014000
#define DT_N_S_soc_S_timers_40014000_FULL_NAME_TOKEN timers_40014000
#define DT_N_S_soc_S_timers_40014000_FULL_NAME_UPPER_TOKEN TIMERS_40014000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40014000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40014000_CHILD_IDX 21

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40014000_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40014000_FOREACH_NODELABEL(fn) fn(timers9)
#define DT_N_S_soc_S_timers_40014000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers9, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40014000_CHILD_NUM 2
#define DT_N_S_soc_S_timers_40014000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40014000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40014000_S_pwm) fn(DT_N_S_soc_S_timers_40014000_S_counter)
#define DT_N_S_soc_S_timers_40014000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014000_S_counter)
#define DT_N_S_soc_S_timers_40014000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014000_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40014000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40014000_HASH lq5p3vgPpp0Pc1e97jH3shzpysrGZocBMMy1grfenUs

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40014000_ORD 175
#define DT_N_S_soc_S_timers_40014000_ORD_STR_SORTABLE 00175

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40014000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40014000_SUPPORTS_ORDS \
	176, /* /soc/timers@40014000/counter */ \
	177, /* /soc/timers@40014000/pwm */
#define DT_N_NODELABEL_DT_N_S_soc_S_timers_40014000_IDX_0_C_TOKEN timers9

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40014000_EXISTS 1
#define DT_N_INST_5_st_stm32_timers DT_N_S_soc_S_timers_40014000
#define DT_N_NODELABEL_timers9      DT_N_S_soc_S_timers_40014000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40014000_REG_NUM 1
#define DT_N_S_soc_S_timers_40014000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_REG_IDX_0_VAL_ADDRESS 1073823744 /* 0x40014000 */
#define DT_N_S_soc_S_timers_40014000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40014000_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40014000, 0)
#define DT_N_S_soc_S_timers_40014000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, 0)
#define DT_N_S_soc_S_timers_40014000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40014000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40014000_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_VAL_irq 24
#define DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40014000_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40014000_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40014000_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40014000_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40014000_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40014000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40014000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40014000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40014000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40014000_P_reg {1073823744 /* 0x40014000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40014000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_reg_IDX_0 1073823744
#define DT_N_S_soc_S_timers_40014000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40014000_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_VAL_bus 68
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_VAL_bits 65536
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40014000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40014000, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014000, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_1_VAL_bus 22
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40014000, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40014000, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014000, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40014000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40014000, clocks, 1)
#define DT_N_S_soc_S_timers_40014000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014000, clocks, 1)
#define DT_N_S_soc_S_timers_40014000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40014000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40014000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_VAL_id 1168
#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40014000, resets, 0, id)
#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, resets, 0, id)
#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40014000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, resets, 0)
#define DT_N_S_soc_S_timers_40014000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, resets, 0)
#define DT_N_S_soc_S_timers_40014000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40014000_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40014000_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_countermode 0
#define DT_N_S_soc_S_timers_40014000_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40014000_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_slavemode "disabled"
#define DT_N_S_soc_S_timers_40014000_P_st_slavemode_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014000_P_st_slavemode_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014000_P_st_slavemode_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014000_P_st_slavemode_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014000_P_st_slavemode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_slavemode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40014000_P_st_slavemode_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_slavemode_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_slavemode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40014000_P_st_slavemode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40014000_P_st_slavemode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_st_slavemode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_st_slavemode_LEN 1
#define DT_N_S_soc_S_timers_40014000_P_st_slavemode_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_trigger_selection "ITR0"
#define DT_N_S_soc_S_timers_40014000_P_st_trigger_selection_STRING_UNQUOTED ITR0
#define DT_N_S_soc_S_timers_40014000_P_st_trigger_selection_STRING_TOKEN ITR0
#define DT_N_S_soc_S_timers_40014000_P_st_trigger_selection_STRING_UPPER_TOKEN ITR0
#define DT_N_S_soc_S_timers_40014000_P_st_trigger_selection_IDX_0 "ITR0"
#define DT_N_S_soc_S_timers_40014000_P_st_trigger_selection_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_trigger_selection_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40014000_P_st_trigger_selection_IDX_0_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_trigger_selection_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_trigger_selection_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40014000_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40014000_P_st_trigger_selection_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_st_trigger_selection_LEN 1
#define DT_N_S_soc_S_timers_40014000_P_st_trigger_selection_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_status "disabled"
#define DT_N_S_soc_S_timers_40014000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40014000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, status, 0)
#define DT_N_S_soc_S_timers_40014000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, status, 0)
#define DT_N_S_soc_S_timers_40014000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_status_LEN 1
#define DT_N_S_soc_S_timers_40014000_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40014000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40014000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40014000_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40014000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40014000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, compatible, 0)
#define DT_N_S_soc_S_timers_40014000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, compatible, 0)
#define DT_N_S_soc_S_timers_40014000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40014000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_interrupts {24 /* 0x18 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40014000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_interrupts_IDX_0 24
#define DT_N_S_soc_S_timers_40014000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40014000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40014000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40014000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40014000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40014000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40014000/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40014000_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE\dts\bindings\counter\st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40014000_S_counter_PATH "/soc/timers@40014000/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40014000_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40014000_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40014000_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40014000_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40014000) identifier: */
#define DT_N_S_soc_S_timers_40014000_S_counter_PARENT DT_N_S_soc_S_timers_40014000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40014000_S_counter_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40014000_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40014000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40014000_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40014000_S_counter_HASH HTxmpxrEMdGrjqKzwYEQ3Db8lHf9V4eSc5b5awosPW0

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40014000_S_counter_ORD 176
#define DT_N_S_soc_S_timers_40014000_S_counter_ORD_STR_SORTABLE 00176

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40014000_S_counter_REQUIRES_ORDS \
	175, /* /soc/timers@40014000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40014000_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40014000_S_counter_EXISTS 1
#define DT_N_INST_5_st_stm32_counter DT_N_S_soc_S_timers_40014000_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40014000_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014000_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40014000_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40014000_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40014000_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40014000_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40014000_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40014000_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40014000_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40014000_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40014000_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40014000_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40014000/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40014000_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_PATH "/soc/timers@40014000/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40014000_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40014000_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40014000_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40014000) identifier: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_PARENT DT_N_S_soc_S_timers_40014000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40014000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40014000_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_HASH kSLo0yu1rvkKjWd1KPNaOZTkLqT1fXRh8ItGZQcov88

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_ORD 177
#define DT_N_S_soc_S_timers_40014000_S_pwm_ORD_STR_SORTABLE 00177

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_REQUIRES_ORDS \
	175, /* /soc/timers@40014000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_EXISTS 1
#define DT_N_INST_5_st_stm32_pwm DT_N_S_soc_S_timers_40014000_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40014000_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40014000_S_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status "disabled"
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40014400
 *
 * Node identifier: DT_N_S_soc_S_timers_40014400
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE\dts\bindings\timer\st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40014400_PATH "/soc/timers@40014400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40014400_FULL_NAME "timers@40014400"
#define DT_N_S_soc_S_timers_40014400_FULL_NAME_UNQUOTED timers@40014400
#define DT_N_S_soc_S_timers_40014400_FULL_NAME_TOKEN timers_40014400
#define DT_N_S_soc_S_timers_40014400_FULL_NAME_UPPER_TOKEN TIMERS_40014400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40014400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40014400_CHILD_IDX 22

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40014400_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40014400_FOREACH_NODELABEL(fn) fn(timers10)
#define DT_N_S_soc_S_timers_40014400_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers10, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40014400_CHILD_NUM 2
#define DT_N_S_soc_S_timers_40014400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40014400_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40014400_S_pwm) fn(DT_N_S_soc_S_timers_40014400_S_counter)
#define DT_N_S_soc_S_timers_40014400_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014400_S_counter)
#define DT_N_S_soc_S_timers_40014400_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014400_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40014400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40014400_HASH LhbzUUvofdpe9RJBdWKw1tw8MqV4XObGHJe29iNM0Lc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40014400_ORD 178
#define DT_N_S_soc_S_timers_40014400_ORD_STR_SORTABLE 00178

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40014400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40014400_SUPPORTS_ORDS \
	179, /* /soc/timers@40014400/counter */ \
	180, /* /soc/timers@40014400/pwm */
#define DT_N_NODELABEL_DT_N_S_soc_S_timers_40014400_IDX_0_C_TOKEN timers10

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40014400_EXISTS 1
#define DT_N_INST_6_st_stm32_timers DT_N_S_soc_S_timers_40014400
#define DT_N_NODELABEL_timers10     DT_N_S_soc_S_timers_40014400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40014400_REG_NUM 1
#define DT_N_S_soc_S_timers_40014400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_REG_IDX_0_VAL_ADDRESS 1073824768 /* 0x40014400 */
#define DT_N_S_soc_S_timers_40014400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40014400_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40014400, 0)
#define DT_N_S_soc_S_timers_40014400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, 0)
#define DT_N_S_soc_S_timers_40014400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40014400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40014400_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_VAL_irq 25
#define DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40014400_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40014400_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40014400_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40014400_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40014400_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40014400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40014400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40014400_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40014400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40014400_P_reg {1073824768 /* 0x40014400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40014400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_reg_IDX_0 1073824768
#define DT_N_S_soc_S_timers_40014400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40014400_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_VAL_bus 68
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_VAL_bits 131072
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40014400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40014400, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014400, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_1_VAL_bus 22
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40014400, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40014400, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014400, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40014400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40014400, clocks, 1)
#define DT_N_S_soc_S_timers_40014400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014400, clocks, 1)
#define DT_N_S_soc_S_timers_40014400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40014400, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014400, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40014400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_VAL_id 1169
#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40014400, resets, 0, id)
#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, resets, 0, id)
#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40014400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, resets, 0)
#define DT_N_S_soc_S_timers_40014400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, resets, 0)
#define DT_N_S_soc_S_timers_40014400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40014400_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40014400_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_countermode 0
#define DT_N_S_soc_S_timers_40014400_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40014400_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_slavemode "disabled"
#define DT_N_S_soc_S_timers_40014400_P_st_slavemode_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014400_P_st_slavemode_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014400_P_st_slavemode_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014400_P_st_slavemode_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014400_P_st_slavemode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_slavemode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40014400_P_st_slavemode_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_slavemode_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_slavemode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40014400_P_st_slavemode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40014400_P_st_slavemode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_st_slavemode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_st_slavemode_LEN 1
#define DT_N_S_soc_S_timers_40014400_P_st_slavemode_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_trigger_selection "ITR0"
#define DT_N_S_soc_S_timers_40014400_P_st_trigger_selection_STRING_UNQUOTED ITR0
#define DT_N_S_soc_S_timers_40014400_P_st_trigger_selection_STRING_TOKEN ITR0
#define DT_N_S_soc_S_timers_40014400_P_st_trigger_selection_STRING_UPPER_TOKEN ITR0
#define DT_N_S_soc_S_timers_40014400_P_st_trigger_selection_IDX_0 "ITR0"
#define DT_N_S_soc_S_timers_40014400_P_st_trigger_selection_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_trigger_selection_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40014400_P_st_trigger_selection_IDX_0_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_trigger_selection_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_trigger_selection_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40014400_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40014400_P_st_trigger_selection_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_st_trigger_selection_LEN 1
#define DT_N_S_soc_S_timers_40014400_P_st_trigger_selection_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_status "disabled"
#define DT_N_S_soc_S_timers_40014400_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014400_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014400_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014400_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40014400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, status, 0)
#define DT_N_S_soc_S_timers_40014400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, status, 0)
#define DT_N_S_soc_S_timers_40014400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_status_LEN 1
#define DT_N_S_soc_S_timers_40014400_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40014400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40014400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40014400_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40014400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40014400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, compatible, 0)
#define DT_N_S_soc_S_timers_40014400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, compatible, 0)
#define DT_N_S_soc_S_timers_40014400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40014400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_interrupts {25 /* 0x19 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40014400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_interrupts_IDX_0 25
#define DT_N_S_soc_S_timers_40014400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40014400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40014400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40014400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40014400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40014400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40014400/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40014400_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE\dts\bindings\counter\st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40014400_S_counter_PATH "/soc/timers@40014400/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40014400_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40014400_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40014400_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40014400_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40014400) identifier: */
#define DT_N_S_soc_S_timers_40014400_S_counter_PARENT DT_N_S_soc_S_timers_40014400

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40014400_S_counter_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40014400_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40014400) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40014400_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40014400_S_counter_HASH p37X7wit0iPn8X9v8y4Gj2t07AN6oeaaeHeLb6OojSE

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40014400_S_counter_ORD 179
#define DT_N_S_soc_S_timers_40014400_S_counter_ORD_STR_SORTABLE 00179

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40014400_S_counter_REQUIRES_ORDS \
	178, /* /soc/timers@40014400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40014400_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40014400_S_counter_EXISTS 1
#define DT_N_INST_6_st_stm32_counter DT_N_S_soc_S_timers_40014400_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40014400_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014400_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40014400_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40014400_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40014400_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40014400_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40014400_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40014400_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40014400_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40014400_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40014400_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40014400_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40014400/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40014400_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_PATH "/soc/timers@40014400/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40014400_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40014400_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40014400_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40014400) identifier: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_PARENT DT_N_S_soc_S_timers_40014400

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40014400) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40014400_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_HASH qSncIfFrKmBeFCfySGntGi5dvRM62NXtfq0Z60Th_Tw

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_ORD 180
#define DT_N_S_soc_S_timers_40014400_S_pwm_ORD_STR_SORTABLE 00180

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_REQUIRES_ORDS \
	178, /* /soc/timers@40014400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_EXISTS 1
#define DT_N_INST_6_st_stm32_pwm DT_N_S_soc_S_timers_40014400_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40014400_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40014400_S_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status "disabled"
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40014800
 *
 * Node identifier: DT_N_S_soc_S_timers_40014800
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE\dts\bindings\timer\st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40014800_PATH "/soc/timers@40014800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40014800_FULL_NAME "timers@40014800"
#define DT_N_S_soc_S_timers_40014800_FULL_NAME_UNQUOTED timers@40014800
#define DT_N_S_soc_S_timers_40014800_FULL_NAME_TOKEN timers_40014800
#define DT_N_S_soc_S_timers_40014800_FULL_NAME_UPPER_TOKEN TIMERS_40014800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40014800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40014800_CHILD_IDX 23

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40014800_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40014800_FOREACH_NODELABEL(fn) fn(timers11)
#define DT_N_S_soc_S_timers_40014800_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers11, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40014800_CHILD_NUM 2
#define DT_N_S_soc_S_timers_40014800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40014800_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40014800_S_pwm) fn(DT_N_S_soc_S_timers_40014800_S_counter)
#define DT_N_S_soc_S_timers_40014800_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014800_S_counter)
#define DT_N_S_soc_S_timers_40014800_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014800_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40014800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40014800_HASH HFfK32JNDgTzZmhucfswXs63t4LSBAvBFi__WAnpexw

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40014800_ORD 181
#define DT_N_S_soc_S_timers_40014800_ORD_STR_SORTABLE 00181

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40014800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40023800 */ \
	63, /* /soc/rcc@40023800/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40014800_SUPPORTS_ORDS \
	182, /* /soc/timers@40014800/counter */ \
	183, /* /soc/timers@40014800/pwm */
#define DT_N_NODELABEL_DT_N_S_soc_S_timers_40014800_IDX_0_C_TOKEN timers11

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40014800_EXISTS 1
#define DT_N_INST_7_st_stm32_timers DT_N_S_soc_S_timers_40014800
#define DT_N_NODELABEL_timers11     DT_N_S_soc_S_timers_40014800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40014800_REG_NUM 1
#define DT_N_S_soc_S_timers_40014800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_REG_IDX_0_VAL_ADDRESS 1073825792 /* 0x40014800 */
#define DT_N_S_soc_S_timers_40014800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40014800_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40014800, 0)
#define DT_N_S_soc_S_timers_40014800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, 0)
#define DT_N_S_soc_S_timers_40014800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40014800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40014800_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_VAL_irq 26
#define DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40014800_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40014800_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40014800_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40014800_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40014800_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40014800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40014800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40014800_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40014800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40014800_P_reg {1073825792 /* 0x40014800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40014800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_reg_IDX_0 1073825792
#define DT_N_S_soc_S_timers_40014800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40014800_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_VAL_bus 68
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_VAL_bits 262144
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40014800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40014800, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014800, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40023800
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_1_VAL_bus 22
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40014800, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40014800, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014800, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40014800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40014800, clocks, 1)
#define DT_N_S_soc_S_timers_40014800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014800, clocks, 1)
#define DT_N_S_soc_S_timers_40014800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40014800, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014800, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40014800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40023800_S_reset_controller
#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_VAL_id 1170
#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40014800, resets, 0, id)
#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, resets, 0, id)
#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40014800_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, resets, 0)
#define DT_N_S_soc_S_timers_40014800_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, resets, 0)
#define DT_N_S_soc_S_timers_40014800_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40014800_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40014800_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_countermode 0
#define DT_N_S_soc_S_timers_40014800_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40014800_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_slavemode "disabled"
#define DT_N_S_soc_S_timers_40014800_P_st_slavemode_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014800_P_st_slavemode_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014800_P_st_slavemode_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014800_P_st_slavemode_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014800_P_st_slavemode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_slavemode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40014800_P_st_slavemode_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_slavemode_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_slavemode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40014800_P_st_slavemode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, st_slavemode, 0)
#define DT_N_S_soc_S_timers_40014800_P_st_slavemode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_st_slavemode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, st_slavemode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_st_slavemode_LEN 1
#define DT_N_S_soc_S_timers_40014800_P_st_slavemode_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_trigger_selection "ITR0"
#define DT_N_S_soc_S_timers_40014800_P_st_trigger_selection_STRING_UNQUOTED ITR0
#define DT_N_S_soc_S_timers_40014800_P_st_trigger_selection_STRING_TOKEN ITR0
#define DT_N_S_soc_S_timers_40014800_P_st_trigger_selection_STRING_UPPER_TOKEN ITR0
#define DT_N_S_soc_S_timers_40014800_P_st_trigger_selection_IDX_0 "ITR0"
#define DT_N_S_soc_S_timers_40014800_P_st_trigger_selection_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_trigger_selection_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40014800_P_st_trigger_selection_IDX_0_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_trigger_selection_ENUM_VAL_itr0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_trigger_selection_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40014800_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, st_trigger_selection, 0)
#define DT_N_S_soc_S_timers_40014800_P_st_trigger_selection_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_st_trigger_selection_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, st_trigger_selection, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_st_trigger_selection_LEN 1
#define DT_N_S_soc_S_timers_40014800_P_st_trigger_selection_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_status "disabled"
#define DT_N_S_soc_S_timers_40014800_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014800_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014800_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014800_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40014800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, status, 0)
#define DT_N_S_soc_S_timers_40014800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, status, 0)
#define DT_N_S_soc_S_timers_40014800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_status_LEN 1
#define DT_N_S_soc_S_timers_40014800_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40014800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40014800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40014800_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40014800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40014800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, compatible, 0)
#define DT_N_S_soc_S_timers_40014800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, compatible, 0)
#define DT_N_S_soc_S_timers_40014800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40014800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_interrupts {26 /* 0x1a */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40014800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_interrupts_IDX_0 26
#define DT_N_S_soc_S_timers_40014800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40014800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40014800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40014800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40014800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40014800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40014800/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40014800_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE\dts\bindings\counter\st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40014800_S_counter_PATH "/soc/timers@40014800/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40014800_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40014800_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40014800_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40014800_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40014800) identifier: */
#define DT_N_S_soc_S_timers_40014800_S_counter_PARENT DT_N_S_soc_S_timers_40014800

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40014800_S_counter_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40014800_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40014800) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40014800_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40014800_S_counter_HASH S6y2pTOmJHjQSdFjECAm7CIldgBp6UkB1xRx45LXe9E

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40014800_S_counter_ORD 182
#define DT_N_S_soc_S_timers_40014800_S_counter_ORD_STR_SORTABLE 00182

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40014800_S_counter_REQUIRES_ORDS \
	181, /* /soc/timers@40014800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40014800_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40014800_S_counter_EXISTS 1
#define DT_N_INST_7_st_stm32_counter DT_N_S_soc_S_timers_40014800_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40014800_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014800_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40014800_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40014800_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40014800_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40014800_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40014800_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40014800_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40014800_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40014800_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40014800_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40014800_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40014800/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40014800_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_PATH "/soc/timers@40014800/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40014800_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40014800_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40014800_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40014800) identifier: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_PARENT DT_N_S_soc_S_timers_40014800

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40014800) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40014800_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_HASH pP_vpmBmH6Uc99dxi1iL0vcGxl00Y6rTzAdbQLvVodY

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_ORD 183
#define DT_N_S_soc_S_timers_40014800_S_pwm_ORD_STR_SORTABLE 00183

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_REQUIRES_ORDS \
	181, /* /soc/timers@40014800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_EXISTS 1
#define DT_N_INST_7_st_stm32_pwm DT_N_S_soc_S_timers_40014800_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40014800_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40014800_S_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status "disabled"
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Chosen nodes
 */
#define DT_CHOSEN_zephyr_flash_controller              DT_N_S_soc_S_flash_controller_40023c00
#define DT_CHOSEN_zephyr_flash_controller_EXISTS       1
#define DT_CHOSEN_zephyr_system_timer_companion        DT_N_S_soc_S_rtc_40002800
#define DT_CHOSEN_zephyr_system_timer_companion_EXISTS 1
#define DT_CHOSEN_zephyr_entropy                       DT_N_S_soc_S_rng_50060800
#define DT_CHOSEN_zephyr_entropy_EXISTS                1
#define DT_CHOSEN_zephyr_console                       DT_N_S_soc_S_serial_40004800
#define DT_CHOSEN_zephyr_console_EXISTS                1
#define DT_CHOSEN_zephyr_shell_uart                    DT_N_S_soc_S_serial_40004800
#define DT_CHOSEN_zephyr_shell_uart_EXISTS             1
#define DT_CHOSEN_zephyr_sram                          DT_N_S_memory_20000000
#define DT_CHOSEN_zephyr_sram_EXISTS                   1
#define DT_CHOSEN_zephyr_flash                         DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000
#define DT_CHOSEN_zephyr_flash_EXISTS                  1
#define DT_CHOSEN_zephyr_dtcm                          DT_N_S_memory_10000000
#define DT_CHOSEN_zephyr_dtcm_EXISTS                   1
#define DT_CHOSEN_zephyr_code_partition                DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000
#define DT_CHOSEN_zephyr_code_partition_EXISTS         1

/* Macros for iterating over all nodes and enabled nodes */
#define DT_FOREACH_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_flash_controller_40023c00) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e) fn(DT_N_S_soc_S_rcc_40023800) fn(DT_N_S_soc_S_rcc_40023800_S_reset_controller) fn(DT_N_S_soc_S_interrupt_controller_40013c00) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800) fn(DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0) fn(DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5) fn(DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12) fn(DT_N_S_soc_S_watchdog_40003000) fn(DT_N_S_soc_S_watchdog_40002c00) fn(DT_N_S_soc_S_serial_40011000) fn(DT_N_S_soc_S_serial_40004400) fn(DT_N_S_soc_S_serial_40011400) fn(DT_N_S_soc_S_i2c_40005400) fn(DT_N_S_soc_S_i2c_40005800) fn(DT_N_S_soc_S_i2c_40005c00) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_usb_50000000) fn(DT_N_S_soc_S_timers_40010000) fn(DT_N_S_soc_S_timers_40010000_S_pwm) fn(DT_N_S_soc_S_timers_40010000_S_counter) fn(DT_N_S_soc_S_timers_40010000_S_qdec) fn(DT_N_S_soc_S_timers_40000000) fn(DT_N_S_soc_S_timers_40000000_S_pwm) fn(DT_N_S_soc_S_timers_40000000_S_counter) fn(DT_N_S_soc_S_timers_40000000_S_qdec) fn(DT_N_S_soc_S_timers_40000400) fn(DT_N_S_soc_S_timers_40000400_S_pwm) fn(DT_N_S_soc_S_timers_40000400_S_counter) fn(DT_N_S_soc_S_timers_40000400_S_qdec) fn(DT_N_S_soc_S_timers_40000800) fn(DT_N_S_soc_S_timers_40000800_S_pwm) fn(DT_N_S_soc_S_timers_40000800_S_counter) fn(DT_N_S_soc_S_timers_40000800_S_qdec) fn(DT_N_S_soc_S_timers_40000c00) fn(DT_N_S_soc_S_timers_40000c00_S_pwm) fn(DT_N_S_soc_S_timers_40000c00_S_counter) fn(DT_N_S_soc_S_timers_40000c00_S_qdec) fn(DT_N_S_soc_S_timers_40014000) fn(DT_N_S_soc_S_timers_40014000_S_pwm) fn(DT_N_S_soc_S_timers_40014000_S_counter) fn(DT_N_S_soc_S_timers_40014400) fn(DT_N_S_soc_S_timers_40014400_S_pwm) fn(DT_N_S_soc_S_timers_40014400_S_counter) fn(DT_N_S_soc_S_timers_40014800) fn(DT_N_S_soc_S_timers_40014800_S_pwm) fn(DT_N_S_soc_S_timers_40014800_S_counter) fn(DT_N_S_soc_S_rtc_40002800) fn(DT_N_S_soc_S_rtc_40002800_S_backup_regs) fn(DT_N_S_soc_S_adc_40012000) fn(DT_N_S_soc_S_dma_40026000) fn(DT_N_S_soc_S_dma_40026400) fn(DT_N_S_soc_S_sdmmc_40012c00) fn(DT_N_S_soc_S_spi_40003800) fn(DT_N_S_soc_S_spi_40003c00) fn(DT_N_S_soc_S_spi_40013400) fn(DT_N_S_soc_S_i2s_40003800) fn(DT_N_S_soc_S_i2s_40003c00) fn(DT_N_S_soc_S_serial_40004800) fn(DT_N_S_soc_S_serial_40004c00) fn(DT_N_S_soc_S_serial_40005000) fn(DT_N_S_soc_S_timers_40001000) fn(DT_N_S_soc_S_timers_40001000_S_counter) fn(DT_N_S_soc_S_timers_40001400) fn(DT_N_S_soc_S_timers_40001400_S_counter) fn(DT_N_S_soc_S_timers_40010400) fn(DT_N_S_soc_S_timers_40010400_S_pwm) fn(DT_N_S_soc_S_timers_40010400_S_counter) fn(DT_N_S_soc_S_timers_40010400_S_qdec) fn(DT_N_S_soc_S_timers_40001800) fn(DT_N_S_soc_S_timers_40001800_S_pwm) fn(DT_N_S_soc_S_timers_40001800_S_counter) fn(DT_N_S_soc_S_timers_40001c00) fn(DT_N_S_soc_S_timers_40001c00_S_pwm) fn(DT_N_S_soc_S_timers_40001c00_S_counter) fn(DT_N_S_soc_S_timers_40002000) fn(DT_N_S_soc_S_timers_40002000_S_pwm) fn(DT_N_S_soc_S_timers_40002000_S_counter) fn(DT_N_S_soc_S_usb_40040000) fn(DT_N_S_soc_S_can_40006400) fn(DT_N_S_soc_S_can_40006800) fn(DT_N_S_soc_S_rng_50060800) fn(DT_N_S_soc_S_memory_40024000) fn(DT_N_S_soc_S_adc_40012100) fn(DT_N_S_soc_S_adc_40012200) fn(DT_N_S_soc_S_dac_40007400) fn(DT_N_S_soc_S_ethernet_40028000) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0) fn(DT_N_S_soc_S_serial_40007800) fn(DT_N_S_soc_S_serial_40007c00) fn(DT_N_S_soc_S_spi_40015000) fn(DT_N_S_soc_S_spi_40015400) fn(DT_N_S_soc_S_memory_controller_a0000000) fn(DT_N_S_soc_S_memory_controller_a0000000_S_sdram) fn(DT_N_S_soc_S_sai1_40015800) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24) fn(DT_N_S_soc_S_display_controller_40016800) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_power_states) fn(DT_N_S_cpus_S_power_states_S_stop) fn(DT_N_S_memory_20000000) fn(DT_N_S_clocks) fn(DT_N_S_clocks_S_clk_hse) fn(DT_N_S_clocks_S_clk_hsi) fn(DT_N_S_clocks_S_clk_lse) fn(DT_N_S_clocks_S_clk_lsi) fn(DT_N_S_clocks_S_pll) fn(DT_N_S_clocks_S_plli2s) fn(DT_N_S_clocks_S_pllsai) fn(DT_N_S_mcos) fn(DT_N_S_mcos_S_mco1) fn(DT_N_S_mcos_S_mco2) fn(DT_N_S_power_40007000) fn(DT_N_S_power_40007000_S_wkup_pin_1) fn(DT_N_S_dietemp) fn(DT_N_S_vref) fn(DT_N_S_vbat) fn(DT_N_S_otgfs_phy) fn(DT_N_S_smbus1) fn(DT_N_S_smbus2) fn(DT_N_S_smbus3) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_memory_10000000) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3) fn(DT_N_S_gpio_keys) fn(DT_N_S_gpio_keys_S_button)
#define DT_FOREACH_OKAY_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_flash_controller_40023c00) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e) fn(DT_N_S_soc_S_rcc_40023800) fn(DT_N_S_soc_S_rcc_40023800_S_reset_controller) fn(DT_N_S_soc_S_interrupt_controller_40013c00) fn(DT_N_S_soc_S_pin_controller_40020000) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800) fn(DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0) fn(DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5) fn(DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12) fn(DT_N_S_soc_S_watchdog_40003000) fn(DT_N_S_soc_S_serial_40011400) fn(DT_N_S_soc_S_i2c_40005400) fn(DT_N_S_soc_S_i2c_40005800) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_usb_50000000) fn(DT_N_S_soc_S_timers_40010000) fn(DT_N_S_soc_S_timers_40010000_S_pwm) fn(DT_N_S_soc_S_rtc_40002800) fn(DT_N_S_soc_S_adc_40012000) fn(DT_N_S_soc_S_dma_40026400) fn(DT_N_S_soc_S_serial_40004800) fn(DT_N_S_soc_S_rng_50060800) fn(DT_N_S_soc_S_dac_40007400) fn(DT_N_S_soc_S_ethernet_40028000) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_power_states) fn(DT_N_S_cpus_S_power_states_S_stop) fn(DT_N_S_memory_20000000) fn(DT_N_S_clocks) fn(DT_N_S_clocks_S_clk_hse) fn(DT_N_S_clocks_S_clk_lsi) fn(DT_N_S_clocks_S_pll) fn(DT_N_S_mcos) fn(DT_N_S_power_40007000_S_wkup_pin_1) fn(DT_N_S_dietemp) fn(DT_N_S_vref) fn(DT_N_S_vbat) fn(DT_N_S_otgfs_phy) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_memory_10000000) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3) fn(DT_N_S_gpio_keys) fn(DT_N_S_gpio_keys_S_button)
#define DT_FOREACH_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7800, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_40023800, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_40023800_S_reset_controller, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_40013c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_40003000, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_40002c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005800, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005c00, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_qdec, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_qdec, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400_S_qdec, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800_S_qdec, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00_S_qdec, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_40002800, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_40002800_S_backup_regs, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40012000, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40026000, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40026400, __VA_ARGS__) fn(DT_N_S_soc_S_sdmmc_40012c00, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003c00, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013400, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40003c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40005000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010400_S_qdec, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001c00_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40040000, __VA_ARGS__) fn(DT_N_S_soc_S_can_40006400, __VA_ARGS__) fn(DT_N_S_soc_S_can_40006800, __VA_ARGS__) fn(DT_N_S_soc_S_rng_50060800, __VA_ARGS__) fn(DT_N_S_soc_S_memory_40024000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40012100, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40012200, __VA_ARGS__) fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) fn(DT_N_S_soc_S_ethernet_40028000, __VA_ARGS__) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, __VA_ARGS__) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007c00, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40015400, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_a0000000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_a0000000_S_sdram, __VA_ARGS__) fn(DT_N_S_soc_S_sai1_40015800, __VA_ARGS__) fn(DT_N_S_soc_S_sai1_40015800_S_sai1a_4, __VA_ARGS__) fn(DT_N_S_soc_S_sai1_40015800_S_sai1b_24, __VA_ARGS__) fn(DT_N_S_soc_S_display_controller_40016800, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states_S_stop, __VA_ARGS__) fn(DT_N_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lsi, __VA_ARGS__) fn(DT_N_S_clocks_S_pll, __VA_ARGS__) fn(DT_N_S_clocks_S_plli2s, __VA_ARGS__) fn(DT_N_S_clocks_S_pllsai, __VA_ARGS__) fn(DT_N_S_mcos, __VA_ARGS__) fn(DT_N_S_mcos_S_mco1, __VA_ARGS__) fn(DT_N_S_mcos_S_mco2, __VA_ARGS__) fn(DT_N_S_power_40007000, __VA_ARGS__) fn(DT_N_S_power_40007000_S_wkup_pin_1, __VA_ARGS__) fn(DT_N_S_dietemp, __VA_ARGS__) fn(DT_N_S_vref, __VA_ARGS__) fn(DT_N_S_vbat, __VA_ARGS__) fn(DT_N_S_otgfs_phy, __VA_ARGS__) fn(DT_N_S_smbus1, __VA_ARGS__) fn(DT_N_S_smbus2, __VA_ARGS__) fn(DT_N_S_smbus3, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_memory_10000000, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_gpio_keys_S_button, __VA_ARGS__)
#define DT_FOREACH_OKAY_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_vrefint_2a, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal1_2c, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout_S_ts_cal2_2e, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_40023800, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_40023800_S_reset_controller, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_40013c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_adc1_in0_pa0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_dac_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_ref_clk_pa1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdio_pa2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_crs_dv_pa7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd1_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_mdc_pc1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd0_pc4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_rxd1_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_tx_en_pg11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_eth_txd0_pg13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_scl_pb10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_i2c2_sda_pb11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_miso_pa6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_mosi_pa7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_spi1_sck_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_tim1_ch3_pe13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_rx_pd9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_rx_pg9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart3_tx_pd8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usart6_tx_pg14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_40003000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005800, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_40002800, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40012000, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40026400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004800, __VA_ARGS__) fn(DT_N_S_soc_S_rng_50060800, __VA_ARGS__) fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) fn(DT_N_S_soc_S_ethernet_40028000, __VA_ARGS__) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, __VA_ARGS__) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states_S_stop, __VA_ARGS__) fn(DT_N_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lsi, __VA_ARGS__) fn(DT_N_S_clocks_S_pll, __VA_ARGS__) fn(DT_N_S_mcos, __VA_ARGS__) fn(DT_N_S_power_40007000_S_wkup_pin_1, __VA_ARGS__) fn(DT_N_S_dietemp, __VA_ARGS__) fn(DT_N_S_vref, __VA_ARGS__) fn(DT_N_S_vbat, __VA_ARGS__) fn(DT_N_S_otgfs_phy, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_memory_10000000, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_gpio_keys_S_button, __VA_ARGS__)

/* parent NVM identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0_NVM_DEVICE DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000
#define DT_COMPAT_zephyr_mapped_partition_LABEL_mcuboot DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0
#define DT_COMPAT_zephyr_mapped_partition_LABEL_mcuboot_EXISTS 1

/* parent NVM identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000_NVM_DEVICE DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000
#define DT_COMPAT_zephyr_mapped_partition_LABEL_image_0 DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000
#define DT_COMPAT_zephyr_mapped_partition_LABEL_image_0_EXISTS 1

/* parent NVM identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000_NVM_DEVICE DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000
#define DT_COMPAT_zephyr_mapped_partition_LABEL_image_1 DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000
#define DT_COMPAT_zephyr_mapped_partition_LABEL_image_1_EXISTS 1

/* parent NVM identifier: */
#define DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000_NVM_DEVICE DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000
#define DT_COMPAT_zephyr_mapped_partition_LABEL_image_scratch DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000
#define DT_COMPAT_zephyr_mapped_partition_LABEL_image_scratch_EXISTS 1

/*
 * Macros for compatibles with status "okay" nodes
 */
#define DT_COMPAT_HAS_OKAY_st_my_nucleo_f429zi 1
#define DT_COMPAT_HAS_OKAY_st_stm32f429 1
#define DT_COMPAT_HAS_OKAY_st_stm32f4 1
#define DT_COMPAT_HAS_OKAY_simple_bus 1
#define DT_COMPAT_HAS_OKAY_arm_v7m_nvic 1
#define DT_COMPAT_HAS_OKAY_arm_armv7m_systick 1
#define DT_COMPAT_HAS_OKAY_st_stm32_flash_controller 1
#define DT_COMPAT_HAS_OKAY_st_stm32f4_flash_controller 1
#define DT_COMPAT_HAS_OKAY_st_stm32f4_nv_flash 1
#define DT_COMPAT_HAS_OKAY_st_stm32_nv_flash 1
#define DT_COMPAT_HAS_OKAY_soc_nv_flash 1
#define DT_COMPAT_HAS_OKAY_zephyr_mapped_partition 1
#define DT_COMPAT_HAS_OKAY_st_stm32_nvm_otp 1
#define DT_COMPAT_HAS_OKAY_fixed_layout 1
#define DT_COMPAT_HAS_OKAY_st_stm32f4_rcc 1
#define DT_COMPAT_HAS_OKAY_st_stm32_rcc_rctl 1
#define DT_COMPAT_HAS_OKAY_st_stm32_exti 1
#define DT_COMPAT_HAS_OKAY_st_stm32_pinctrl 1
#define DT_COMPAT_HAS_OKAY_st_stm32_gpio 1
#define DT_COMPAT_HAS_OKAY_st_stm32_watchdog 1
#define DT_COMPAT_HAS_OKAY_st_stm32_usart 1
#define DT_COMPAT_HAS_OKAY_st_stm32_uart 1
#define DT_COMPAT_HAS_OKAY_st_stm32_i2c_v1 1
#define DT_COMPAT_HAS_OKAY_st_stm32_spi 1
#define DT_COMPAT_HAS_OKAY_st_stm32_otgfs 1
#define DT_COMPAT_HAS_OKAY_st_stm32_timers 1
#define DT_COMPAT_HAS_OKAY_st_stm32_pwm 1
#define DT_COMPAT_HAS_OKAY_st_stm32_rtc 1
#define DT_COMPAT_HAS_OKAY_st_stm32f4_adc 1
#define DT_COMPAT_HAS_OKAY_st_stm32_adc 1
#define DT_COMPAT_HAS_OKAY_st_stm32_dma_v1 1
#define DT_COMPAT_HAS_OKAY_st_stm32_rng 1
#define DT_COMPAT_HAS_OKAY_st_stm32_dac 1
#define DT_COMPAT_HAS_OKAY_st_stm32_ethernet 1
#define DT_COMPAT_HAS_OKAY_st_stm32_mdio 1
#define DT_COMPAT_HAS_OKAY_snps_dwmac_mdio 1
#define DT_COMPAT_HAS_OKAY_ethernet_phy 1
#define DT_COMPAT_HAS_OKAY_arm_cortex_m4f 1
#define DT_COMPAT_HAS_OKAY_zephyr_power_state 1
#define DT_COMPAT_HAS_OKAY_zephyr_memory_region 1
#define DT_COMPAT_HAS_OKAY_mmio_sram 1
#define DT_COMPAT_HAS_OKAY_st_stm32_hse_clock 1
#define DT_COMPAT_HAS_OKAY_fixed_clock 1
#define DT_COMPAT_HAS_OKAY_st_stm32fx_pll_clock 1
#define DT_COMPAT_HAS_OKAY_st_stm32_temp_cal 1
#define DT_COMPAT_HAS_OKAY_st_stm32_vref 1
#define DT_COMPAT_HAS_OKAY_st_stm32_vbat 1
#define DT_COMPAT_HAS_OKAY_usb_nop_xceiv 1
#define DT_COMPAT_HAS_OKAY_st_stm32_ccm 1
#define DT_COMPAT_HAS_OKAY_arduino_header_r3 1
#define DT_COMPAT_HAS_OKAY_gpio_leds 1
#define DT_COMPAT_HAS_OKAY_gpio_keys 1

/*
 * Macros for status "okay" instances of each compatible
 */
#define DT_N_INST_st_my_nucleo_f429zi_NUM_OKAY 1
#define DT_N_INST_st_stm32f429_NUM_OKAY 1
#define DT_N_INST_st_stm32f4_NUM_OKAY 1
#define DT_N_INST_simple_bus_NUM_OKAY 1
#define DT_N_INST_arm_v7m_nvic_NUM_OKAY 1
#define DT_N_INST_arm_armv7m_systick_NUM_OKAY 1
#define DT_N_INST_st_stm32_flash_controller_NUM_OKAY 1
#define DT_N_INST_st_stm32f4_flash_controller_NUM_OKAY 1
#define DT_N_INST_st_stm32f4_nv_flash_NUM_OKAY 1
#define DT_N_INST_st_stm32_nv_flash_NUM_OKAY 1
#define DT_N_INST_soc_nv_flash_NUM_OKAY 1
#define DT_N_INST_zephyr_mapped_partition_NUM_OKAY 4
#define DT_N_INST_st_stm32_nvm_otp_NUM_OKAY 1
#define DT_N_INST_fixed_layout_NUM_OKAY 1
#define DT_N_INST_st_stm32f4_rcc_NUM_OKAY 1
#define DT_N_INST_st_stm32_rcc_rctl_NUM_OKAY 1
#define DT_N_INST_st_stm32_exti_NUM_OKAY 1
#define DT_N_INST_st_stm32_pinctrl_NUM_OKAY 1
#define DT_N_INST_st_stm32_gpio_NUM_OKAY 11
#define DT_N_INST_st_stm32_watchdog_NUM_OKAY 1
#define DT_N_INST_st_stm32_usart_NUM_OKAY 2
#define DT_N_INST_st_stm32_uart_NUM_OKAY 2
#define DT_N_INST_st_stm32_i2c_v1_NUM_OKAY 2
#define DT_N_INST_st_stm32_spi_NUM_OKAY 1
#define DT_N_INST_st_stm32_otgfs_NUM_OKAY 1
#define DT_N_INST_st_stm32_timers_NUM_OKAY 1
#define DT_N_INST_st_stm32_pwm_NUM_OKAY 1
#define DT_N_INST_st_stm32_rtc_NUM_OKAY 1
#define DT_N_INST_st_stm32f4_adc_NUM_OKAY 1
#define DT_N_INST_st_stm32_adc_NUM_OKAY 1
#define DT_N_INST_st_stm32_dma_v1_NUM_OKAY 1
#define DT_N_INST_st_stm32_rng_NUM_OKAY 1
#define DT_N_INST_st_stm32_dac_NUM_OKAY 1
#define DT_N_INST_st_stm32_ethernet_NUM_OKAY 1
#define DT_N_INST_st_stm32_mdio_NUM_OKAY 1
#define DT_N_INST_snps_dwmac_mdio_NUM_OKAY 1
#define DT_N_INST_ethernet_phy_NUM_OKAY 1
#define DT_N_INST_arm_cortex_m4f_NUM_OKAY 1
#define DT_N_INST_zephyr_power_state_NUM_OKAY 1
#define DT_N_INST_zephyr_memory_region_NUM_OKAY 2
#define DT_N_INST_mmio_sram_NUM_OKAY 1
#define DT_N_INST_st_stm32_hse_clock_NUM_OKAY 1
#define DT_N_INST_fixed_clock_NUM_OKAY 1
#define DT_N_INST_st_stm32fx_pll_clock_NUM_OKAY 1
#define DT_N_INST_st_stm32_temp_cal_NUM_OKAY 1
#define DT_N_INST_st_stm32_vref_NUM_OKAY 1
#define DT_N_INST_st_stm32_vbat_NUM_OKAY 1
#define DT_N_INST_usb_nop_xceiv_NUM_OKAY 2
#define DT_N_INST_st_stm32_ccm_NUM_OKAY 1
#define DT_N_INST_arduino_header_r3_NUM_OKAY 1
#define DT_N_INST_gpio_leds_NUM_OKAY 1
#define DT_N_INST_gpio_keys_NUM_OKAY 1
#define DT_FOREACH_OKAY_st_my_nucleo_f429zi(fn) fn(DT_N)
#define DT_FOREACH_OKAY_VARGS_st_my_nucleo_f429zi(fn, ...) fn(DT_N, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_my_nucleo_f429zi(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_my_nucleo_f429zi(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32f429(fn) fn(DT_N_S_soc)
#define DT_FOREACH_OKAY_VARGS_st_stm32f429(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32f429(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32f429(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32f4(fn) fn(DT_N_S_soc)
#define DT_FOREACH_OKAY_VARGS_st_stm32f4(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32f4(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32f4(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_simple_bus(fn) fn(DT_N_S_soc)
#define DT_FOREACH_OKAY_VARGS_simple_bus(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_simple_bus(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_simple_bus(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_v7m_nvic(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100)
#define DT_FOREACH_OKAY_VARGS_arm_v7m_nvic(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_v7m_nvic(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_v7m_nvic(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_armv7m_systick(fn) fn(DT_N_S_soc_S_timer_e000e010)
#define DT_FOREACH_OKAY_VARGS_arm_armv7m_systick(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_armv7m_systick(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_armv7m_systick(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_flash_controller(fn) fn(DT_N_S_soc_S_flash_controller_40023c00)
#define DT_FOREACH_OKAY_VARGS_st_stm32_flash_controller(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_flash_controller(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_flash_controller(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32f4_flash_controller(fn) fn(DT_N_S_soc_S_flash_controller_40023c00)
#define DT_FOREACH_OKAY_VARGS_st_stm32f4_flash_controller(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32f4_flash_controller(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32f4_flash_controller(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32f4_nv_flash(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000)
#define DT_FOREACH_OKAY_VARGS_st_stm32f4_nv_flash(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32f4_nv_flash(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32f4_nv_flash(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_nv_flash(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000)
#define DT_FOREACH_OKAY_VARGS_st_stm32_nv_flash(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_nv_flash(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_nv_flash(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_soc_nv_flash(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000)
#define DT_FOREACH_OKAY_VARGS_soc_nv_flash(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_soc_nv_flash(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_soc_nv_flash(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_zephyr_mapped_partition(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000)
#define DT_FOREACH_OKAY_VARGS_zephyr_mapped_partition(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_20000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_60000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_8000000_S_partitions_S_partition_a0000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_zephyr_mapped_partition(fn) fn(0) fn(1) fn(2) fn(3)
#define DT_FOREACH_OKAY_INST_VARGS_zephyr_mapped_partition(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__) fn(3, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_nvm_otp(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00)
#define DT_FOREACH_OKAY_VARGS_st_stm32_nvm_otp(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_nvm_otp(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_nvm_otp(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_fixed_layout(fn) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout)
#define DT_FOREACH_OKAY_VARGS_fixed_layout(fn, ...) fn(DT_N_S_soc_S_flash_controller_40023c00_S_flash_1fff7a00_S_nvmem_layout, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_fixed_layout(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_fixed_layout(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32f4_rcc(fn) fn(DT_N_S_soc_S_rcc_40023800)
#define DT_FOREACH_OKAY_VARGS_st_stm32f4_rcc(fn, ...) fn(DT_N_S_soc_S_rcc_40023800, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32f4_rcc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32f4_rcc(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_rcc_rctl(fn) fn(DT_N_S_soc_S_rcc_40023800_S_reset_controller)
#define DT_FOREACH_OKAY_VARGS_st_stm32_rcc_rctl(fn, ...) fn(DT_N_S_soc_S_rcc_40023800_S_reset_controller, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_rcc_rctl(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_rcc_rctl(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_exti(fn) fn(DT_N_S_soc_S_interrupt_controller_40013c00)
#define DT_FOREACH_OKAY_VARGS_st_stm32_exti(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_40013c00, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_exti(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_exti(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_pinctrl(fn) fn(DT_N_S_soc_S_pin_controller_40020000)
#define DT_FOREACH_OKAY_VARGS_st_stm32_pinctrl(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_pinctrl(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_pinctrl(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_gpio(fn) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800)
#define DT_FOREACH_OKAY_VARGS_st_stm32_gpio(fn, ...) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40020c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40021c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_40020000_S_gpio_40022800, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_gpio(fn) fn(0) fn(1) fn(2) fn(3) fn(4) fn(5) fn(6) fn(7) fn(8) fn(9) fn(10)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_gpio(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__) fn(3, __VA_ARGS__) fn(4, __VA_ARGS__) fn(5, __VA_ARGS__) fn(6, __VA_ARGS__) fn(7, __VA_ARGS__) fn(8, __VA_ARGS__) fn(9, __VA_ARGS__) fn(10, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_watchdog(fn) fn(DT_N_S_soc_S_watchdog_40003000)
#define DT_FOREACH_OKAY_VARGS_st_stm32_watchdog(fn, ...) fn(DT_N_S_soc_S_watchdog_40003000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_watchdog(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_watchdog(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_usart(fn) fn(DT_N_S_soc_S_serial_40011400) fn(DT_N_S_soc_S_serial_40004800)
#define DT_FOREACH_OKAY_VARGS_st_stm32_usart(fn, ...) fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004800, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_usart(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_usart(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_uart(fn) fn(DT_N_S_soc_S_serial_40011400) fn(DT_N_S_soc_S_serial_40004800)
#define DT_FOREACH_OKAY_VARGS_st_stm32_uart(fn, ...) fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004800, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_uart(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_uart(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_i2c_v1(fn) fn(DT_N_S_soc_S_i2c_40005400) fn(DT_N_S_soc_S_i2c_40005800)
#define DT_FOREACH_OKAY_VARGS_st_stm32_i2c_v1(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005800, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_i2c_v1(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_i2c_v1(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_spi(fn) fn(DT_N_S_soc_S_spi_40013000)
#define DT_FOREACH_OKAY_VARGS_st_stm32_spi(fn, ...) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_spi(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_spi(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_otgfs(fn) fn(DT_N_S_soc_S_usb_50000000)
#define DT_FOREACH_OKAY_VARGS_st_stm32_otgfs(fn, ...) fn(DT_N_S_soc_S_usb_50000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_otgfs(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_otgfs(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_timers(fn) fn(DT_N_S_soc_S_timers_40010000)
#define DT_FOREACH_OKAY_VARGS_st_stm32_timers(fn, ...) fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_timers(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_timers(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_pwm(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm)
#define DT_FOREACH_OKAY_VARGS_st_stm32_pwm(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_pwm(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_pwm(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_rtc(fn) fn(DT_N_S_soc_S_rtc_40002800)
#define DT_FOREACH_OKAY_VARGS_st_stm32_rtc(fn, ...) fn(DT_N_S_soc_S_rtc_40002800, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_rtc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_rtc(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32f4_adc(fn) fn(DT_N_S_soc_S_adc_40012000)
#define DT_FOREACH_OKAY_VARGS_st_stm32f4_adc(fn, ...) fn(DT_N_S_soc_S_adc_40012000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32f4_adc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32f4_adc(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_adc(fn) fn(DT_N_S_soc_S_adc_40012000)
#define DT_FOREACH_OKAY_VARGS_st_stm32_adc(fn, ...) fn(DT_N_S_soc_S_adc_40012000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_adc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_adc(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_dma_v1(fn) fn(DT_N_S_soc_S_dma_40026400)
#define DT_FOREACH_OKAY_VARGS_st_stm32_dma_v1(fn, ...) fn(DT_N_S_soc_S_dma_40026400, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_dma_v1(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_dma_v1(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_rng(fn) fn(DT_N_S_soc_S_rng_50060800)
#define DT_FOREACH_OKAY_VARGS_st_stm32_rng(fn, ...) fn(DT_N_S_soc_S_rng_50060800, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_rng(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_rng(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_dac(fn) fn(DT_N_S_soc_S_dac_40007400)
#define DT_FOREACH_OKAY_VARGS_st_stm32_dac(fn, ...) fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_dac(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_dac(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_ethernet(fn) fn(DT_N_S_soc_S_ethernet_40028000)
#define DT_FOREACH_OKAY_VARGS_st_stm32_ethernet(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_ethernet(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_ethernet(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_mdio(fn) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio)
#define DT_FOREACH_OKAY_VARGS_st_stm32_mdio(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_mdio(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_mdio(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_snps_dwmac_mdio(fn) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio)
#define DT_FOREACH_OKAY_VARGS_snps_dwmac_mdio(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_snps_dwmac_mdio(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_snps_dwmac_mdio(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_ethernet_phy(fn) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0)
#define DT_FOREACH_OKAY_VARGS_ethernet_phy(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio_S_ethernet_phy_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_ethernet_phy(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_ethernet_phy(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_cortex_m4f(fn) fn(DT_N_S_cpus_S_cpu_0)
#define DT_FOREACH_OKAY_VARGS_arm_cortex_m4f(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_cortex_m4f(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_cortex_m4f(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_zephyr_power_state(fn) fn(DT_N_S_cpus_S_power_states_S_stop)
#define DT_FOREACH_OKAY_VARGS_zephyr_power_state(fn, ...) fn(DT_N_S_cpus_S_power_states_S_stop, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_zephyr_power_state(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_zephyr_power_state(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_zephyr_memory_region(fn) fn(DT_N_S_memory_20000000) fn(DT_N_S_memory_10000000)
#define DT_FOREACH_OKAY_VARGS_zephyr_memory_region(fn, ...) fn(DT_N_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_memory_10000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_zephyr_memory_region(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_zephyr_memory_region(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_mmio_sram(fn) fn(DT_N_S_memory_20000000)
#define DT_FOREACH_OKAY_VARGS_mmio_sram(fn, ...) fn(DT_N_S_memory_20000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_mmio_sram(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_mmio_sram(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_hse_clock(fn) fn(DT_N_S_clocks_S_clk_hse)
#define DT_FOREACH_OKAY_VARGS_st_stm32_hse_clock(fn, ...) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_hse_clock(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_hse_clock(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_fixed_clock(fn) fn(DT_N_S_clocks_S_clk_lsi)
#define DT_FOREACH_OKAY_VARGS_fixed_clock(fn, ...) fn(DT_N_S_clocks_S_clk_lsi, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_fixed_clock(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_fixed_clock(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32fx_pll_clock(fn) fn(DT_N_S_clocks_S_pll)
#define DT_FOREACH_OKAY_VARGS_st_stm32fx_pll_clock(fn, ...) fn(DT_N_S_clocks_S_pll, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32fx_pll_clock(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32fx_pll_clock(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_temp_cal(fn) fn(DT_N_S_dietemp)
#define DT_FOREACH_OKAY_VARGS_st_stm32_temp_cal(fn, ...) fn(DT_N_S_dietemp, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_temp_cal(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_temp_cal(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_vref(fn) fn(DT_N_S_vref)
#define DT_FOREACH_OKAY_VARGS_st_stm32_vref(fn, ...) fn(DT_N_S_vref, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_vref(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_vref(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_vbat(fn) fn(DT_N_S_vbat)
#define DT_FOREACH_OKAY_VARGS_st_stm32_vbat(fn, ...) fn(DT_N_S_vbat, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_vbat(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_vbat(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_usb_nop_xceiv(fn) fn(DT_N_S_otgfs_phy) fn(DT_N_S_otghs_fs_phy)
#define DT_FOREACH_OKAY_VARGS_usb_nop_xceiv(fn, ...) fn(DT_N_S_otgfs_phy, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_usb_nop_xceiv(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_usb_nop_xceiv(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_ccm(fn) fn(DT_N_S_memory_10000000)
#define DT_FOREACH_OKAY_VARGS_st_stm32_ccm(fn, ...) fn(DT_N_S_memory_10000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_ccm(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_ccm(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arduino_header_r3(fn) fn(DT_N_S_connector)
#define DT_FOREACH_OKAY_VARGS_arduino_header_r3(fn, ...) fn(DT_N_S_connector, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arduino_header_r3(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arduino_header_r3(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_gpio_leds(fn) fn(DT_N_S_leds)
#define DT_FOREACH_OKAY_VARGS_gpio_leds(fn, ...) fn(DT_N_S_leds, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_gpio_leds(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_gpio_leds(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_gpio_keys(fn) fn(DT_N_S_gpio_keys)
#define DT_FOREACH_OKAY_VARGS_gpio_keys(fn, ...) fn(DT_N_S_gpio_keys, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_gpio_keys(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_gpio_keys(fn, ...) fn(0, __VA_ARGS__)

/*
 * Bus information for status "okay" nodes of each compatible
 */
#define DT_COMPAT_ethernet_phy_BUS_mdio 1

/* Bus info (controller: '/soc/ethernet@40028000/mdio', bus: 'mdio') */

/* Includes descendants on this bus, excludes devices behind child buses */
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_DESCENDANT_NUM_ON_BUS_mdio 1
#define DT_N_S_soc_S_ethernet_40028000_S_mdio_DESCENDANT_NUM_ON_BUS_mdio_STATUS_OKAY 1
